(8th Semester) Project Report

Nirma Institute of Technology ( Approved by All India Council for Technical Education – New Delhi and Affiliated to Gujarat University, Ahmedabad )

Gandhinagar-Sarkhej Highway Tragad Patia, Post-Chandlodia, Via-Gota, Chharodi, Ahmedabad-382481. Ph.: (079) 3741911-15 Fax : (079) 3741917 E-mail : [email protected]

CERTIFICATE This is to certify that the under mentioned students of B.E. IV, Semester VIII, (Instrumentation and Control), Nirma Institute of Technology, have been working on the project titled ‘Autonomous and Semi-autonomous Robots for Coordinated Task Solving (Robocon 2004)’ at Nirma Institute of Technology under my guidance for the fulfillment of their curriculum requirement, since December, 2003. They have been regular, sincere and hard working to try and successfully completed their project assignment. Abhijit Karnik Harsh Satyapanthi

Prof. B. B. Kadam Project Guide and Coordinator Robocon 2004 Nirma Institute of Technology

DATE:

CERTIFICATE NIRMA INSTITUTE OF TECHNOLOGY AHMEDABAD

I hereby certify that the following students of B.E. IV, Semester VIII, Instrumentation and Control have satisfactorily completed their project on ‘AUTONOMOUS AND SEMI-AUTONOMOUS ROBOTS FOR COORDINATED TASK SOLVING (ROBOCON 2004)’ at

NIRMA INSTITUTE OF TECHNOLOGY

SR. NO.

NAME

ROLL NO.

1

ABHIJIT KARNIK

00IC28

2

HARSH SATYAPANTHI

00IC44

(Mr. Vaibhav Gandhi) INTERNAL GUIDE

DATE:

(Dr. M.D. Desai) HEAD OF THE ELECTRICAL ENGINEERING DEPARTMENT

Project Report 8th Sem. I.C.

ACKNOWLEDGEMENT: As students of the final year of engineering (Instrumentation & Control), we are required to undertake a project as a part of our curriculum. Our project for 8th Semester is titled

“AUTONOMOUS

AND

SEMI-AUTONOMOUS

ROBOTS

FOR

COORDINATED TASK SOLVING”. Herewith is encapsulated a report of the same. In our attempt, we have come to realize that robotics is a field which is not just an isolated field on its own. It is the synthesis of a number of concepts from all the major engineering fields. Hence our journey has had a number of guides, each one from a different field. In submitting this report, we, the undersigned, would like to take the opportunity to thank all these people, without whose help our modest endeavor would never have seen the light of the day. Thereby we take immense pleasure in thanking Prof. B. B. Kadam (Prof. Electrical Dept.) who is our guide, Dr. M.D. Desai (HOD, Electrical Dept.), Mr. Vaibhav Gandhi (Lecturer, IC Dept., & Internal Guide), Prof. D. M. Adhyaru (Asst. Prof., IC Dept.), Ms. Gauri Mudaliar (Lecturer, Mechanical Dept.), Mr. Chintan Bhatt (Lecturer, IC Dept.), Mr. Sachin Gajjar (Lecturer, EC Dept.), Mr. Dishang Trivedi (Lecturer, Electrical Dept.), Mr. H.K. Patel (Lecturer, IC Dept.), Mr. Navinbhai Shah (Applications Engineers). We would also like to acknowledge the enthusiastic support that was given to us by the management of college and faculty of I.C. Dept., who not only gave us moral support but were actively interested in our project through all its ups and downs. Last but not the least; we would like to acknowledge the unquestioning and tireless support from our families.

Abhijit Karnik Harsh Satyapanthi

Nirma Institute of Technology

Project Report 8th Sem. I.C.

FOREWORD: The word robot was coined by the Czech writer Kapek in his play ‘Rossum's Universal Robots’. Since then countless devices have been created and have been associated with the word ‘Robot’. The works of Isaac Asimov have laid the foundation of sociology pertaining to the use of robots instead of humans and the word ‘Robotics’ was also coined by him. In today’s world, work on robots, that resemble and look almost human, and others which don’t resemble humans in any way, progresses in leaps and bounds. The world has forerunners in this technology like MIT, CMU, Sony, Honda etc. In this world of ASIMO, AIBO, Packbot etc., we have made an attempt to create machines which we dare call ‘Robots’.

In this era where organizations like ABU – Asia Pacific Broadcasting Union are organizing robot contests like Robocon we have made an attempt to make robotic systems which could send and receive communication signal amongst them and complete the task assigned to them with coordinated efforts. Today when technology is developing faster then a blink of an eye and the competition is tough to win at any stage may it be national or international, we have put in tireless efforts to implement the technology in simpler and effective form to compete against some of the best in field of robotics in the country.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

INTRODUCTION: This report is the documentation of all the efforts put into the making of Autonomous and Semi-autonomous Robots by us as the Participating Team Members of Robocon 2004 Team of Nirma Institute of Technology. The title of the project was coined as:

‘Autonomous and Semi-autonomous Robots for Coordinated Task Solving’, These robots are targeted to perform a coordinated task in the Game Arena of Robocon ’04 where the task to be performed is common for all the participant teams from all the institutions and nations. This report explains the technology and heuristics involved in making of the robots and how the task is planned to be completed using the same. The report is divided into 6 sections. Each section deals with the project from a different viewpoint. The first section deals with the explanation of the Contest Theme of Robocon 2004 and pertaining details. The second section deals with the purpose of the robots and the features included in the robots. The third section deals with the operational description of the different modules of the robot which thereby allow the proper functioning of the features that we have planned to implement on the robot. The fourth section is the hardware and software section wherein the mind and the nerve control of the robot is explained. The fifth section explains how the research and development as well as heuristics and ideas have played a major role in shaping up this project. The last section is the annexure containing the selected sections of the datasheets of the electronic components used in our project, bibliography and the information about the sources of the systems components.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

SECTION 1 ABU – Asia Pacific Robot Contest Robocon 2004 Seoul The ABU – Asia Pacific Broadcasting Union has been organizing the Asia Pacific Robot Contest since 2002 which is better known as ‘Robocon’ in which the teams from the member nations of the Asia Pacific Broadcasting Union participate. This contest is being organized in order to create the awareness for the field of Robotics amongst the students at undergraduate level. The undergraduate students are encouraged to participate and finally take interest and contribute to the field of Robotics. The contest is held first at the National level in all the participating countries. In the national level contest the teams or undergraduate students from various colleges and institutions participate and the winning team of the contest represents the country at the international level. For the contest a theme and rules are declared by the Robocon Committee and the theme and ruler remain common for all the competitions at national levels in various countries as well as for the international contest. Robocon 2004 will be the third consecutive time this contest will take place. Robocon 2004 is to be held in Seoul, Korea and the Theme and Rules of the contest are mentioned next.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Theme and Rules – Robocon 2004 Seoul The aim of this robot contest is to make machines by hand from design to construction which will be most suitable to compete in the below contest theme and rules. Reunion of Separated Lovers, ‘Gyeonwoo and Jiknyeo’ The theme of this contest is based on a love story in Asian legend. A couple called ‘Gyeonwoo & Jiknyeo’ are forced to be apart from each other with the Milky Way between them due to their laziness. Magpies and crows which feel sorry for the couple fly up to the sky and build a bridge with their bodies to get the couple together. It is called ‘Ojak Bridge’ (Bridge of Crow and Magpie). The couple get together by crossing ‘Ojak Bridge’ once a year, on July 7th by lunar calendar. It always rains on this day and we say that it is the tears of joy from Gyeonwoo and Jiknyeo for their reunion. The aim of this contest is to compete for accomplishing “Reunion” by completing the unfinished bridge and carrying Golden Gift by Automatic Machine from “Gyeonwoo Zone (Zone A)” to “Jiknyeo Zone (Zone B)”. The duration of each match is three minutes.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

1. THE GAME FIELD The following three pages show and explain the layout and details of the Game Field to on which the contest takes place.

2. OBJECTS (GIFT/GOLDEN GIFT/BRIDGE) The details pertaining to the Gift, Golden Gift and the Bridge and Bridge parts are also mentioned in the floor plan and layout of the game field in the following three pages.

Nirma Institute of Technology

Big Bridge Part (EPS) 3.2 0.1 kg

Game Field

Smaller Bridge Part (EPS) Small Bridge Part (EPS)

Big Bridge Part (EPS)

Big Bridge Part (EPS)

Jiknyeo's Hands Jiknyeo Zone (Zone B)

Manual Machine Common Zone 2 Point Scoring Bin

Ojak Bridge

Red Milky Way Zone Blue Milky Way Zone

Gyeonwoo Zone (Zone A)

1 Point Scoring Bin

Golden Gift (EPS) 2.3 0.1 kg Gift (EPS) 0.4 0.05 kg

Red Manual Machine Start Zone

Red Automatic Machine Start Zone

Blue Manual Machine Start Zone

Blue Automatic Machine Start Zone

Project Title

ABU Asia-Pacific Robot Contest 2004 Seoul "Reunion of Separated Lovers, Gyeonwoo & Jiknyeo " SCALE:

SHEET 1 OF 3

A3

Game Field (Dimension) 1000

1000

100

14

2900

40 0

896.25

00

500

100

100

30

2000

10

14. 25°

14 .25

°

100

14000

14.25°

1/5

100

1000

Inner Wall

500

1000

3

600

400 Outer Wall 50

500

1200

1200

Inner Wall 100 1950

50

5000

Outer Wall 150

14000

Project Title

ABU Asia-Pacific Robot Contest 2004 Seoul "Reunion of Separated Lovers, Gyeonwoo & Jiknyeo " SCALE:

SHEET 2 OF 3

A3

Gyeonwoo Zone 500

500

500

500

500

500

500

500

500

500

500

500

500

500

500

500

500

500

500

485

1000

485 1000

500

500

Fixed Ojak Bridge

Gift

200

500

1500

200

500

5000

500

500

1000

500

500

500

10000

400

1500

500

1200

500

500

400

Golden Gift 800

10000

400

1200 600

1200

Big Bridge Part

415 385 00 20 0 140 0 4 0

Small Bridge Part

600

Jiknyeo Zone

385

Smaller Bridge Part

400

2 Point Scoring Bin

100

3

1 Point Scoring Bin

100

500

10

1000

Mark for Gift Position 10 mm wide non-shiny vinyl tape Project Title in the same color as Gyeonwoo Zone (Zone A)ABU Asia-Pacific Robot Contest 2004 Seoul "Reunion of Separated Lovers, Gyeonwoo & Jiknyeo " 30 mm wide white guideline SCALE:

SHEET 3 OF 3

A3

Project Report 8th Sem. I.C.

3. MACHINES Each team must design and construct either or both handmade Manual Machine and Automatic Machine(s) to compete in the contest. There is no restriction in the number of Automatic Machine(s) but ONLY ONE Manual Machine is allowed to each team. (1) Manual Machine a. Manual Machine has to be operated via remote control using cable connected to the Manual Machine or remote control using infrared rays, visible rays or sound waves. Radio waves are not allowed. Operators are not allowed to ride on the machines. b. When operating via cable, the connecting point between the Machine and the control box must be placed at least 1000 mm above the ground. Also the length of the cable from the Manual Machine to the control box must not exceed 3000 mm. c. The team members are not allowed to operate the machines or touch the materials placed on the game field by using cable. d. Manual Machine or its operator cannot touch “Gyeonwoo Zone (Zone A)’s floor and extend over into “Jiknyeo Zone (Zone B)”. e. Manual Machine cannot touch the boundary lines or extend over the opponent’s “Milky Way Zone”. f. Manual Machine cannot touch its own team’s Automatic Machines. g. Manual Machine is allowed to send a signal to an Automatic Machine only once for communication. (2) Automatic Machine(s) a. Automatic Machines have to be autonomous. b. Everything separated from an automatic machine is considered to be another automatic machine, so it must work as an automatic machine. c. Automatic Machines are allowed to go into any zones except for the opponent’s “Gyeonwoo Zone (Zone A)”. d. There is no time restriction for the start of Automatic Machines. In other words, each Automatic Machine can be started at a different time after a game begins. e. Once a machine starts, the team members are not allowed to touch the machine. But, after a team calls for a “retry” and the referee grants it, Nirma Institute of Technology

Project Report 8th Sem. I.C.

all the team are allowed to reset and restart any Automatic Machines from the start zone. f. “Retry” is permitted only once per game for each team. (3) Method of Control a. Only one operator for each team is allowed to control Manual Machine in the game field. b. The Automatic Machine operators are allowed to enter the game field only when they start the machines including a “retry”. c. Each Automatic Machine must be started by one operation. (4) Power Supply a. Each team shall prepare its own power source for all its machines during the games. b. Voltage of the machines’ electrical power source must be below DC24 V. c. Power source that is considered dangerous or unsuitable by the committee shall not be permitted. (5) Weight a. The total sum of weight of all machines must not exceed 50 kg. b. The total weight includes the weight of power sources, cables, remote controller and other parts of the machines. (6) Size a. The total size of Automatic Machines has to fit in the size of 1200 mm x 1200 mm x 1500 mm at the Start Zone. b. After the game begins, Automatic Machines can be separated and the sizes can be changed freely. c. The Manual Machine has to fit in the size of 1200 mm x 1200 mm x 1500 mm at the Start Zone. d. After the game begins, the size of Manual Machine can be changed freely, but it cannot be separated.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Apart from the mentioned technical details in the report there are other numerous facts like scoring methodology, limitations of the robots, violations in the game, decision of winner etc. that could matter during each game to be played for 3 minutes. The details pertaining to the same could be obtained from the following sources. ü

QUESTIONS REGARDING THEME AND RULES

Questions regarding theme and rules should be addressed by e-mail to the Committee in English. E-mail: [email protected] ‘ABU Robocon 2004 Seoul’ http://www.abu.org.my/programme/robocon/robocon.htm http://www.kbs.co.kr/aburobocon2004 The Contest Rules designed by KBS Technical Advisor Group Prof. Chong Nam Chu, Seoul National University Prof. Dong Sam Park, University of Incheon Dr. Young Soo Lee, Seoul National University Mr. Min Soo Park, Seoul National University & ABU Contest Committee

Nirma Institute of Technology

Project Report 8th Sem. I.C.

SECTION 2 PROJECT OBJECTIVES: As the title of the project along with the game theme suggests there are in total four robots planned to be placed into the game field in order to complete the required task. For the proper execution of the strategy for the game the robots are require to work in coordination and thus the robots are made capable to communicate amongst themselves as well. The four robots could be classified into two categories as mentioned below: 1. Semi-autonomous (Manual) Robot

-

1

2. Autonomous Robots

-

3

Semi-autonomous (Manual) Robot – Viswakarma: The manual robot is actually the semi-autonomous robot mentioned in the title which is controlled using a control box attached to the system through cables. There are various controls in the robot and the electronic system is designed to work in full manual mode or semi-autonomous manual mode. Various features of the manual robot are mentioned here: ü

Locomotion Module using Parallel H-Bridge Drive

ü

Scissor Mechanism for Single or Half Bridge Part Gripping

ü

Lead screw Mechanism for Gripping of two stacked Bridge Parts

ü

Hoist Mechanism for Gripped Bridge Parts

ü

Flap Mechanism for Reference and Bridge Completion

ü

Signaling Mechanism for Intra robot Communication

ü

Feedback Mechanisms using Limit Switches

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Autonomous Robots: There are three fully autonomous robots planned to operate in the automatic machine zone. These three autonomous robots and their features are mentioned here:

Kuber – The Golden Gift Career: This autonomous robot is designed to grip the Golden Gift placed at the center of the automatic zone and carry it over the bridge to the Jiknyeo’s hands and accomplish the reunion. Various features of the robot are:

ü

Line Following and Turning

ü

Rotary Switch Feedback in Sweeper Mechanism

ü

Vacuum Gripper Mechanism

ü

Serial Interface for Program Modification

ü

Status Monitoring Module using Serial Interface and LCD

Natraj – The Point Scoring Robot: This autonomous robot is designed to gather one after another 11 gifts from various places in the automatic zone into its helical structure and finally deploy the gifts into the 1 point scoring bin and 2 point scoring bin in order to score points. Various features of the robot are:

ü

Line Following and Turning

ü

Rotary Switch Feedback Mechanism in the Rotating Center Shaft

ü

Gift Intake and Gift Delivery Mechanism

Nirma Institute of Technology

Project Report 8th Sem. I.C. ü

Serial Interface for Program Modification

ü

Status Monitoring Module using Serial Interface and LCD

Ganesh – The Multipurpose Robot: This autonomous robot is designed to be a multipurpose robot which could be used as a test platform for testing of various programs as well as it could also be used to perform tasks like gift pick n place and for defense against the attack from opponent’s automatic robots. Various features of the robot are:

ü

Line Following and Turning

ü

Mechanism for Defense

ü

Serial Interface for Program Modification

Nirma Institute of Technology

Project Report 8th Sem. I.C.

SECTION 3 Function Description:

Various functions of the Semi-autonomous robot are described in the following part of the section.

Locomotion Module Using Parallel H-Bridge Drive: This is a very specific feature incorporated in the manual robot due to the high current requirement of the motors. The Swiss make Faulhaber Motors used for the locomotion module of the manual robot require high current of above 3 A per motor where the limitation of the H-Bridge IC LMD18200 comes into picture. This IC could withstand the maximum current of 3 A. Thus two such ICs have been paralleled in order to provide the sufficient drive current to one motor without damaging the IC or the circuitry. In this case the control signals and the supply signals to the IC are the same and their outputs are connected so that the motors are supplied sufficient current for full high speed drive.

Scissor Mechanism for Single or Half Bridge Part Gripping: As per the game theme a total of six bridge parts are required by both the teams for the completion of the bridge of both the teams but the available full bridge parts are only five. Thus one of the team might have to use two half bridge parts for the completion of the bridge gap. Scissor Mechanism is specially designed for the same. It is capable to grip a single bridge part or two half bridge parts individually. This mechanism is controlled using rack n pinion motors used for the automatic door locks of the cars.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Lead screw Mechanism for Gripping of two stacked Bridge Parts: The stacks of two bridge parts at the extremes of the manual machine common zone would be used to fill up the remaining two gaps of the bridge. These two bridge parts would be gripped using a gripper with lead screw mechanism that uses high torque geared motors to rotate the lead screw and grip the stacked bridge parts.

Hoist Mechanism for Gripped Bridge Parts: For hoisting the gripped single or half bridge parts thread and pulley are used where the thread is attached with the high torque geared motor that pulls the thread and the scissor mechanisms are hoisted along with the bridge part or parts.

Flap Mechanism for Reference and Bridge Completion: The rotating flaps connected to the slow speed motors are provided on the rear side of the robot in order to have the reference from the wall so that the bridge parts are gripped at their centers of gravity as well as while the bridge parts are filled into the bridge gaps they could be filled properly.

Signaling Mechanism for Intra robot Communication The manual robot equipped with a signaling device so that when it completes the bridge, it could signal the automatic robots to continue their tasks further. For the same the a laser signaling device is mounted onto the robot which while signaling covers a specific range of angle in order to send the signal to the automatic robot.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Feedback Mechanisms using Limit Switches As mentioned the manual robot is planned to be semi-autonomous as well. For the same purpose there are various limit switches mounted onto the robot at various places which shall detect the positions of the moving parts of the robots such as hoist mechanism, flaps etc. The on and off signals from the switches going to the microcontroller shall automatically decide the next operation of the robot. In this case the manual controller shall not have to control anything apart from the drive of the robot.

Various features of the autonomous robots are further discussed in the following part of the section.

Line Following and Turning The autonomous robots are required to perform their respective tasks without any manual guidance. Thus the technique used to make the robots reach the desired locations in order to perform their tasks is the white line following, cross detection and turning technique using the optoelectronic sensors. These optoelectronic sensors are actually developed during the project using light to voltage converter IC – OPT101 and LED. These sensors work on the principle of reflective light amplification. The IC – OPT101 comprised of a photodiode and amplifier. The light of LED reflects from the surface and falls on to the OPT101 which is amplified by the amplifier inbuilt the IC. The intensity of the light falling onto the photodiode of IC depends upon the color of the surface. Thus while the sensor is on the white line it gives the saturated output voltage where as while not on the white line it gives a low voltage. This voltage is converted into a digital signal using an analog comparator IC TLC393

Nirma Institute of Technology

Project Report 8th Sem. I.C.

where the second input to the IC is a fixed voltage. Thus when the output voltage of the sensor is below certain level i.e. when the sensor is not on white line it gives ‘0’ as the output whereas if the output voltage of the sensor is above certain level i.e. when the sensor is on the white line it gives ‘1’ as the output. Using six such sensors divided into two rows on in front and one at the rear side the white line following is achieved. To make the robot follow the white line various sequences of the possible states of the sensors are considered and depending upon the same, position of the robot and correction required in the proper direction is analyzed. Finally on the basis of the required correction, PWM signal is applied to the H-Bridge drive circuit which uses LMD18200T IC, and the straight line is followed by the robot. For the motion of the robot high torque Maxon Motors are used with the gearbox having 1:18 ratio of gear reduction. While the robot follows the white line it is also required for the robot to take 90 degree turn in certain direction. For the same the cross detection is used in which the robot counts the number of crosses in the grid it passes and when this number matches with the number of cross where it has to turn or stop, the robot stops the straight line motion and the by rotating both the motors in the opposite directions it takes the turn in the desired direction till the desired sensor in the front line of the sensors come onto the white line.

Rotary Switch Feedback Mechanism This is a very special feature introduced in the robots in order to reduce the weight and complexity involved in implementing the stepper motors. This mechanism is used wherever a part of the robot is desired to be rotated only till certain position is achieved or only by certain angle. In this mechanism the shaft of a 12 position rotary switch is coupled with the rotating member of the robot so that the rotary switch also turns by the angle the rotating

Nirma Institute of Technology

Project Report 8th Sem. I.C.

member of the robot rotates. During the same process the position of the rotary switch is read by the microcontroller and as per the program whenever the rotating element of the robot reaches the desired position the pertaining position of the rotary switch is read and the motor is stopped immediately.

Vacuum Gripper Mechanism Vacuum Gripper is a unique feature incorporated in the golden gift carrying autonomous robot. In this mechanism a vacuum gripper is used to pick up the golden gift and this vacuum gripper is actuated using a lead screw mechanism. The prerequisite for generating vacuum and gripping the gift is that the gripper tool should be in contact with the surface to be gripped with sufficient pressure and to generate the same another lead screw mechanism is used which brings the gripping surface of the gripper tool and the surface of the gift to be gripped in contact with each other with sufficient pressure required to generate vacuum and grip the gift.

Serial Interface for Program Modification and Status Monitoring Serial Interface between the Microcontroller and the Computer is established in order to update the microcontroller program as well as to monitor the status of various sensors and switches etc. on the robot. This serial communication between the microcontroller and the computer is done using the trial version of the Procomm Software. Serial communication allows the operator to monitor the status of various parts of the robot especially sensors, limit switches etc. and accordingly verify the functioning of the robot and its electronic circuitry. This also allows the operators to update the microcontroller program very fast without detaching it from the circuit as the time between the two games shall be very less and the program might be required to be changed as per the change in the strategy for the game.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Status Monitoring using LCD For the status monitoring purpose apart from the serial interface LCD also is used. When the computer is not available nearby the testing area of the robot to monitor the status of various sensors and limit switches mounted on the robots, LCD interface is used.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

SECTION 4 HARDWARE & SOFTWARE

Nirma Institute of Technology

Project Report 8th Sem. I.C.

SOFTWARE The software programs for the microcontroller have been developed using Assembly Level Programming language. Microcontroller used in the project is DS89C420 manufactured by Dallas Semiconductor which is 8052 based microcontroller. Thus for microcontroller software programming Evaluation Version of Assembler – 8051IDE developed by AceBus has been used to assemble, compile and simulate the software programs. The benefit of using DS89C420 microcontroller is that it has a 16kb of Flash Memory for programs, 1kb of RAM and 256 bytes of SRAM and also for loading the program into the microcontroller flash memory self developed serial programmer could be used and the programming is fast due to flash memory. For loading the program from the computer to the microcontroller through serial programmer the MTK – Microcontroller Tool Kit developed by Dallas Semiconductors has been used.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

LCD Interface The LCD interface has been developed in order to monitor the status of various components, sensors, switches on the robot as well as for microcontroller operation. The test software for the 16x2 Matrix Intelligent LCD interface with microcontroller is shown here.

;CONTROL LINES RS EQU P1.0 RW EQU P1.1 EN EQU P1.2 ;DATA PORT --> P3 ORG 0000 START: MOV SP,#80H LCALL PORTCONFIG LCALL READY MOV A,#'R' LCALL DISP MOV A,#'O' LCALL DISP MOV A,#'B' LCALL DISP MOV A,#'O' LCALL DISP MOV A,#'C' LCALL DISP MOV A,#'O' LCALL DISP MOV A,#'N'

Nirma Institute of Technology

Project Report 8th Sem. I.C.

LCALL DISP MOV A,#' ' LCALL DISP MOV A,#'2' LCALL DISP MOV A,#'0' LCALL DISP MOV A,#'0' LCALL DISP MOV A,#'4' LCALL DISP MOV A,#0C0H LCALL CMND MOV A,#'N' LCALL DISP MOV A,#'I' LCALL DISP MOV A,#'T' LCALL DISP PORTCONFIG: MOV P1,#00H MOV P3,#00H RET

;Configure required Ports as Input or Output

READY: ;Initialize LCD to be Ready to operate CLR RS CLR RW LCALL CHK MOV A,#80H LCALL CMND MOV A,#01H LCALL CMND MOV A,#03H LCALL CMND MOV A,#3CH LCALL CMND MOV A,#3CH LCALL CMND MOV A,#0FH LCALL CMND MOV A,#06H LCALL CMND SETB RW SETB RS RET CMND: ;Send the Command LCALL CHK MOV P3,#00H MOV P3,A

Nirma Institute of Technology

Project Report 8th Sem. I.C.

CLR RS CLR RW SETB EN CLR EN RET DISP: ;Display Character LCALL CHK MOV P3,#00H MOV P3,A SETB RS CLR RW SETB EN CLR EN RET CHK: ;Check the Busy Flag CLR RS SETB RW MOV P3,#0FFH CNT: CLR EN SETB EN JB P3.7,CNT CLR EN MOV P3,#00H RET END

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Serial Interface The Serial Interface is found easier and more suitable for status monitoring as it could also be used for program modification. Thus compared to LCD Serial Interface is much more used for program modification and status monitoring purpose. MSG HHH

DECODE1 H

DECODE2 H

DECODE3 H

PWx

PAGE

WRITE

NEW PAGE

PRH

PAGE

READ

DON'T CARE

XAx

XRAM

LOB WRITE ADDR

DATA

RXA

READ

XRAM

LOB OF ADDRESS

SAx

SRAM

LOB WRITE ADDR

DATA

RSA

READ

SRAM

LOB OF ADDRESS

ANY OTHER MESSAGE

SAMPLE COMMUNICATION: HHH THOR COMMUNICATIONS. LINK OK HOI COMMAND SYNTAX ERROR. TRY AGAIN PW2 PRF Xa99 Sb88 RXa9 RSb8 HHH THOR COMMUNICATIONS. LINK OK HYU COMMAND SYNTAX ERROR. TRY AGAIN

Nirma Institute of Technology

RESPONSE 'THOR COMMUNICATIONS. LINK OK.' SET PAGESEL=NEW ADDR SEND CONTENTS OF PAGESEL WRITE x TO PAGESEL+W. SEND CONTENTS OF PAGESEL+x WRITE X TO SRAM LOCATION A SEND CONTENTS OF SRAM LOCATION A 'COMMAND SYNTAX ERROR. TRY AGAIN'

Project Report 8th Sem. I.C.

Program ;DOCUMENTATION ;REGISTERS IN USE: ;R0 FOR COUNTING AND TRANSFERRING DATA ;T1 FOR TIMING THE 9600BPS COUNT ;ADDITIONAL ADDRESSES: ;CRITICAL ADDRESSES: ;#0160H, #0161H, #0162H FOR STORING COMMAND BEFORE PROCESSING ;#0163H, #0164H FOR STORING DPTR FOR ERR AND ACK MESSAGES ;NON-CRITICAL ADDRESSES: ;PAGESEL (41H), TEMP (42H) ;NON-CRITICAL BITS: ;ERR_ON (21H), ACK_ON (22H), P_WR (23H), VBCR (24H), VBLF (25H) ;START ADDRESS: 1000H ;END ADDRESS: 11FDH ;BYTES PAGESEL EQU 41H TEMP EQU 42H ;BITS ERR_ON EQU 21H ACK_ON EQU 22H P_WR EQU 23H VBCR EQU 24H VBLF

EQU 25H

ORG 0000H LJMP INIT ORG 0023H LJMP SER_PROC ORG 0100H

Nirma Institute of Technology

Project Report 8th Sem. I.C.

INIT:

;MASTER INIT ALGOL

MOV SP,#80H

;MASTER INIT DIRECTIVE

;>>> LCALL SI_INIT ;CALL TO MODULE 'SERIAL INTERFACE' ;>>> LJMP LOOPINF

;STANDARD IDLE LOOP

ORG 0120H LOOPINF: NOP SJMP LOOPINF ORG 1001H MSG:

DB 13,10,'THOR COMMUNICATIONS. LINK OK',13,10

ORG 1031H MSG1: DB 13,10,'COMMAND SYNTAX ERROR. TRY AGAIN',13,10 ORG 1060H SI_INIT:

;MODULE 'SERIAL INTERFACE'

ORL 0C4H, #03H

;ENABLE SRAM, LOCATION C4H BITS 0 AND 1

MOV PAGESEL,#00H CLR ERR_ON CLR ACK_ON CLR VBCR MOV R0, #60H LCALL SER_INIT RET ORG 1078H SER_INIT: ANL SCON, #00H SETB SCON.6

;SCON.7,6=01 => MODE 1

SETB SCON.4

;SCON.4=REN =>RECEIVER ENABLED

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Project Report 8th Sem. I.C.

SETB SCON.3

;SCON.3=1 =>STOP BIT =1

MOV TH1, #0FDH ;RELOAD SETTINGS FOR 9600BPS ANL TMOD, #0FH ;CLEAR ALL BITS OF TMOD FOR TIMER1 ORL TMOD, #20H ;SET TIMER1 TO MODE 2 AUTORELOAD SETB TR1

;START TIMER1

ORL IE, #90H

;SET EA=1 AND ES0=1 TO ENABLE GLOBAL AND SERIAL0

INTERRUPTS RET ORG 1098H SER_PROC: JNB RI, TXINT CLR RI MOV A, SBUF

;LOAD RECEIVED DATA

MOV DPTR, #0160H;SAVE TO #0100H+[R0] MOV DPL, R0 MOVX @DPTR, A ;SAVE TO XRAM INC R0 MOV A, R0 CJNE A, #63H, KR

;SEE IF TOTAL 3 BYTE COMMAND HAS BEEN RECVD

LCALL PROC_CMD ;IF YES PROCESS COMMAND KR:

RETI

TXINT: CLR TI

;ELSE OR THEN DO NOTHING ;CLR THE TI INTERRUPT

JNB ERR_ON, TXT1 LCALL ERR_MSG RETI TXT1: JNB ACK_ON, TXT2 LCALL ACK_MSG RETI TXT2: JNB VBCR, TXT3 SETB VBLF CLR VBCR MOV SBUF, #0DH RETI

Nirma Institute of Technology

Project Report 8th Sem. I.C.

TXT3: JNB VBLF, TXT4 CLR VBLF MOV SBUF, #0AH RETI TXT4: MOV R0, #60H RETI ORG 10D8H PROC_CMD: MOV DPTR, #0160H MOVX A, @DPTR CJNE A, #48H, PCM1

;'H'

INC DPTR MOVX A, @DPTR CJNE A, #48H, PCME

;'H'

INC DPTR MOVX A, @DPTR CJNE A, #48H, PCME

;'H'

SETB ACK_ON CLR ERR_ON MOV DPTR, #1001H XRL A, A MOVC A, @A+DPTR MOV SBUF, A LCALL SAV_DPTR RET PCM1: CJNE A, #50H, PCM2

;'P'

INC DPTR MOVX A, @DPTR CJNE A, #57H, PCM1A

;'W'

SETB P_WR LCALL PAGE_OPS RET PCM1A:

CJNE A, #52H, PCME

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;'R'

Project Report 8th Sem. I.C.

CLR P_WR LCALL PAGE_OPS RET PCM2: CJNE A, #52H, PCM3

;'R'

INC DPTR MOVX A, @DPTR CJNE A, #58H, PCM2A

;'X'

INC DPTR MOVX A, @DPTR MOV DPL, A MOV DPH, PAGESEL MOVX A, @DPTR MOV SBUF, A SETB VBCR RET PCM2A:

CJNE A, #53H, PCME

;'S'

INC DPTR MOVX A, @DPTR MOV R0, A MOV A, @R0 MOV SBUF, A SETB VBCR RET PCM3: CJNE A, #58H, PCM4

;'X' [WRITE XRAM]

INC DPTR MOVX A, @DPTR MOV TEMP, A INC DPTR MOVX A, @DPTR MOV DPL, TEMP MOV DPH, PAGESEL MOVX @DPTR, A ;WRITE TO XRAM MOVX A, @DPTR MOV SBUF, A

Nirma Institute of Technology

Project Report 8th Sem. I.C.

SETB VBCR RET PCM4: CJNE A, #53H, PCME

;'S' [WRITE SRAM]

INC DPTR MOVX A, @DPTR MOV R0, A INC DPTR MOVX A, @DPTR MOV @R0, A

;WRITE TO SRAM

MOV A, @R0 MOV SBUF, A SETB VBCR RET PCME: CLR ACK_ON

;COMMAND SYNTAX ERROR SEQUENCE

SETB ERR_ON MOV DPTR, #1031H

;ERR MSG LOCATION IS #1031H

XRL A, A MOVC A, @A+DPTR MOV SBUF, A LCALL SAV_DPTR RET ORG 1168H PAGE_OPS: JNB P_WR, POP1 INC DPTR

;CHK IF IT IS PWRITE OR PREAD CMD ;HERE IF PWRITE

MOVX A, @DPTR CJNE A, #2FH, POP1A LJMP POE POP1A: JB CY, POP1B

;[A]>#2FH THEN NO BORROW=>PROCESS 30->33H

CJNE A, #34H, POP1C LJMP POE POP1C:

JNB CY, POE CLR CY

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;[A]>#34H THEN NO BORROW=>ERROR

Project Report 8th Sem. I.C.

SUBB A, #30H ;HERE MEANS 2FH<[A]<34H LJMP POP1E POP1B: CJNE A, #04H, POP1D LJMP POE POP1D: JNB CY, POE

;[A]>#04H THEN NO BORROW=>ERROR

POP1E: MOV PAGESEL, A POP1: MOV SBUF, PAGESEL SETB VBCR RET POE: CLR ACK_ON SETB ERR_ON MOV DPTR, #1031H

;ERR MSG LOCATION IS #1031H

XRL A, A MOVC A, @A+DPTR MOV SBUF, A RET ORG 11A8H ERR_MSG: LCALL RD_DPTR INC DPL MOV A, DPL CJNE A, #54H, EMX CLR ERR_ON MOV R0, #60H ;!!!REQUIRED FOR FUTURE COMM RECEPTION RET EMX: XRL A, A MOVC A, @A+DPTR MOV SBUF, A LCALL SAV_DPTR RET ORG 11C4H ACK_MSG:

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Project Report 8th Sem. I.C.

LCALL RD_DPTR INC DPL MOV A, DPL CJNE A, #21H, AMX CLR ACK_ON MOV R0, #60H ;!!!REQUIRED FOR FUTURE COMM RECEPTION RET AMX:

XRL A, A

MOVC A, @A+DPTR MOV SBUF, A LCALL SAV_DPTR RET ORG 11E0H SAV_DPTR: MOV TEMP, DPH MOV A, DPL MOV DPTR, #0163H

;DPL IN #0163H AND DPH IN #0164H

MOVX @DPTR, A INC DPTR MOV A, TEMP MOVX @DPTR, A RET ORG 11F0H RD_DPTR: MOV DPTR, #0163H MOVX A, @DPTR

;RETRIEVE DPL

MOV TEMP, A

;SAVE TO TEMP

INC DPTR MOVX A, @DPTR MOV DPH, A

;RETRIEVE DPH ;LOAD DPH

MOV DPL, TEMP RET

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;LOAD DPL

Project Report 8th Sem. I.C.

White Line Following As mentioned earlier in the report, straight line following for the white line has been implemented for the autonomous robots in order to make them reach their desired positions in the grid of automatic zone to perform their respective tasks automatically. The test program for the same is included in the following part of the section. Here only the test program is mentioned but the optimized version of the same with more features in it also has been developed.

Program: ;BIT ALOCATIONS LDIR EQU P1.0 LDRV EQU P1.1 RDIR EQU P1.2 RDRV EQU P1.3 ORG 0000H LJMP START ORG 0100H START: LCALL PORTCONFIG SLF: MOV A,P2 CPL A MOV P3,A MOV A,P2 ANL A,#0FCH MOV R0,A MOV A,R0 CJNE A,#48H,NXT1 LJMP STRGHT NXT1: MOV A,R0 CJNE A,#4CH,NXT2 LJMP RGHT1 NXT2: MOV A,R0 CJNE A,#58H,NXT3 LJMP LEFT1 NXT3: MOV A,R0 CJNE A,#0CCH,NXT4

Nirma Institute of Technology

Project Report 8th Sem. I.C.

LJMP RGHT2 NXT4: MOV A,R0 CJNE A,#78H,NXT5 LJMP LEFT2 NXT5: MOV A,R0 CJNE A,#8CH,NXT6 LJMP RGHT3 NXT6: MOV A,R0 CJNE A,#38H,NXT7 LJMP LEFT3 NXT7: MOV A,R0 CJNE A,#0D8H,NXT8 LJMP RGHT4 NXT8: MOV A,R0 CJNE A,#98H,NXT9 LJMP RGHT5 NXT9: MOV A,R0 CJNE A,#6CH,NXT10 LJMP LEFT4 NXT10: MOV A,R0 CJNE A,#2CH,NXT11 LJMP LEFT5 NXT11: MOV A,R0 CJNE A,#64H,NXT12 LJMP RGHT6 NXT12: MOV A,R0 CJNE A,#0D0H,NXT13 LJMP LEFT6 NXT13: MOV A,R0 CJNE A,#90H,NXT14 LJMP RGHT4 NXT14: MOV A,R0 CJNE A,#24H,NXT15 LJMP LEFT4 NXT15: MOV A,R0 CJNE A,#80H,NXT16 LJMP LEFT7 NXT16: MOV A,R0 CJNE A,#10H,NXT17 LJMP RGHT8 NXT17: MOV A,R0 CJNE A,#20H,NXT18 LJMP RGHT7 NXT18: MOV A,R0 CJNE A,#04H,NXT19 LJMP LEFT8 NXT19: MOV A,R0 CJNE A,#00H,NXT20 LJMP DEFAULT NXT20: LJMP START

Nirma Institute of Technology

Project Report 8th Sem. I.C.

PORTCONFIG: MOV P1,#00H MOV P2,#0FFH MOV P3,#0FFH RET STRGHT: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#40H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT1: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#30H LCALL DLY SETB RDRV CLR LDRV MOV R1,#10H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT1: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#30H LCALL DLY CLR RDRV SETB LDRV MOV R1,#10H LCALL DLY

Nirma Institute of Technology

Project Report 8th Sem. I.C.

CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT2: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#2BH LCALL DLY SETB RDRV CLR LDRV MOV R1,#15H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT2: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#2BH LCALL DLY CLR RDRV SETB LDRV MOV R1,#15H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT3: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#26H LCALL DLY SETB RDRV

Nirma Institute of Technology

Project Report 8th Sem. I.C.

CLR LDRV MOV R1,#1AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT3: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#26H LCALL DLY CLR RDRV SETB LDRV MOV R1,#1AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT4: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#3AH LCALL DLY SETB RDRV CLR LDRV MOV R1,#06H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT4: SETB RDIR SETB LDIR SETB RDRV SETB LDRV

Nirma Institute of Technology

Project Report 8th Sem. I.C.

MOV R1,#3AH LCALL DLY CLR RDRV SETB LDRV MOV R1,#06H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT5: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#33H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT5: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#33H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF

Nirma Institute of Technology

Project Report 8th Sem. I.C.

RGHT6: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#36H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT6: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#36H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT7: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#20H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#33H

Nirma Institute of Technology

Project Report 8th Sem. I.C.

LCALL DLY LJMP SLF LEFT7: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#20H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#33H LCALL DLY LJMP SLF RGHT8: CLR RDIR CLR LDIR SETB RDRV SETB LDRV MOV R1,#23H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#30H LCALL DLY LJMP SLF LEFT8: CLR RDIR CLR LDIR SETB RDRV SETB LDRV MOV R1,#23H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0DH LCALL DLY

Nirma Institute of Technology

Project Report 8th Sem. I.C.

CLR RDRV CLR LDRV MOV R1,#30H LCALL DLY LJMP SLF DEFAULT: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#20H LCALL DLY CLR RDRV CLR LDRV MOV R1,#40H LCALL DLY LJMP SLF DLY: MOV R2,#0FFH DLYCNT: DJNZ R2,DLYCNT DJNZ R1,DLYCNT

Nirma Institute of Technology

Project Report 8th Sem. I.C.

HARDWARE The hardware implementation in this project is done in a unique way. As the robots and their design are very complex and the number of inputs and outputs of the system may vary according to the requirements and change in strategy or design the PCBs made for the robots are designed to be multipurpose such that the same circuits and PCBs could be used for all the robots just with minute change and increase or decrease in the number of components mounted on the PCB. The Schematics of various circuits are included in the following part of this section.

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U3

1 2

1 D3

C3 22uF

7812/TO

VIN

U4 3

VOUT

1 C4 10uF

POWER SUPPLY 1

D4

D

J2

J3

C

J4

B

LISTENER HMI 1 2 3 4 5 6 7 8 HMIL.LS1 9 10 HMIL.LS2 11 HMIL.LS3 12 VCC 13 14

3

2

1

7805/TO VOUT

VCC

3 C5 2.2uF

VCC

D5

LED

LED

LED

RED

YELLOW

GREEN

R3 22K

R4 10K

R5 5K

LISTENER DRVAX 1 2 3 4 5 6 7 8 DRVAXL.LS2 9 DRVAXL.LS1 10 LISTENER HB12V 1 2 3 4 5 6 7 8 HB12VL.LS1 9 10

VIN

DIODE

GND

24 V EXT

D1

2

+ -

DIODE

GND

J1

4

D2

2

5

SI.RXD SI.TXD VCC

C7 VCC 10nF HB12VT.LS1 HB12VT.LS2 VCC U1

DRVAXL.LS2 DRVAXL.LS1 HB12VL.LS1 HMIL.LS1 HMIL.LS2 HMIL.LS3 LCDL.LS1 AUXL.LS1

VCC

U2

39 38 37 36 35 34 33 32

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P1.0/T2 P1.1/T2X P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

1 2 3 4 5 6 7 8

21 22 23 24 25 26 27 28

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

10 11 12 13 14 15 16 17

19 18

X1 X2

ALE/P PSEN

30 29

31 9

EA/VP RST

SI.RXD SI.TXD HB12VT.LS1 HB12VT.LS2 DRVAUXT.LS1 DRVAUXT.LS2 LCDT.LS1 LCDT.LS2

VCC

3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7

11 1

LE OE

TALKER AUX

B

DS89C420

J6 1 2 3 4 5 6 7 8 9 10

AUXL.LS1 VCC

LISTENER AUX

R1 100E LCDT.LS1 LCDT.LS2 VCC

PB

DESIGNER'S NOTES: D1 OF LISTENER LCD/AUX IS USED FOR READING LCD BUSY FLAG. THE REST CAN BE USED TO READ 7 OTHER INPUTS

4

J9 1 2 3 4 5 6 7 8 9 10 11 12

TALKER LCD

A Title C1 30pF

11.0592 Mhz Y1

C2 30pF

VISHWAKARMA MICROCONTROLLER CARD Size A4 Date:

5

TALKER HB12V

J10 1 2 3 4 5 6 7 8 DRVAUXT.LS1 9 DRVAUXT.LS2 10 VCC 11 12

VCC

A

J8 1 2 3 4 5 6 7 8 9 10 11 12

D

C

74LS373

R2 10K LISTENER LCD 1 2 3 4 5 6 7 8 LCDL.LS1 9 10 VCC

TALKER DRVAX

2 5 6 9 12 15 16 19

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

C6 10uF

J5

J7 1 2 3 4 5 6 7 8 9 10 11 12

3

2

Document Number VK.1 Tuesday, April 06, 2004

Rev 1.1 Sheet

1

1

of

1

5

4

3

2

1

D1 VCC LED

GREEN

R3 5K1

D

D U1

J1 INTERFACE BUTTONS LANDER

C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MASTERON.TOGGLE AUTOMODE.EN.TOGGLE SPG1.PUSHBUTTON SPG2.PUSHBUTTON FLAP.TOGGLE DPG1.TOGGLE DPG2.TOGGLE GG.PSHLOCKBUTTON GAH.ON.TOGGLE GAH.DR.TOGGLE SPH.ON.TOGGLE SPH.DR.TOGGLE DPH.ON.TOGGLE DPH.DR.TOGGLE SPEEDCONTROL.SLIDER1 SPEEDCONTROL.SLIDER2 DIRNCONTROL.FWD.PB DIRNCONTROL.REV.PB DIRNCONTROL.RGT.PB DIRNCONTROL.LFT.PB SIGNAL.PUSHBUTTON

R2

3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

11

LE

OE

1

VCC

10K

HMIT.LS1 J2 TALKER

74LS373 U2 3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

11

LE

OE

1

VCC

HMIT.LS1 HMIT.LS2 HMIT.LS3

HMIT.LS2

74LS373

VCC

1 2 3 4 5 6 7 8 9 10 11 12 13 14

MASTER ON IS INPUT ON 1ST 74LS373'S D0 23 OTHER INPUTS CAN BE THEN READ INTO THE MICROCONTROLLER USING THE 3 SELECTION LINES

C

U3

B

3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

11

LE

OE

1

VCC

1 2 3 4 5 6 7 8 9 10

74LS373

2 3 4 5 6 7 8 9 10 VCC

R1 RESISTOR SIP 10 [10K]

1

J3 POWER OUT

B

HMIT.LS3

A

A Title VISHWAKARMA HUMAN MACHINE INTERFACE CARD Size A4 Date:

5

4

3

2

Document Number VK.4 Tuesday, April 06, 2004

Rev 1.1 Sheet

1

1

of

1

RM.DR RM.ON

J1

3 5

U14A

D

3

24V

1

BS2

11

OUT2

10

BRAKE

74LS08

LED

CS OUT TH OUT

LM.DR 3 LM.ON 5

10nF 10nF

4

C2

LMD18200T OUT1

LM.M1

2 C8

DIR PWM

BS1

1

BRAKE

BS2

11

OUT2

10

RM.M2

7

C17 1000uF

C1

BS1

DIR PWM

2

D2 POWER HEADER

RM.DR

U7 8 9

RM.M1

2

OUT1

GND

1 2

4

LMD18200T

10nF 10nF C7

D

LM.M2

7

1

CS OUT TH OUT

6

U3 8 9

1

24V

GND

Q4 IS INVERTED O/P OF Q5 [MASTER ON]

2

24V

VCC

3

6

4

VCC

5 DESIGNER NOTES:

U14B

J2

4 R2 22K

6

RM.ON RM.M1 RM.M2 LM.M1 LM.M2

5 74LS08 24V

LAYOUT CAUTION NOTES:

RM.DR RM.ON

8 9

CS OUT TH OUT

3 5 4

U14D 11

LM.ON

OUT1

2

DIR PWM

BS1

1

BRAKE

BS2

11

OUT2

10

GND

13 74LS08

U10

8 9

RM.M1 C3

CS OUT TH OUT

LM.DR 3 LM.ON 5

10nF 10nF

4

C4

LMD18200T LM.M1

OUT1

2

DIR PWM

BS1

1

BRAKE

BS2

11

OUT2

10

RM.M2

C5 10nF 10nF C6 LM.M2

VCC R1 10K

24V

R3

SPH.DR 3

DIR PWM

4 74LS08 U13B DPH.ON

4

OUT2

10

DPH.DR 10nF 10nF

6

3 5

DIR PWM

BS1

1 C11

4

BRAKE

BS2

11

OUT2

10

C10 SPH.M2

5

LE

OE

2 5 6 9 12 15 16 19

24V

10nF 10nF C12 DPH.M2

SPH.M1 SPH.M2 DPH.M1 DPH.M2 GAH.M1 GAH.M2 GG.M1 GG.M2

U2 8 9

CS OUT TH OUT

3 5

DIR PWM

1 GAH.DR U13C

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

11

LE

OE

1

1 2 3 4 5 6 7 8 DRVAXT.LS2 9 DRVAXT.LS1 10

74LS373 R4 RESISTOR SIP 10

9

4 8

10

BRAKE

74LS08

LMD18200T OUT1

U4 GAH.M1

2

BS1

1 C13

BS2

11

OUT2

10

GG.DR 10nF 10nF

C14 GAH.M2

7

D0 D1 D2 D3 D4 D5 D6 D7

2 3 4 5 6 7 8 9 10 VCC

GAH.ON

3 4 7 8 13 14 17 18

LMD18200T

AUX MOTORS

8 9

CS OUT TH OUT

3 5

DIR PWM

BS1

1 C15

4

BRAKE

BS2

11

OUT2

10

OUT1

GG.M1

2

10nF 10nF C16 GG.M2

A

U13D

J5 TALKER

MASTER.ON

12

GG.ON

13

11

Title VISHWAKARMA DRIVE CONTROL & AUXILIARY MOTOR CARD

74LS08

Size A3 Date:

4

B

1 2 3 4 5 6 7 8

GIFT GRIPPER [GG]

GND

U12 SPH.LOW SPH.HGH DPH.LOW DPH.HGH GAH.LOW GAH.HGH GG.OL GG.CL

24V

GIFT ARM HOIST [GAH]

6

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

VCC

D0 D1 D2 D3 D4 D5 D6 D7

74LS373

5

DPH.M1

2

J3

GND

11 VCC VCC

J6 MSW LANDER

BS2

11

OUT1

U9 3 4 7 8 13 14 17 18

1

1 C9

CS OUT TH OUT

74LS08

RG1 RG2

VCC

BS1

LMD18200T

8 9

6

MASTER.ON

1 2 3 4 5 6 7 8 9 10 11 12

BRAKE

U5 SPH.M1

2

VCC

3 5

OUT1

7

1 2 3 4 5 6 7 8 9 10 11 12

2

LMD18200T

74LS373

RESISTOR SIP 10

J7 AUX MSW LANDER

1

MASTER.ON

CS OUT TH OUT

6

1

SPH.ON

MASTER.ON

2 3 4 5 6 7 8 9 10

B

U13A

8 9

GND

LE OE

SPH.DR SPH.ON DPH.DR DPH.ON GAH.DR GAH.ON GG.DR GG.ON

7

DRVAXL.LS2 11 1

2 5 6 9 12 15 16 19

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

DOUBLE PART HOIST [DPH]

GND

U1 U11 D0 D1 D2 D3 D4 D5 D6 D7

24V

SINGLE PART HOIST [SPH]

74LS373

3 4 7 8 13 14 17 18

C

7

D1 LED

7

LE OE

R.DR R.ON L.DR L.ON MASTER.IND MASTER.ON R.BR L.BR

6

11 1

2 5 6 9 12 15 16 19

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

VCC

DRVAXL.LS1

VCC

D0 D1 D2 D3 D4 D5 D6 D7

VCC

DRVAXL.LS1 DRVAXL.LS2

3 4 7 8 13 14 17 18

7

1 2 3 4 5 6 7 8 9 10 11 12

J4 LISTENER

A

U8

VCC

74LS08

LMD18200T

GND

10

12

6

U6

6

DRV MOTORS LM.DR

VCC

8

CHECK FOR CONNECTIONS OF 74LS08 AND 74LS373 TO 5V AND NOT TO 24V

C

24V

U14C 9

POWER HEADER , AUX MOTORS HEADER AND DRV MOTORS HEADER SHOULD BE RATED TO CARRY 10A [MAX]

1 2 3 4

3

2

Document Number VK.2 Tuesday, April 06, 2004

Rev 1.0 Sheet

1

1

of

1

5

4

3

2

1

J3 U10 D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

11

LE

OE

1

2 3 4 5 6 7 8 9 10

G1.STL G2.STL

3 4 7 8 13 14 17 18

VCC

R4

VCC

LE

F1 U1 8 9

D2 LED F1.DR F1.ON

3 5 4

CS OUT TH OUT

6

10uF

5K1

VCC

OE

1

U14A 3

+

R2 R

2

-

LMD18200T OUT1 2 BS1

BRAKE

74LS373

BS2 OUT2

G1.STL

1

12V TLC393

F1.M1

10uF LED

G1 U7 8 9

10nF 11 C10

10nF

G1.DR G1.ON

7

VCC R6 R

DIR PWM

4

BRAKE

R8 R

U14B C1

R7 R

5

+

6

-

CS OUT TH OUT

3 5

F1.M2

10

VCC

12V

C8

D4

1 C9

DIR PWM

D

TALKER

LMD18200T OUT1 2

G1.M1

BS1

1 C17

BS2

11 C18

OUT2

10nF 10nF G1.M2

10

7

11

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

C6

R9

GND

D0 D1 D2 D3 D4 D5 D6 D7

G1.DR G1.ON G2.DR G2.ON MASTER.IND MASTER.ON LSR.DRV LSR.EN

1 2 3 4 5 6 7 8 9 10

R3 R

6

12V 2 5 6 9 12 15 16 19

R1 R

VCC

VCC

U12 3 4 7 8 13 14 17 18

HB12VT.LS1

74LS373

RESISTOR SIP 10 [10K]

1

J2 MSW LANDER

HB12VT.LS1

GND

VCC

VCC

C

D

F1.1 F1.2 F2.1 F2.2 G1.OL G2.OL

F1.1 F1.2 F2.1 F2.2 G1.OL G2.OL SG1.OL SG2.OL

1 2 3 4 5 6 7 8 9 10 11 12

G2.STL

7 D3

12V

TLC393

C4

3 5

U11 D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

11

LE

OE

1

F1.DR F1.ON F2.DR F2.ON SG2.DR SG2.ON SG1.DR SG1.ON

F2.DR F2.ON

4

1 C11

BS2

11 C12

OUT2

G2.DR G2.ON

10nF

8 9

CS OUT TH OUT

3 5

DIR PWM

4

BRAKE

6

U3 10nF

DIR PWM BRAKE

G2

F2.M2

10

G2.M1

BS1

1 C19

BS2

11 C20

OUT2

10nF 10nF G2.M2

10

VCC 74LS373

12V

LISTENER

12V

C5

12V

4 3

BRAKE

5 8

BS2 OUT2

4

BRAKE

10nF 11 C14

10nF

BS1

BS2 OUT2

1 C21

VCC

10nF 11 C22 10

LSR.DRV

8 9

CS OUT TH OUT

3 5

DIR PWM

4

BRAKE

6 VCC

DIR PWM

VCC

6 GND

4

1 C13

DIR PWM

K1

3 5

SG21.M1

SG11.M1

LMD18200T OUT1 2

SG11.M2

LSR.M1

BS1

1 C27

BS2

11 C28

10nF GND

SG2.ON

B

BS1

CS OUT TH OUT

U9

OUT2

10nF 10nF

B

LSR.M2

10

SG21.M2

10

7

3 5

CS OUT TH OUT

8 9

GND

8 9

12V EXT

LMD18200T OUT1 2

10uF

LSR LMD18200T OUT1 2

7

12V EXT

VCC

SG21

U8

6

10uF

SG11 U5

C26

C7

10uF

7

R10 6

VCC

U13B

7 1 2

4 D5 DIODE

12V

6 SG1.DR 5 12V

RELAY DPDT

LSR.EN

SG2.DR 2 74LS86 12V EXT 1 2

DESIGNER NOTES: 4

Q4 IS INVERTED O/P OF Q5 [MASTER ON] [U12]

D1 LED

C25 100uF

BS1

BS2 OUT2

SG1.ON

1 C15

11 C16

10nF

10

CS OUT TH OUT

3 5

DIR PWM

4

BRAKE

10nF

DIR PWM BRAKE

SG22.M1

BS1

1 C23

BS2

11 C24

OUT2

G1.M1 G1.M2 G2.M1 G2.M2 LSR.M1 LSR.M2 LSR.AN LSR.CT F1.M1 F1.M2 F2.M1 F2.M2 SG11.M1 SG11.M2 SG21.M1 SG21.M2 SG12.M1 SG12.M2 SG22.M1 SG22.M2

SG12.M1

10nF

10

10nF SG12.M2

SG22.M2

7

12V POWER

3 5

CS OUT TH OUT

8 9

LMD18200T OUT1 2

J6 MOTORS OUT

LMD18200T OUT1 2

7

8 9

GND

3

6

U6

VCC

SG22

U13A 1

U4

6

SG12 10uF

VCC

Q1

J1

10E Q2 2N2222

10uF

74LS86 2N2222

C3

C2

GND

12V

LMD18200T OUT1 2

7

HB12VL.LS1 HB12VL.LS2

3 4 7 8 13 14 17 18

BS1

C

10uF F2.M1

7

1 2 3 4 5 6 7 8 9 10 11 12

LMD18200T OUT1 2

VCC

J4

CS OUT TH OUT

GND

U2 8 9

LED

GND

C

VCC

F2

6

10uF

LAYOUT CAUTION NOTES: 1.) RELAY [K1] SHOULD BE 5AMP/CONTACT TYPE 2.) THE 12V POWER HEADER [J1] SHOULD BE ABLE TO SOURCE 10AMP [MAX VALUE] 3.) MOTORS OUT HEADER [J6] SHOULD BE ABLE TO SUPPLY 1A/PIN [MAX VALUE] 4.) ALL BYPASS CAPACITORS SHOULD BE AS CLOSE TO THEIR RESPECTIVE LMD18200s AS POSSIBLE. 5.) ALL ELECTROLYTIC CAPS ARE RATED AT 16/25V

A

R5 22K

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A

Title VISHWAKARMA 12V H-BRIDGE BOARD Size A3 Date: 5

4

3

2

Document Number VK.3

Rev 1.1

Wednesday, April 14, 2004

Sheet 1

1

of

1

5

4

J4

1 +

HEADER 2

IN

OUT

1 2 3 4 5 6 7 8

VCC 3

GND

1 2

D1

+ C2

U2A 3

D

2 8 HEADER R18

+

U6A 3

1 2

-

+

1

D

-

VCC

R2 U2B 5 6

+

U6B 5

7 6

-

+

RESISTOR SIP 9 7

R16

-

TLC393

TLC393

VCC 9 8 7 6 5 4 3 2

J3

1

VCC R1

2

C1

2

1

UA7805/SOT U1

J7

3

VCC

1 2 3 4 5 6 7 8

VCC J5 VCC

VCC

Q1 8 HEADER

VCC 1 2 3 4 5 6 7 8

Q2

2N2222

C

U3A 3

+

2

-

5

+

U7A 3

+

2

-

5

+

6

-

1

3 4 7 8 13 14 17 18

1

R4 U3B

6

U7B

7

-

8 HEADER

7

VCC

11 1

U12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

LE OE

3

+

2

-

5

+

U8A 3

+

2

-

5

+

6

-

1

3 4 7 8 13 14 17 18

1

R6 U4B

VCC

LE OE

U11

R5

6

VCC

U8B

7

-

7

C

VCC

D0 D1 D2 D3 D4 D5 D6 D7

HEADER 14

11 1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

LE OE

TLC393 TLC393 Q5

SN74LS373/LCC

2 3 4 5 6 7 8 9

11 1

D0 D1 D2 D3 D4 D5 D6 D7

1 2 3 4 5 6 7 8 9 10 11 12 13 14

SN74LS373/LCC

U4A

3 4 7 8 13 14 17 18

2 5 6 9 12 15 16 19

Q4

J2

1 2 3 4 5 6 7 8 9 10 11 12

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

VCC VCC

Q3

D0 D1 D2 D3 D4 D5 D6 D7

TLC393 TLC393

VCC

J1

U10

R3

Q6

SN74LS373/LCC

B

B

VCC R17

12 HEADER

J6

VCC

Q7

VCC 1 2 3 4 5 6 7 8

VCC

Q8

3

+

2

-

U9A R7

3

+

2

-

1 VCC

1

U5A

1

RESISTOR SIP 9

VCC R8 U5B 5 6

+

R9

U9B 5

+

6

-

7

TLC393

7

TLC393

R10

8 HEADER J8

1 2 3 4 5 6 7 8

A

A

VCC

Title Digitizer Size A4

8 HEADER

Date: 5

4

3

2

Document Number DIG.1

Rev

Monday, May 10, 2004

Sheet 1

1

of

1

Project Report 8th Sem. I.C.

SECTION 5 Heuristics Design and Development: This whole project in itself has been a mammoth task to complete within a short time of five months during which the A to Z of the project was supposed to be designed and developed physically in reliable and working conditions. Due to the same reason a lot of research oriented activity, new ideas and heuristics designing has been done in order to minimize efforts, time and at the same time gain more efficiency. In the same process implementation of certain concepts mentioned below have played and important role in the formation of this project.

ü

Optoelectronic Sensor using OPT101 and LED

ü

Multipurpose Schematics and PCB Designs

ü

Serial Interface for Status Monitoring and Program Updating

ü

LCD interface for Status Monitoring

Optoelectronic Sensor using OPT101 and LED Using the combination of PDIP IC – OPT101 and LED with the concept of reflective light amplification as the Optoelectronic sensor has been a totally new development at student level. This development has been specially beneficial as the weight constituted by the sensors is much lesser then the commercially available ready made sensors and also if the sensor fails it is very easy to change the IC or even the whole set up to make the system working again.

Nirma Institute of Technology

Project Report 8th Sem. I.C.

Multipurpose Schematics and PCB Designs The Schematics and PCB Designs of the Electronic Circuits have been done such that the PCBs are multipurpose and just with the minute change in the number of components mounted on the PCB and some change in the interconnections between the PCBs, they could be used for all the robots. In fact the PCBs are made such that in most of the general robotic applications these PCBs could be used. The robotic systems are MIMO – Multi Input Multi Output Systems and the Set of PCBs is made so flexible that it could be used for sensing 64 Inputs as well as for sending 48 output signals.

Serial Interface for Status Monitoring and Program Updating Loading the microcontroller again and again with minute changes in the program is always a time taking process especially while testing the programs. At the same time when the program is not performing as per the desire it is necessary to find the flaw in the program which is possible by monitoring various RAM locations, Registers, Microcontroller Ports, and Individual Bits etc. on the microcontroller. Implementing Serial Interface is the solution to both these problems as the program in the microcontroller could be quickly updated using Serial Interface and at the same time monitoring status of various memory locations and ports etc. become easy using the serial communication.

LCD interface for Status Monitoring Monitoring status is difficult where the serial communication between PC and microcontroller is not easy as the PC is not nearby. In this case the LCD is interfaced with the microcontroller in order to monitor the status and debug the program.

Nirma Institute of Technology

Ultra-High-Speed Flash Microcontroller User’s Guide

33 16kB FLASH MEMORY

1kB SRAM

WITH AUTOSELECT INCREMENT/ DECREMENT

HIGH-SPEED ONE CLOCK-CYCLE 8051 MICROPROCESSOR

FOUR 8-BIT PARALLEL PORTS

MIPS

25

DUAL DATA POINTERS

5 1

DUAL SERIAL PORTS

0 ORIGINAL 8051

DS89C420

DS89C420

SECTION 1: INTRODUCTION Dallas Semiconductor’s DS89C420 is an 8051-compatible microcontroller that provides improved performance and power consumption when compared to the original 8051 version. It retains instruction set and object code compatibility with the 8051, yet performs the same operations in fewer clock cycles. Consequently, greater throughput is possible for the same crystal speed. As an alternative, the DS89C420 can be run at a reduced frequency to save power. The more efficient design allows a much slower crystal speed to get the same results as an original 8051, using much less power. The fundamental innovation of the DS89C420 is the use of only one clock per instruction cycle compared with 12 for the original 8051. This results in up to 12 times improvement in performance over the original 8051 architecture and up to four times improvement over other Dallas Semiconductor high-speed microcontrollers. The DS89C420 provides several peripherals and features in addition to all of the standard features of an 80C32. These include 16kB of on-chip flash memory, 1kB of on-chip RAM, four 8bit I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual data pointers, an on-chip watchdog timer, five levels of interrupt

priority, and a crystal multiplier. The device provides 256 bytes of RAM for variables and stack; 128 bytes can be reached using direct or indirect addressing, or using indirect addressing only. In addition to improved efficiency, the DS89C420 can operate at a maximum clock rate of 33MHz. Combined with the 12 times performance, this allows for a maximum performance of 33 million instructions per second (MIPs). This level of computing power is comparable to many 16-bit processors, but without the added expense and complexity if implementing a 16-bit interface. The DS89C420 incorporates a power-management mode that allows the device to dynamically vary the internal clock speed from 1 clock per cycle (default) to 1024 clocks per cycle. Because power consumption is directly proportional to clock speed, the device can reduce its operating frequency during periods of little switchback. This greatly reduces power consumption. The switchback feature allows the device to quickly return to highest speed operation upon receipt of an interrupt or serial port activity, allowing the device to respond to external events while in power-management mode.

________________________________________________________________________ Maxim Integrated Products

1

Ultra-High-Speed Flash Microcontroller User’s Guide DS89C420 Special-Function Register Locations REGISTER P0 SP DPL DPH DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 EXIF CKMOD SCON0 SBUF0 ACON P2 IE SADDR0 SADDR1 P3 IP1 IP0 SADEN0 SADEN1 SCON1 SBUF1 ROMSIZE PMR STATUS TA T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PSW FCNTL FDATA WDCON ACC EIE B EIP1 EIP0

ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 96h 98h 99h 9Dh A0h A8h A9h AAh B0h B1h B8h B9h BAh C0h C1h C2h C4h C5h C7h C8h C9h CAh CBh CCh CDh D0h D5h D6h D8h E0h E8h F0h F1h F8h

BIT 7 P0.7

BIT 6 P0.6

BIT 5 P0.5

BIT 4 P0.4

BIT 3 P0.3

BIT 2 P0.2

BIT 1 P0.1

BIT 0 P0.0

ID1 SMOD_0 TF1 GATE

ID0 SMOD0 TR1 C/T

TSL OFDF TF0 M1

AID OFDE TR0 M0

— GF1 IE1 GATE

— GF0 IT1 C/T

— STOP IE0 M1

SEL IDLE IT0 M0

WD1 P1.7 IE5

WD0 P1.6 IE4

T0M P1.3 CKRY T0MH TB8_0

MD1 P1.1 RGSL

MD0 P1.0 BGS

SM1_0

T1M P1.4 IE2 T1MH REN_0

MD2 P1.2 RGMD

SM0/FE_0

T2M P1.5 IE3 T2MH SM2_0

RB8_0

TI_0

RI_0

PAGEE P2.7 EA

PAGES1 P2.6 ES1

PAGES0 P2.5 ET2

P2.4 ES0

P2.3 ET1

P2.2 EX1

P2.1 ET0

P2.0 EX0

P3.7 — —

P3.6 MPS1 LPS1

P3.5 MPT2 LPT2

P3.4 MPS0 LPS0

P3.3 MPT1 LPT1

P3.2 MPX1 LPX1

P3.1 MPT0 LPT0

P3.0 MPX0 LPX0

SM0/FE_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

CD1 PIS2

CD0 PIS1

SWB PIS0

CTM —

PRAME 4X/2X SPTA1

RMS2 ALEON SPRA1

RMS1 DME1 SPTA0

RMS0 DME0 SPRA0

TF2 —

EXF2 —

RCLK —

TCLK —

EXEN2 —

TR2 —

C/T2 T2OE

CP/RL2 DCEN

CY FBUSY

AC FERR

F0

RS1

RS0 FC3

OV FC2

F1 FC1

P FC0

SMOD_1

POR

EPFI

PFI

WDIF

WTRF

EWT

RWT

—

—

—

EWDI

EX5

EX4

EX3

EX2

—

—

—

MPWDI LPWDI

MPX5 LPX5

MPX4 LPX4

MPX3 LPX3

MPX2 LPX2

Note: Shaded bits are timed-access protected.

_____________________________________________________________________________________________

10

Ultra-High-Speed Flash Microcontroller User’s Guide ROM Size Select (ROMSIZE) SFR C2h

7 — R-1

6 — R-1

5 — R-1

4 — R-1

3 PRAME RT-0

2 RMS2 RT-1

1 RMS1 RT-0

0 RMS0 RT-1

R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset

LPX0 Bit 0

Least Significant Priority Select Bit for External Interrupt 0. MPX0 is the least significant bit of the bit pair MPX0 (IP1.0), LPX0 that designates priority level for external interrupt 0.

Bits 7–3

These bits are reserved. Read data is 1.

PRAME Bit 3

Program RAM Enable. When set (= 1), the internal 1k RAM is mapped as internal program space between addresses 0400h–07FFh. All program fetches and MOVC accesses are directed to this 1k RAM. When serving as program memory, the RAM continues to be accessible as MOVX data space (if DME0 = 1). The 1k RAM is not accessible as program space when EA = 0. When clear (= 0), the internal 1k RAM is not accessible as program space.

RMS2–0 Bits 2–0

ROM Memory Size Select 2-0. This register is used to select the maximum on-chip decoded address. Care must be taken that the memory location of the current program counter is valid both before and after modification. These bits can only be modified using a timed-access procedure. The EA pin overrides the function of these bits when asserted, forcing the device to access external program memory only. Configuring this register to a setting that exceeds the maximum amount of internal memory can corrupt device operation. These bits default on reset to the maximum amount of internal program memory (i.e., 16k for DS89C420).

On-Chip ROM Address . RS2 0 0 0 0 1 1 1 1

RS1 0 0 1 1 0 0 1 1

RS0 0 1 0 1 0 1 0 1

MAXIMUM ON-CHIP ROM ADDRESS 0kB/Disable on-chip ROM 1kB/03FFh 2kB/07FFh 4kB/0FFFh 8kB/1FFFh 16kB/3FFFh (default) 32kB/7FFFh 64kB/FFFFh

Power Management Register (PMR) SFR C4h

7 CD1 RW*-1

6 CD0 RW*-0

5 SWB RW-0

4 CTM RW*-0

3 4X / 2X RW*-0

2 ALEON RW-0

1 DME1 RW-0

0 DME0 RW-0

R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description

CD1, CD0 Bits 7, 6

Clock Divide Control 1-0. These bits select the number of crystal oscillator clocks required to generate one machine cycle. Switching between modes requires a transition through the default divide-by-1 mode (CD1, CD0 = 10b). Attempts to perform an invalid transition are ignored. For example, going from the crystal multiplier 2X mode to the divide-by-1024 mode would require first switching from the 2X crystal multiplier mode to the divide-by-1 mode, followed by the switch from the divide-by-1 to the divide-by-1024 mode. These bits cannot be modified when running from the internal ring oscillator (RGMD = 1). The divide-by-1024 setting (CD1,CD0 = 11b) cannot be selected when switchback is enabled (SWB = 1) and a switchback source (serial port or external interrupt) is active. CD1, CD0 00 01 10 11

CLOCK FUNCTION Crystal multiplier (4X or 2X mode as determined by PMR.3) Reserved (forced into divide-by-1 mode if set) Divide-by-1 (default state) Divide-by-1024

The setting of these bits affects timer and serial port operation. Tables located in the SFR decription for CKCON (8Eh) detail the respective operational dependencies on these bits. _____________________________________________________________________________________________

28

Ultra-High-Speed Flash Microcontroller User’s Guide UHSM

UHSM

8051

8051

UHSM vs.

HEX

CLOCK

TIME

CLOCK

TIME

8051 SPEED

INSTRUCTION

CODE

CYCLES

@ 25MHz

CYCLES

@ 25MHz

ADVANTAGE

CJNE A, #data, rel

B4

4

160 ns

24

960 ns

6

CJNE Rn, #data, rel

B8..BF

4

160 ns

24

960 ns

6

CJNE @Ri, #data, rel

B6..B7

5

200 ns

24

960 ns

4.8

DJNZ Rn, rel

D8..DF

4

160 ns

24

960 ns

6

DJNZ direct, rel

D5

5

200 ns

24

960 ns

4.8

NOP

00

1

40 ns

12

480 ns

12

Table 5-2. INSTRUCTION SPEED SUMMARY INSTRUCTION CATEGORY

SPEED ADVANTAGE

QUANTITY

4.0 4.8 5.3 6.0 8.0 12.0 24.0 4.0 6.0 8.0 12.0 4.8 6.0 8.0 8.5

2 1 1 12 5 27 1 1 27 5 13 3 5 8 111

SPEED ADVANTAGE

QUANTITY

4.0 4.8 5.3 6.0 8.0 12.0 24.0 4.0 6.0 8.0 12.0 4.8 6.0 8.0 9.4

4 1 1 35 5 93 1 1 42 5 43 4 12 8 255

Total instructions: 1 byte

Total instructions: 2 byte

Total instructions: 3 byte

Average across all instructions OPCODE CATEGORY Total opcodes: 1 byte

Total opcodes: two byte

Total opcodes: three byte

Average across all opcodes

SECTION 6: MEMORY ACCESS The DS89C420 ultra-high-speed microcontroller supports the memory interface convention established for the industry standard 80C51, but also implements two new page mode memory interfaces needed to support ultra-high-speed external operation. These external page mode interfaces are described later in this section. 53

_____________________________________________________________________________________________

Ultra-High-Speed Flash Microcontroller User’s Guide Program and data memory areas can be implemented on-chip, off-chip, or as a combination. When opting not to use the internal memory provided, or when exceeding the maximum address of on-chip program or data memory, the device performs an external memory access using the expanded memory bus on ports 0 and 2. While serving as a memory bus, port 0 and port 2 cannot function as I/O ports. The PSEN signal is driven active low to function as a chip enable or output enable when performing external code memory fetches. The RD and WR signals serve as enables when accessing external SRAM data memory. Program execution always begins at the reset vector, address 0000h. If on-chip program memory is enabled, program execution begins at internal location 0000h; otherwise, external program memory is used. Any reset causes the next program fetch to begin at this location. Subsequent branches and interrupts determine how program memory fetches deviate from sequential addressing.

INTERNAL FLASH MEMORY The DS89C420 ultra-high-speed microcontroller contains five physically distinct blocks of embedded flash memory. The two largest blocks, each 8kB, provide a total of 16kB for use as internal program memory. A 64-byte flash security block has been incorporated to allow encryption during program memory verify operations. To further protect internal code against undesirable access, a three-level lock system has been implemented in a separate flash memory block. This single-byte block contains three lock bits (LB1, LB2, LB3), each of which can individually enable higher lock levels and greater code protection. The fifth flash memory block resident to the DS89C420 is the option control register. This byte contains a bit to enable or disable the watchdog timer reset function (EWT = WDCON.1) on a power-on reset. The two 8kB program memory blocks form a contiguous 16kB address range extending from 0000h through 3FFFh. The on-chip decoded address range is controlled in hardware by the EA pin, and in software through the ROMSIZE feature. The EA pin enables or disables the ability to access internal program memory and overrides any software configured bit settings. The logic state of the EA pin should be changed only when the microcontroller is being held in reset. The EA pin is sampled on each exit from the reset state to determine whether program fetching should begin internally or externally. When the EA pin is low, all code fetches are done externally through the expanded bus. When the EA pin is high, code fetches begin from internal program memory. Code fetches exceeding the maximum address of on-chip program memory cause the device to access off-chip program memory. The maximum on-chip decoded address is selectable by software using the ROMSIZE feature.

ROMSIZE FEATURE Using the ROMSIZE feature, software can allow the DS89C420 to behave like a device with less on-chip memory. The maximum memory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map, allowing the full 64kB of external memory space to be addressed. The ROMSIZE feature has two primary uses. In the first instance, it allows the device to act as a bootstrap loader for a flash memory or nonvolatile SRAM (NVSRAM). The internal program memory can contain a bootstrap loader, which can program the external memory device. Secondly, this method can be used to increase the amount of available program memory from 64kB to 80kB without bank switching. The maximum amount of on-chip memory is selected by configuring the ROM size select register bits RMS2, RMS1, RMS0 (ROMSIZE.2-0). The reset default condition gives access to the maximum on-chip program memory of 16kB. In this configuration, only code addresses greater than 16kB result in external program memory accesses. The possible settings for the ROM size select register are shown in the following table.

Table 6-1. ROMSIZE REGISTER SETTINGS RMS2 0 0 0 0 1 1 1 1

RMS1 0 0 1 1 0 0 1 1

RMS0 0 1 0 1 0 1 0 1

MAX ON-CHIP PROGRAM MEMORY 0kB 1kB (0-03FFh) 2kB (0-07FFh) 4kB (0-0FFFh) 8kB (0-1FFFh) 16kB (0-3FFFh) DEFAULT INVALID – RESERVED INVALID – RESERVED

Modification of the ROMSIZE (C2h) special function register requires using the timed access procedure and must be followed by a two machine cycle delay, such as executing two NOP instructions, before jumping to the new address range. Interrupts must be disabled during this operation, because a call to an interrupt vector during the changing of the memory map can cause erratic results. To select _____________________________________________________________________________________________

54

Ultra-High-Speed Flash Microcontroller User’s Guide the watchdog reset function automatically. Other bits of this register are undefined and are at logic 1 when read. The value of this register can be read at address FCh in parallel programming mode or by executing the verify option control register instruction in ROM Loader or in-application programming mode.

FFFF

FFFF

Note: The hatched areas shown on the internal and external memory are disabled on power-up (Default)

INTERNAL MEMORY 03FF

INTERNAL REGISTERS

SCRATCH PAD

128 Bytes SFR

0000

1kB x 8 SRAM

External Program Memory

Data OR prog mem addr from 400–7FF

External Data Memory

4000 3FFF

FF

8kB x 8 Flash Memory (Program)

128 Bytes Indirect Addressing 2000

80 7F

1FFF 2F 20 1F

8kB x 8 Flash Memory (Program)

Bit Addressable

Bank 3 Bank 2 Bank 1

00

Bank 0

0000

03FF

0000

0000

Non-usable if Internal SRAM is activated

Figure 6-1. Memory Map

INTERNAL SRAM MEMORY The DS89C420 ultra-high-speed microcontroller incorporates an internal 1kB SRAM that is usable as data, program, or merged program/data memory. Upon a power-on reset, the internal 1kB memory is disabled and transparent to both program and data memory maps. When used for data, the memory is addressed through MOVX commands, and is in addition to the 256 bytes of scratchpad memory. To enable the 1kB SRAM as internal data memory, software must set the DME0 bit (PMR.0). After setting this bit, all MOVX accesses within the first 1kB (0000h–03FFh) is directed to the internal SRAM. Any data memory accesses outside of this range are still directed to the expanded bus. One advantage of using the internal data memory is that MOVX operations automatically default to the fastest access possible. Note that the DME0 bit is cleared after any reset, so access to the internal data memory is prohibited until this bit is modified. The contents of the internal data memory are not affected by the changing of the data memory enable (DME0) bit. Table 63 shows how the DME1, DME0 bits affect the data memory map. _____________________________________________________________________________________________

56

Ultra-High-Speed Flash Microcontroller User’s Guide When serving as an I/O port, the drive varies as follows: for logic 0, the port invokes a strong pulldown; for logic 1, the port invokes a strong pullup for two oscillator cycles to assist with the logic transition. Then the port reverts to a weak pullup. This weak pullup is maintained until the port transitions from logic 1 to logic 0. External circuits can overdrive the weak pullup. This allows the logic 1 output state to serve as the input state as well. Substantial DC current is available in both the high and low levels. However, the power dissipation limitations make it inadvisable to heavily load multiple pins. In general, sink and source currents should not exceed 10mA total per port (8 bits) and 25mA total per package.

Input Functions The input state of the I/O ports is the same as that of the output logic 1. That is, the pin is pulled weakly to logic 1. This logic 1 state is easily overcome by external components. Thus, after software writes a 1 to the port pin, the port is configured for input. When the port is read by software, the state of the pin is read. The only exception is the read-modify-write instructions, discussed earlier. If the external circuit is driving logic 1, then the pin is logic 1. If the external circuit is driving logic 0, then it overcomes the internal pullup. Thus, the pin is the same as the driven logic state. Note that the port latch is not altered by a read operation. Therefore, if logic 0 is driven onto a port pin from an external source, then removed, the pin reverts to the weak pullup, as determined by the internal latch.

SECTION 11: PROGRAMMABLE TIMERS The ultra-high-speed microcontroller incorporates three 16-bit programmable timers and has a watchdog timer with a programmable interval. Because the watchdog timer is significantly different from the other timers, it is described separately. The 16-bit timers are referred to as timers. The three timers offer the same controls and I/O functions that were available in the 80C32. As mentioned, the actual timing of these functions is user selectable to be compatible with the instruction cycle of the older generation of 8051 family (12 clocks per tick) or the new generation (1 clock per tick). The timing for each of the three timers can be selected independently and can be changed dynamically. In most modes, the timers can be used as either counters of external events or timers. When functioning as a counter, 1 to 0 transitions on a port pin are monitored and counted. When functioning as timers, they effectively count oscillator or system clock cycles. The time base for the timer function is detailed later in this section. Because an input clock pulse must be sampled high for two system clock cycles and low for two system clock cycles in order to be recognized, this sets the maximum sampling frequency on any timer input at one-fourth of the main system clock frequency. Since the ultra-high-speed microcontroller timers have a variety of features, the following lists summarize the capabilities: Timer 0

Timer 1

Timer 2

13-bit timer/counter

13-bit timer/counter

16-bit timer/counter

16-bit timer/counter

16-bit timer/counter

16-bit timer with capture

8-bit timer w/ autoreload

8-bit timer w/ autoreload 1

6-bit autoreload timer/counter

Two 8-bit timer/counters

External control pulse timer/counter

16-bit up/down autoreload

External control pulse timer/counter

Baud-rate generator

Timer/counter Baud-rate generator Timer output clock generator

16-BIT TIMERS Timers 0 and 1 are nearly identical. Timer 2 has several additional features such as up/down counting, capture values, and an optional output pin that make it unique. The following table summarizes the SFR bits that control operation of timers 0, 1, and 2. Detailed bit descriptions can be found in Section 4. After the table, timers 0 and 1 are described first, followed by a separate description for timer 2. As mentioned above, the time base for each timer can be varied, which is discussed in more detail in the following pages.

_____________________________________________________________________________________________

96

Ultra-High-Speed Flash Microcontroller User’s Guide

BIT NAMES GATE C/T M1, M0 TF0 TR0 T0M T0MH

DESCRIPTION Gate control enable for INTO pin Counter/timer select Timer mode select bits Timer overflow flag Timer run control Input clock select (/4) Input clock high-speed select (/1) Timer LSB Timer MSB

REGISTER LOCATION TMOD – 89h TMOD – 89h TMOD – 89h TCON – 88h TCON – 88h CKCON – 8Eh CKMOD – 96h TL0 – 8Ah TH0 – 8Ch

BIT POSITIONS TMOD.3 TMOD.2 TMOD.1,0 TCON.5 TCON.4 CKCON.3 CKMOD.3

GATE C/T M1, M0 TF1 TR1 T1M T1MH

Gate control enable for INT1 pin Counter/timer select Timer mode select bits Timer overflow flag Timer run control Input clock select (/4) Input clock high-speed select (/1) Timer LSB Timer MSB

TMOD – 89h TMOD – 89h TMOD – 89h TCON – 88h TCON – 88h CKCON – 8Eh CKMOD – 96h TL1 – 8Bh TH1 – 8Dh

TMOD.7 TMOD.6 TMOD.5,4 TCON.7 TCON.6 CKCON.4 CKMOD.4

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2OE DCEN T2M T2MH

Timer overflow flag Timer external flag Timer 2 receive serial clock enable Timer 2 transmit serial clock enable External enable for T2EX pin Timer run control Counter/timer select Capture/reload select Output enable for T2 pin Down count enable Input clock select (/4) Input clock high-speed select (/1) Timer LSB Timer MSB Timer capture LSB Timer capture MSB

T2CON – C8h T2CON – C8h T2CON – C8h T2CON – C8h T2CON – C8h T2CON – C8h T2CON – C8h T2CON – C8h T2MOD – C9h T2MOD – C9h CKCON – 8Eh CKMOD – 96h TL2 – CCh TH2 – CDh RCAP2L – CAh RCAP2H – CBh

T2CON.7 T2CON.6 T2CON.5 T2CON.4 T2CON.3 T2CON.2 T2CON.1 T2CON.0 T2MOD.1 T2MOD.0 CKCON.5 CKMOD.5

TIMER 2

TIMER 1

TIMER 0

Table 11-1. Programmable Timers

TIMER 0, TIMER 1 MODES Timers 0 and 1 both have three common operating modes. They are 13-bit timer/counter, 16-bit timer/counter, and 8-bit timer/counter with autoreload. Timer 0 can additionally be configured to operate as two 8-bit timers. These four modes, controlled by the TMOD register, are detailed in the following pages.

MODE 0 Mode 0 configures either timer 0 or timer 1 for operation as a 13-bit timer/counter. As shown in Figure 11-1, setting TMOD register bits M1, M0 = 00b selects this operating mode for either timer 0 or timer 1. When using timer 0, TL0 uses only bits 0 through 4. These bits serve as the 5 LSbs of the 13-bit timer. TH0 provides the 8 MSbs of the 13-bit timer. Bit 4 of TL0 is used as a ripple out to TH0 bit 0, thereby completely bypassing bits 5 through 7 of TL0. Once the timer is started using the TR0 (TCON.4) timer enable, the timer counts as long as GATE (TMOD.3) is 0 or GATE is 1 and pin INTO is 1. It counts oscillator or system clock cycles if C/T (TMOD.2) is set to a logic 0 and 1 to 0 transitions on T0 (P3.4) if C/T is set to a 1. When the 13bit count reaches 1FFFh (all ones), the next count causes it to roll over to 0000h. The TF0 (TCON.5) flag is set and an interrupt occurs if enabled. The upper 3 bits of TL0 are indeterminate.

97

_____________________________________________________________________________________________

Ultra-High-Speed Flash Microcontroller User’s Guide Table 12-5. Timer 1 Input Clock Frequency SYSTEM CLOCK MODE

PMR REGISTER BITS 4X/2X, CD1, CD0

Crystal multiply mode 4X Crystal multiply mode 2X Divide-by-1 (default) Power-management mode (/1024)

100 000 X01, X10 X11

TIMER 1 INPUT CLOCK FREQUENCY T1MH,T1M = 00 OSC / 12 OSC / 12 OSC / 12 OSC / 3072

T1MH,T1M = 01 OSC / 1 OSC / 2 OSC / 4 OSC / 1024

T1MH,T1M = 1X OSC / 0.25 OSC / 0.5 OSC / 1 OSC / 1024

Using timer 1 in the 8-bit autoreload mode, serial port baud rates for mode 1 or 3 can be calculated using the formula below.

Modes 1, 3 baud rate =

2 SMOD_x 32

✕

Timer 1 input clock frequency (256 - TH1)

Number of serial bits / Number of timer 1 rollovers

Timer 1 rollover frequency

Timer 1 input clock frequency can be found in the previous table, SMOD_x is the logic state of the baud-rate doubler bit for the associated UART, and TH1 is the user assigned timer 1 reload value. Often, users already know what baud rate is desired and only need to calculate the timer reload value. An equation to calculate the timer reload value, TH1, is as follows:

2 SMOD_x TH1 = 256 -

✕

timer 1 input clock frequency 32 ✕ baud rate

Note that the 8-bit, autoreload mode for timer 1 is the one most commonly used for serial port applications, but that it can actually be configured in any mode, even as a counter.

Using Timer 2 for Baud-Rate Generation To use timer 2 as baud-rate generator for serial port 0, the timer is configured in autoreload mode. Then, either the TCLK or RCLK bit (or both) are set to a logic 1. TCLK = 1 selects timer 2 as the baud-rate generator for the transmitter and RCLK = 1 selects timer 2 for the receiver. Thus, serial port 0 can have the transmitter and receiver operating at different baud rates by choosing timer 1 for one data direction and timer 2 for the other. RCLK and TCLK reside in T2CON.4 and TCON.5, respectively. Although the timer 2 input clock can be configured similarly to timer 1, it must be placed into a baud-rate generator mode in order to be used by serial port 0. Setting either RCLK or TCLK to a logic 1 selects timer 2 for baud-rate generation. When this is done, the timer 2 input clock becomes fixed to the oscillator frequency divided by 2. This is compatible with the 80C32. The only exception is when timer 2 is used for baud-rate generation within power-management mode. For PMM, the system clock (OSC/1024) is used as the input clock for timer 2. The timer 2 interrupt is automatically disabled when either RCLK or TCLK is set. Also, the TF2 (TCON.7) flag is not set on a timer rollover. The manual reload pin, T2EX (P1.1), does not cause a reload either. Table 12-6 illustrates this relationship.

Table 12-6. Timer 2 Baud-Rate Generation

111

SYSTEM CLOCK MODE

PMR REGISTER BITS 4X/2X, CD1, CD0

TIMER 2 INPUT CLOCK FREQUENCY BAUD-RATE GENERATOR MODE (RCLK OR TCLK = 1)

Crystal multiply mode 4X Crystal multiply mode 2X Divide-by-1 (default) Power-management mode (/1024)

100 000 X01, X10 X11

OSC / 2 OSC / 2 OSC / 2 OSC / 1024

____________________________________________________________________________________________

Ultra-High-Speed Flash Microcontroller User’s Guide Serial Program Load Operation Program loading through a serial port is a convenient method of loading application software into the flash memory or external memory. Communication is performed over a standard, asynchronous serial communications port using a terminal emulator program with 8-N-1 (8 data bits, no parity, 1 stop bit) protocol settings. A typical application would use a simple RS-232 serial interface to in-system program the device as part of a final production procedure. The hardware configuration for the serial program load operation is illustrated in Figure 15-2. A variety of crystals can be used to produce standard baud rates. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, transmit, and ground wires are all that are necessary to establish communication with the device. The serial loader implements an easy-to-use command line interface, which allows an Intel hex file to be loaded and read back from the device. Intel hex is the standard format output by 8051 cross-assemblers. TO PC TD ROOUT

RXDO

TOOUT DS232A TOIN

TXDO

ROIN RD

DTR R1IN

R1OUT

T1OUT

T1IN

DS89C420 VCC

RST

EA

PSEN

HC/AC125 Figure 15-2. Serial Load Hardware Configuration

AUTOBAUD-RATE DETECTION The serial bootstrap loader can automatically detect, within certain limits, the external baud rate and configure itself to that speed. The loader controls serial port 0 in mode 1 (asynchronous, 1 start bit, 8 data bits, no parity, 1 stop bit, full duplex), using timer 1 in 8-bit autoreload mode with the serial port 0 doubler bit (PCON.7) set. For these settings, an equation to calculate possible serial loader baud rates is provided as a function of crystal frequency and timer reload value. Table 15-1 shows baud rates generated using the equation:

Serial Loader_Baud rate =

Crystal Frequency 192 x ( 256-Timer Reload )

** Timer reload values attempted by the loader: FF, FE, FD, FC, FB, FA, F8, F6, F5, F4, F3, F0, EC, EA, E8, E6, E0, DD, D8, D4, D0, CC, C0, BA, B0, A8, A0, 98, 80, 60, 40 When communicating with a PC COM port having a standard 8250/16450 UART, attempt to match the loader baud rate and PC COM port baud rate within 3% in order to maintain a reliable communication channel. If baud rates cannot be matched exactly, it is suggested configuring the loader to the faster baud rate to avoid the possibility of overflowing the DS89C420 serial input buffer.

129

____________________________________________________________________________________________

Ultra-High-Speed Flash Microcontroller User’s Guide USER CODE IN-APPLICATION PROGRAMMING MODE The DS89C420 data sheet contains the most comprehensive information relating to the in-application programming mode. Additional supporting information can be found in the SFR definitions of FCNTL (D5h) and FDATA (F6h) of this user’s guide.

INTEL HEX FILE FORMAT Assemblers that are 8051-compatible assemblers produce an absolute output file in Intel hex format. These files are composed of a series of records. Records in an Intel hex file have the following format:

The specific record elements are detailed as follows: : II aaaa tt dddddd ... dd xx where: :

Indicates a record beginning

II

Indicates the record length

aaaa

Indicates the 16-bit load address

tt

Indicates the record type

dd

Indicates hex data

xx

Indicates the checksum = (two’s complement (II+aa+a+tt+dd+dd+...dd)

Record type 00 indicates a data record and type 01 indicates an end record. An end record appears as :00 00000 01 FF. These are the only valid record types for a NIL hex file. Spaces are provided for clarity. The following is a short Intel hex file. The data bytes begin at 01 and count up to 2F. Notice the record’s length, beginning address, and record type at the start of each line and the checksum at the end: :200000000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20D0 :0F0020002122232425262728292A2B2C2D2E2F79 :00000001FF

REVISION HISTORY January 24, 2001 Original Issue October 3, 2002 Revision 1

135

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     
  
 SLCS115E − DECEMBER 1986 − REVISED JULY 2003

D Very Low Power . . . 110 µW Typ at 5 V D Fast Response Time . . . tPLH = 2.5 µs Typ

D, JG, P, OR PW PACKAGE (TOP VIEW)

With 5-mV Overdrive

1OUT 1IN − 1IN + GND

D Single Supply Operation:

8

2

7

3

6

4

5

VDD 2OUT 2IN − 2IN +

FK PACKAGE (TOP VIEW)

NC 1OUT NC VDD NC

description The TLC193 and TLC393 consist of dual independent micropower voltage comparators designed to operate from a single supply. They are functionally similar to the LM393 but uses one-twentieth the power for similar response times. The open-drain MOS output stage interfaces to a variety of loads and supplies. For a similar device with a push-pull output configuration (see the TLC3702 data sheet).

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

NC GND NC

NC 1IN − NC 1IN + NC

Texas Instruments LinCMOS process offers superior analog performance to standard CMOS processes. Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias currents, the LinCMOS process offers extremely stable input offset voltages, even with differential input stresses of several volts. This characteristic makes it possible to build reliable CMOS comparators.

NC 2OUT NC 2IN − NC

2IN+ NC

D

TLC393C . . . 3 V to 16 V TLC393I . . . 3 V to 16 V TLC393Q . . . 4 V to 16 V TLC393M . . . 4 V to 16 V TLC193M . . . 4 V to 16 V On-Chip ESD Protection

1

NC − No internal connection

symbol (each comparator) IN + OUT IN −

The TLC393C is characterized for operation over the commercial temperature range of TA = 0°C to 70°C. The TLC393I is characterized for operation over the extended industrial temperature range of TA = −40°C to 85°C. The TLC393Q is characterized for operation over the full automotive temperature range of TA = −40°C to 125°C. The TLC193M and TLC393M are characterized for operation over the full military temperature range of TA = −55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. Copyright  1986-2003, Texas Instruments Incorporated

 
 
   !"   #!$%  &"' &!    #"   #" (" " 
") !" && *+' &!  # ", &"  " "%+  %!&" ",  %% #""'

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

•

1



     
  
 SLCS115D − DECEMBER 1986 − REVISED JULY 2003

AVAILABLE OPTIONS PACKAGES TA

VIOmax at 25°C

0°C to 70°C

SMALL OUTLINE (D)

CHIP CARRIER (FK)

CERAMIC DIP (JG)

PLASTIC DIP (P)

TSSOP (PW)

5 mV

TLC393CD

—

—

TLC393CP

TLC393CPWLE

− 40°C to 85°C

5 mV

TLC393ID

—

—

TLC393IP

TLC393IPWLE

− 40°C to 125°C

5 mV

TLC393QD

—

—

—

—

− 55°C to 125°C

5 mV

TLC393MD

TLC193MFK

TLC193MJG

TLC393MP

—

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC393CDR).

schematic OUT

OPEN-DRAIN CMOS OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 16 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range: TLC393C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC393I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C TLC393Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 125°C TLC393M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C TLC193M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN −. DISSIPATION RATING TABLE PACKAGE

2

TA ≤ 25°C POWER RATING

DERATING FACTOR ABOVE TA = 25°C

TA = 70°C POWER RATING

TA = 85°C POWER RATING

TA = 125°C POWER RATING

D

725 mW

5.8 mW/°C

464 mW

377 mW

145 mW

FK

1375 mW

11.0 mW/°C

880 mW

715 mW

275 mW

JG

1050 mW

8.4 mW/°C

672 mW

546 mW

210 mW

P

1000 mW

8.0 mW/°C

640 mW

520 mW

—

PW

525 mW

4.2 mW/°C

336 mW

273 mW

—

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

•



     
  
 SLCS115E − DECEMBER 1986 − REVISED JULY 2003

recommended operating conditions TLC393C Supply voltage, VDD Common-mode input voltage, VIC

MIN

NOM

3

5

−0.2

Low-level output current, IOL Operating free-air temperature, TA

UNIT

MAX 16

V

VDD − 1.5 20

V mA

70

°C

0

electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER

VIO

Inp t offset voltage Input oltage

IIO

Inp t offset ccurrent Input rrent

TEST CONDITIONS† VIC = VICRmin, VDD = 5 V to 10 V, V See Note 3

TLC393C TA

MIN

25°C

VICR

Common mode inp Common-mode inputt voltage oltage range

kSVR

Common-mode Common mode rejection ratio

Supply-voltage Su ly voltage rejection ratio

VIC = 2.5 25V

1

70°C

VIC = 2.5 25V

0°C to 70°C

VIC = VICRmin

VDD = 5 V to 10 V

Lo le el o tp t voltage oltage Low-level output

VID = −1 1 V, V IOL = 6 mA

IOH

High le el o High-level output tp t ccurrent rrent

VID = 1 V, V

0.3

Supply current (both comparators)

Outputs low, low No load

0 to VDD − 1 0 to VDD − 1.5

nA V

84

70°C

84

0°C

84

25°C

85

70°C

85

0°C

85

25°C

300

70°C

dB

dB 400 650

mV

0.8

40

nA

1

µA

22

40

70°C 25°C

nA pA

0.6

25°C

25°C VO = 5 V

pA

5

70°C

VOL

IDD

5 mV

25°C

CMMR

1.4

UNIT

6.5

25°C Inp t bias current Input c rrent

MAX

0°C to 70°C 25°C

IIB

TYP

0°C to 70°C

50

µA

† All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

•

3

®

OPT101

MONOLITHIC PHOTODIODE AND SINGLE-SUPPLY TRANSIMPEDANCE AMPLIFIER FEATURES

DESCRIPTION

● SINGLE SUPPLY: +2.7 to +36V

The OPT101 is a monolithic photodiode with on-chip transimpedance amplifier. Output voltage increases linearly with light intensity. The amplifier is designed for single or dual power supply operation, making it ideal for battery operated equipment.

● PHOTODIODE SIZE: 0.090 x 0.090 inch ● INTERNAL 1MΩ FEEDBACK RESISTOR ● HIGH RESPONSIVITY: 0.45A/W (650nm) ● BANDWIDTH: 14kHz at RF = 1MΩ ● LOW QUIESCENT CURRENT: 120µA

The integrated combination of photodiode and transimpedance amplifier on a single chip eliminates the problems commonly encountered in discrete designs such as leakage current errors, noise pick-up and gain peaking due to stray capacitance. The 0.09 x 0.09 inch photodiode is operated in the photoconductive mode for excellent linearity and low dark current. The OPT101 operates from +2.7V to +36V supplies and quiescent current is only 120µA. It is available in clear plastic 8-pin DIP, 5-pin SIP and J-formed DIP for surface mounting. Temperature range is 0°C to 70°C.

● AVAILABLE IN 8-PIN DIP, 5-PIN SIP, AND 8-LEAD SURFACE MOUNT PACKAGES

APPLICATIONS ● MEDICAL INSTRUMENTATION ● LABORATORY INSTRUMENTATION ● POSITION AND PROXIMITY SENSORS ● PHOTOGRAPHIC ANALYZERS ● BARCODE SCANNERS ● SMOKE DETECTORS ● CURRENCY CHANGERS

3pF 1MΩ

4 (4)

8pF

5 (5) 7.5mV

λ

Infrared

0.6

0.5

0.5 Using Internal 1MΩ Resistor

0.4

0.4

0.3

0.3

0.2

0.2

0.1

0.1

0 VB

200 OPT101

(1) 8 (SIP)

300

400

500 600 700 800 Wavelength (nm)

900

Photodiode Responsivity (A/W)

0.6

(2) 1

Voltage Output (V/µW)

2

0.7 Red

V+

Blue

(Pin available on DIP only.)

Ultraviolet

Green Yellow

SPECTRAL RESPONSIVITY

0.7

0 1000 1100

(3) 3 DIP

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ®

©

SBBS002

1994 Burr-Brown Corporation

PDS-1257D 1

OPT101

Printed in U.S.A. March, 1998

SPECIFICATIONS At TA = +25°C, VS = +2.7V to +36V, λ = 650nm, internal 1MΩ feedback resistor, and RL = 10kΩ, unless otherwise noted. OPT101P, W PARAMETER

CONDITIONS

RESPONSIVITY Photodiode Current Voltage Output vs Temperature Unit to Unit Variation Nonlinearity(1) Photodiode Area DARK ERRORS, RTO(2) Offset Voltage, Output vs Temperature vs Power Supply Voltage Noise, Dark, fB = 0.1Hz to 20kHz

MIN

650nm 650nm 650nm FS Output = 24V (0.090 x 0.090in) (2.29 x 2.29mm)

+5 VS = +2.7V to +36V VS = +15V, VPIN3 = –15V

POWER SUPPLY Operating Voltage Range Quiescent Current

+7.5 ±2.5 10 300

1 ±0.5 ±0.5 ±50 VOUT = 10Vp-p VOUT = 10V Step VOUT = 10V Step

100%, Return to Linear Operation

OUTPUT Voltage Output, High Capacitive Load, Stable Operation Short-Circuit Current

MAX

0.45 0.45 100 ±5 ±0.01 0.008 5.2

TRANSIMPEDANCE GAIN Resistor Tolerance, P W vs Temperature FREQUENCY RESPONSE Bandwidth Rise Fall Time, 10% to 90% Settling Time, 0.05% 0.1% 1% Overload Recovery

TYP

(VS) – 1.3 VS = 36V

+10 100

±2

mV µV/°C µV/V µVrms MΩ % % ppm/°C

kHz µs µs µs µs µs

(VS) – 1.15 10 15

V nF mA

120 220

TEMPERATURE RANGE Specification Operating Storage Thermal Resistance, θJA

A/W V/µW ppm/°C % % of FS in2 mm2

14 28 160 80 70 50

+2.7 Dark, VPIN3 = 0V RL = ∞, VOUT = 10V

UNITS

0 0 –25

+36 240

V µA µA

+70 +70 +85

°C °C °C °C/W

MAX

UNITS

100

NOTES: (1) Deviation in percent of full scale from best-fit straight line. (2) Referred to Output. Includes all error sources.

PHOTODIODE SPECIFICATIONS TA = +25°C, VS = +2.7V to +36V unless otherwise noted. Photodiode of OPT101P PARAMETER

CONDITIONS

Photodiode Area Current Responsivity Dark Current vs Temperature Capacitance

MIN

(0.090 x 0.090in) (2.29 x 2.29mm) 650nm 650nm VDIODE = 7.5mV

TYP 0.008 5.2 0.45 865 2.5 doubles every 7°C 1200

in2 mm2 A/W µA/W/cm2 pA pF

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

OPT101

2

OP AMP SPECIFICATIONS At TA = +25°C, VS = +2.7V to +36V, λ = 650nm, internal 1MΩ feedback resistor, and RL = 10kΩ, unless otherwise noted. OPT101 Op Amp(1) PARAMETER INPUT Offset Voltage vs Temperature vs Power Supply Input Bias Current vs Temperature Input Impedance Differential Common-Mode Common-Mode Input Voltage Range Common-Mode Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

±0.5 ±2.5 10 165 1

mV µV/°C µV/V pA pA/°C

400 || 5 250 || 35 0 to [(VS) – 1] 90

MΩ || pF GΩ || pF V dB

OPEN-LOOP GAIN Open-loop Voltage Gain

90

dB

FREQUENCY RESPONSE Gain-Bandwidth Product(2) Slew Rate Settling Time 1% 0.1% 0.05%

2 1 5.8 7.7 8.0

MHz V/µs µs µs µs

(VS) – 1.15 15

V mA

OUTPUT Voltage Output, High Short-Circuit Current POWER SUPPLY Operating Voltage Range Quiescent Current

(–) Input (–) Input

Linear Operation

(VS) – 1.3 VS = +36V +2.7 Dark, VPIN3 = 0V RL ∞, VOUT = 10V

120 220

+36 240

V µA µA

NOTES: (1) Op amp specifications provided for information and comparison only. (2) Stable gains ≥ 10V/V.

®

3

OPT101

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

D D D D D D

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

SN54LS373, SN54LS374, SN54S373, SN54S374 . . . J OR W PACKAGE SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE SN74LS374 . . . DB, DW, N, OR NS PACKAGE SN74S373 . . . DW OR N PACKAGE (TOP VIEW)

OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND

description

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q C†

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374. SN54LS373, SN54LS374, SN54S373, SN54S374 . . . FK PACKAGE (TOP VIEW)

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

2D 2Q 3Q 3D 4D

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

8D 7D 7Q 6Q 6D

4Q GND C† 5Q 5D

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

20

2

1D 1Q OC VCC 8Q

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

1

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† (’LS devices) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions SN54LS’ MIN

NOM

4.5

5

SN74LS’ MAX

MIN

NOM

MAX

5

4.75

5

5.25

UNIT

VCC VOH

Supply voltage High-level output voltage

5.5

5.5

V

IOH IOL

High-level output current

–1

–2.6

mA

24

mA

Low-level output current

tw

Pulse duration

tsu

Data setup time

th

Data hold time

12 CLK high

15

15

CLK low

15

15

’LS373

5↓

5↓

’LS374

20↑

20↑

’LS373 ’LS374‡

20↓

20↓

5↑

0↑

V

ns ns ns

TA Operating free-air temperature –55 125 0 70 °C ‡ The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS†

PARAMETER

MIN

SN54LS’ TYP‡ MAX

2

MIN

SN74LS’ TYP‡ MAX

2

UNIT

VIH VIL

High-level input voltage

VIK

Input clamp voltage

VCC = MIN,

II = –18 mA

VOH

High level output voltage High-level

VCC = MIN,, VIL = VIL max,

VIH = 2 V,, IOH = MAX

VOL

Low level output voltage Low-level

VCC = MIN,, VIL = VIL max

VIH = 2 V,,

VCC = MAX,, VO = 2.7 V

VIH = 2 V,,

20

20

m

A

m

A

Low-level input voltage

Off-state output current,, IOZH high-level voltage applied

24 2.4 IOL = 12 mA IOL = 24 mA

0.8

V

–1.5

–1.5

V

34 3.4 0.25

V

0.7

24 2.4

31 3.1

0.4

V

0.25

0.4

0.35

0.5

IOZL

Off-state output current,, low-level voltage applied

VCC = MAX,, VO = 0.4 V

VIH = 2 V,,

–20 20

–20 20

II

Input current at maximum input voltage

VCC = MAX MAX,

VI = 7 V

01 0.1

01 0.1

VI = 2.7 V VI = 0.4 V

20

20

IIH IIL

High-level input current Low-level input current

VCC = MAX, VCC = MAX,

IOS

Short-circuit output current§

VCC = MAX

ICC

Supply current

VCC = MAX,, Output control at 4.5 V

–0.4 –30

–130

–30

V

mA m

A

–0.4

mA

–130

mA

’LS373

24

40

24

40

’LS374

27

40

27

40

mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER

FROM (INPUT)

TO (OUTPUT)

TEST CONDITIONS

’LS373 MIN

TYP

’LS374 MAX

RL = 667 Ω, CL = 45 pF, See Note 3

fmax

MIN

TYP

35

50

MAX

MHz

tPLH tPHL

Data

Any Q

RL = 667 Ω, CL = 45 pF,, See Note 3

12

18

12

18

tPLH tPHL

C or CLK

Any Q

RL = 667 Ω, CL = 45 pF,, See Note 3

20

30

15

28

18

30

19

28

tPZH tPZL

Any Q

RL = 667 Ω, CL = 45 pF,, See Note 3

15

28

20

26

OC

25

36

21

28

25

15

28

Any Q

RL = 667 Ω, CL = 5 pF

15

OC

12

20

12

20

tPHZ tPLZ

UNIT

ns ns ns

ns

NOTE 3: Maximum clock frequency is tested with all outputs loaded. fmax = maximum clock frequency tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output tPZH = output enable time to high level tPZL = output enable time to low level tPHZ = output disable time from high level tPLZ = output disable time from low level

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

7

LMD18200 3A, 55V H-Bridge General Description The LMD18200 is a 3A H-Bridge designed for motion control applications. The device is built using a multi-technology process which combines bipolar and CMOS control circuitry with DMOS power devices on the same monolithic structure. Ideal for driving DC and stepper motors; the LMD18200 accommodates peak output currents up to 6A. An innovative circuit which facilitates low-loss sensing of the output current has been implemented.

Features n n n n

Delivers up to 3A continuous output Operates at supply voltages up to 55V Low RDS(ON) typically 0.3Ω per switch TTL and CMOS compatible inputs

n n n n n n

No “shoot-through” current Thermal warning flag output at 145˚C Thermal shutdown (outputs off) at 170˚C Internal clamp diodes Shorted load protection Internal charge pump with external bootstrap capability

Applications n n n n n

DC and stepper motor drives Position and velocity servomechanisms Factory automation robots Numerically controlled machinery Computer printers and plotters

Functional Diagram

DS010568-1

FIGURE 1. Functional Block Diagram of LMD18200

© 1999 National Semiconductor Corporation

DS010568

www.national.com

LMD18200 3A, 55V H-Bridge

December 1999

Power Dissipation (TA = 25˚C, Free Air) Junction Temperature, TJ(max) ESD Susceptibility (Note 4) Storage Temperature, TSTG Lead Temperature (Soldering, 10 sec.)

Total Supply Voltage (VS, Pin 6) Voltage at Pins 3, 4, 5, 8 and 9 Voltage at Bootstrap Pins (Pins 1 and 11) Peak Output Current (200 ms) Continuous Output Current (Note 2) Power Dissipation (Note 3)

60V 12V

3W 150˚C 1500V −40˚C to +150˚C 300˚C

Operating Ratings(Note 1)

VOUT +16V 6A 3A 25W

Junction Temperature, TJ VS Supply Voltage

−40˚C to +125˚C +12V to +55V

Electrical Characteristics (Note 5) The following specifications apply for VS = 42V, unless otherwise specified. Boldface limits apply over the entire operating temperature range, −40˚C ≤ TJ ≤ +125˚C, all other limits are for TA = TJ = 25˚C. Symbol RDS(ON)

Switch ON Resistance

VCLAMP

Clamp Diode Forward Drop

Conditions Output Current = 3A (Note 6) Output Current = 6A (Note 6) Clamp Current = 3A (Note 6)

VIL

Logic Low Input Voltage

Pins 3, 4, 5

RDS(ON)

Parameter Switch ON Resistance

IIL

Logic Low Input Current

VIN = −0.1V, Pins = 3, 4, 5

VIH

Logic High Input Voltage

Pins 3, 4, 5

IIH

Logic High Input Current Current Sense Output

VIN = 12V, Pins = 3, 4, 5 IOUT = 1A (Note 8)

Typ

Limit

Units

0.33

0.4/0.6

Ω (max)

0.33

0.4/0.6

Ω (max)

1.2

1.5

V (max)

377

−0.1

V (min)

0.8

V (max)

−10

µA (max)

2

V (min)

12

V (max)

10

µA (max)

325/300

µA (min)

425/450

µA (max)

Current Sense Linearity

1A ≤ IOUT ≤ 3A (Note 7)

Undervoltage Lockout

Outputs turn OFF

TJW

Warning Flag Temperature

VF(ON)

Flag Output Saturation Voltage

0.15

IF(OFF)

Flag Output Leakage

Pin 9 ≤ 0.8V, IL = 2 mA TJ = TJW, IL = 2 mA VF = 12V

TJSD

Shutdown Temperature

Outputs Turn OFF

170

IS

Quiescent Supply Current

All Logic Inputs Low

13

tDon

Output Turn-On Delay Time

Sourcing Outputs, IOUT = 3A

300

ns

300

ns

Output Turn-On Switching Time

Sinking Outputs, IOUT = 3A Bootstrap Capacitor = 10 nF

100

ns

80

ns

Output Turn-Off Delay Times

Sourcing Outputs, IOUT = 3A Sinking Outputs, IOUT = 3A Sourcing Outputs, IOUT = 3A

200

ns

200

ns

Output Turn-Off Switching Times

Sinking Outputs, IOUT = 3A Bootstrap Capacitor = 10 nF

ton

tDoff toff

Sourcing Outputs, IOUT = 3A Sinking Outputs, IOUT = 3A

±6

±9

%

9

V (min)

11

V (max)

145 0.2

˚C V 10

µA (max)

25

mA (max)

˚C

75

ns

70

ns

tpw

Minimum Input Pulse Width

Pins 3, 4 and 5

1

µs

tcpr

Charge Pump Rise Time

No Bootstrap Capacitor

20

µs

3

www.national.com

LMD18200

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

LMD18200

Pinout Description (See Connection Diagram) (Continued) Pin 6, VS Power Supply Pin 7, GROUND Connection: This pin is the ground return, and is internally connected to the mounting tab. Pin 8, CURRENT SENSE Output: This pin provides the sourcing current sensing output signal, which is typically 377 µA/A. Pin 9, THERMAL FLAG Output: This pin provides the thermal warning flag output signal. Pin 9 becomes active-low at 145˚C (junction temperature). However the chip will not shut itself down until 170˚C is reached at the junction. Pin 10, OUTPUT 2: Half H-bridge number 2 output.

DS010568-4

FIGURE 2. Locked Anti-Phase PWM Control Sign/magnitude PWM consists of separate direction (sign) and amplitude (magnitude) signals (see Figure 3). The (absolute) magnitude signal is duty-cycle modulated, and the absence of a pulse signal (a continuous logic low level) represents zero drive. Current delivered to the load is proportional to pulse width. For the LMD18200, the DIRECTION input (pin 3) is driven by the sign signal and the PWM input (pin 5) is driven by the magnitude signal.

Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for Half H-bridge number 2. The recommended capacitor (10 nF) is connected between pins 10 and 11. TABLE 1. Logic Truth Table PWM

Dir

Brake

H

H

L

Source 1, Sink 2

Active Output Drivers

H

L

L

Sink 1, Source 2

L

X

L

Source 1, Source 2

H

H

H

Source 1, Source 2

H

L

H

Sink 1, Sink 2

L

X

H

NONE

Application Information TYPES OF PWM SIGNALS The LMD18200 readily interfaces with different forms of PWM signals. Use of the part with two of the more popular forms of PWM is described in the following paragraphs. Simple, locked anti-phase PWM consists of a single, variable duty-cycle signal in which is encoded both direction and amplitude information (see Figure 2). A 50% duty-cycle PWM signal represents zero drive, since the net value of voltage (integrated over one period) delivered to the load is zero. For the LMD18200, the PWM signal drives the direction input (pin 3) and the PWM input (pin 5) is tied to logic high.

www.national.com

DS010568-5

FIGURE 3. Sign/Magnitude PWM Control SIGNAL TRANSITION REQUIREMENTS To ensure proper internal logic performance, it is good practice to avoid aligning the falling and rising edges of input signals. A delay of at least 1 µsec should be incorporated between transitions of the Direction, Brake, and/or PWM input signals. A conservative approach is be sure there is at least 500ns delay between the end of the first transition and the beginning of the second transition. See Figure 4.

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Continental Device India Limited An ISO/TS16949 and ISO 9001 Certified Company

NPN SILICON PLANAR SWITCHING TRANSISTORS

2N2221A 2N2222A TO-18

Switching And Linear Application DC And VHF Amplifier Applications ABSOLUTE MAXIMUM RATINGS DESCRIPTION

SYMBOL

2N2221A,22A

UNIT

VCEO 40 Collector -Emitter Voltage VCBO 75 Collector -Base Voltage VEBO 6.0 Emitter -Base Voltage IC 800 Collector Current Continuous PD 500 Power Dissipation @Ta=25 degC 2.28 Derate Above 25deg C PD 1.2 @ Tc=25 degC 6.85 Derate Above 25deg C Tj, Tstg -65 to +200 Operating And Storage Junction Temperature Range ELECTRICAL CHARACTERISTICS (Ta=25 deg C Unless Otherwise Specified) DESCRIPTION

SYMBOL TEST CONDITION

Collector -Emitter Voltage Collector -Base Voltage Emitter-Base Voltage Collector-Cut off Current

VCEO VCBO VEBO ICBO

Emitter-Cut off Current Base-Cut off Current Collector Emitter Saturation Voltage

Ta=150 deg C VCB=60V, IE=0 ICEX VCE=60V, VEB=3V IEBO VEB=3V, IC=0 IBL VCE=60V, VEB=3V VCE(Sat)* IC=150mA,IB=15mA IC=500mA,IB=50mA VBE(Sat) * IC=150mA,IB=15mA IC=500mA,IB=50mA

Base Emitter Saturation Voltage

Continental Device India Limited

IC=10mA,IB=0 IC=10uA.IE=0 IE=10uA, IC=0 VCB=60V, IE=0

Data Sheet

V V V mA mW mW/deg C W mW/deg C deg C

VALUE MIN MAX 40 75 6.0 10

-

10 10 10 20 0.3 1.0 0.6-1.2 2.0

UNIT V V V nA

uA nA nA nA V V V V

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