1.evolution And Improvement Of Arm Architect.pptx

EVOLUTION AND IMPROVEMENT OF ARM ARCHIETURE

BY ROHINI MYTHILI

WHAT IS ARM?  ARM

- Advanced RISC Machine.  One of the family of RISC architecture.  First RISC microprocessor for commercial use.  ARM makes 32-bit and 64-bit RISC multicore processors.

HISTORY  Developed

by Acorn private limited in Cambridge,in 1980’s.  At initial, it was Acorn RISC Machine  After the joining of apple, it becomes Advanced RISC Machine.

HISTORY VERSION

YEAR

FEATURES

IMPLEMENTATIONS

V1

1985

The first commercial RISC(26 bit)

ARM1

V2 V3

1987 1992

Coprocessor support

ARM2,ARM3

32 bit,MMU,64 bit MAC

ARM6,ARM7

V4

1996

Thumb

ARM7TDMI, ARM8, ARM9TDMI, StrongARM

V5

1999

DSP and Jazelle extensions

ARM10, XScale

V6

2001

SIMD, Thumb-2, TrustZone, multiprocessing

ARM11, ARM11 MPCore

FEATURES   

 



Load/store architecture Auto increment and auto decrement operation Mostly single-cycle execution Enhanced power-saving design 64 and 32 bit execution for scalable high performance Hardware virtualization support

RISC & CISC RISC - Reduced Instruction Set Computer.  RISC’s instruction set architecture(ISA) allows it to have fewer cycles per instruction(CPI) than CISC.  CISC – Complex Instruction Set Computer  CISC is a computer in which single instruction can execute several low-level operation. 

DIFFERENCE BETWEEN RISC & CISC 

The main difference is the number of computing cycles.

REGISTERS System & User R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 (FP) R12 (IP) R13 (SP) R14 (LR) R15 (PC) CPSR

FIQ

Supervisor

Abort

IRQ

Undefined

R0 R1 R2 R3 R4 R5 R6 R7_fiq R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_svc R14_svc R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_abt R14_abt R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_irq R14_irq R15 (PC)

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_und R14_und R15 (PC)

CPSR SPSR_fiq

CPSR SPSR_svc

CPSR SPSR_abt

CPSR SPSR_irq

CPSR SPSR_und

REGISTERS 30 general-purpose registers in 32 bits  First 16 registers are user-level mode USER LEVEL MODE 

General purpose (R0-R11)

Special purpose (R12-R15)

REGISTERS R0-R12 : Used during common operations to store temporary values,pointers etc.  R13(SP) : Stack Pointer: Used to points to top of the stack.  R14(LR) : Link register: When a function call is made, the Link Register gets updated with a memory address referencing the next instruction where the function was initiated from. 

REGISTERS 

R15(PC) : Program counter : The Program Counter is automatically incremented by the size of the instruction executed. This size is always 4 bytes in ARM state and 2 bytes in THUMB mode.

OVERFLOW UNDERFLOW

JAZELLE

E A I F T M

PROCESSOR MODE (PRIVILEGE MODE)

CARRY

GE

THUMB

J

FIQ DISABLE

Q

IRQ DISABLE

V

ABORT DISABLE

C

ENDIANNESS

Z

GREATER THAN OR EQUAL FOR SIMD

N

ZERO



NEGATIVE

REGISTERS

CPSR – Current Program Status Register

CPSR REGISTER N - Enabled if result of the instruction yields a negative number. Z - Enabled if result of the instruction yields a zero value. C - Enabled if result of the instruction yields a value that requires a 33rd bit to be fully represented.

CPSR REGISTER V - Enabled if result of the instruction yields a value that cannot be represented in 32 bit two’s complement.  E - ARM can operate either in little endian, or big endian. This bit is set to 0 for little endian, or 1 for big endian mode.  T - This bit is set if you are in Thumb state and is disabled when you are in ARM state. 

CPSR REGISTER M - These bits specify the current privilege mode (USR, SVC, etc.).  J - Third execution state that allows some ARM processors to execute Java bytecode in hardware. 

PIPELINE ORGANISATION 

Increases speed – most instructions executed in single cycle



Versions:  3-stage

(ARM7TDMI and earlier)

 5-stage

(ARMS, ARM9TDMI)

 6-stage

(ARM10TDMI)

OPERATION MODES 

Seven operating modes: 

User



Privileged:  System

(version 4 and above)

 FIQ  IRQ  Abort  Undefined  Supervisor

exception modes

OPERATION MODES  User

mode: a normal program execution state  FIQ – Fast Interrupt: for fast interrupt handling  IRQ – Normal Interrupt: for general purpose interrupt handling  Supervisor mode (SVC): a protected mode for operating system

OPERATION MODES Abort mode:  when a data or instruction pre-fetch is aborted  –  Undefined mode:  when an undefined instruction is executed  –  System mode:  a privileged user mode for the operating system 

PROCESSOR STATES Arm state:  all instructionsare 32bits long, word-aligned. –  Thumb state:  all instructionsare 16 bits wide, halfwordaligned. –  Jazelle state:  all instructionsare 8 bits wide for JavaBytecode 

INSTRUCTIONS IN ARM ARM Instruction Set : standard 32-bit instruction set  Thumb instruction Set : standard 16-bit instruction set ARM instruction set: 1.Data processing 4.Software interrupt 2.Branch 5.Program status 3.Load/store register 6.Coprocessor 

DATA PROCESSING INSTRUCTION Used to manipulate data in general purpose registers,employ a 3-address format,support barrel shifter. Arithmetic Instruction: ADD,ADC,SUB,SBC,RSB,RSC Move Instruction: MOV,MVN Bit-wise Logical Instruction: AND,EOR,ORR,BIC 

DATA PROCESSING INSTRUCTION Comparison Instruction: TST,TEQ,CMP,CMN Multiply Instruction: MUL,MLA EXAMPLE: r0=0x00000000 r1=0x00000002 r2=0x00000001 ADD r0,r1,r2

INSTRUCTIONS IN ARM 



Branch Instruction: Changes the flow of sequential execution of instructions and force to modify the program counter. Load/Store Instruction: 1.To transfer data between memory and registers. 2.LDR,STR,LDRB,STRB

INSTRUCTIONS IN ARM 



Swap Instruction: 1.to swap the content of memory with the content of registers. 2.SWP,SWPB Software Interrupt Instruction: 1.To call the operating system functions. 2.SWI

INSTRUCTIONS IN ARM 



Program Status Register Instruction: 1.To transfer the content of program status register to/from a general purpose register. 2.MRS,MSR Coprocessor Instruction: 1.To extend the instruction set,control onchip functions. 2.CDP,MRC/MCR,LDC/STC

DIFFERNCE BETWEEN ARM & 8051 ARM PROCESSOR: 1.ARM executes almost all the instruction in only One cycle. 2.RISC based architecture 3.Based on load store Architecture.

8051 MICROCONTROLLER 1.It takes more than one cycle except register Transfer. 2.CISC based architecture 3.Can access memory Directly.

APPLICATIONS Mobile phones  Patient monitoring  Automotive power train  Anti lock braking  High end washing machine  Image processing 

ARM BASED PROCESSOR

MERITS Low power consumption  Cost sensitive embedded application  Cheap  Easy to develop  High performance  Low code size  Increases speed 

DEMERITS 

Need all software’s to be developed for new architecture.