Vlsi Ieee 2009 Projects @ Hades Infotech
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Hades InfoTech Pvt. Ltd VLSI IEEE 2009 Projects IEEE YEAR 2009
CODE VIE01
VLSI PROJECTS A Dual-Purpose Real/Complex Logarithmic Number System ALU
VIE02
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications An Asynchronous Field-Programmable VLSI using LEDR/4-Phase-Dual-Rail Protocol Converter Design and FPGA Implementation of High Speed, Low Power Digital Up Converter for Power Line Communication Systems Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters
2009
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations Efficient Asynchronous Protocol Efficient Asynchronous Protocol Converters for Two Converters for Two-Phase Delay Phase Delay- Insensitive Global
2009
VIE03 VIE04 VIE05 VIE06 VIE07
2009 2009 2009
2009
Communication VIE08
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
2009
VIE09
2009
VIE10
On the Exploitation of Narrow-Width Values for Improving Register File Reliability 81.6 GOPS Object Recognition Processor Based on a Memory-Centric NOC
VIE11
Low-Power, High-Speed Transceivers for Network-on-Chip Communication
2009
VIE12
Low-Power Programmable FPGA Routing Circuitry
2009
VIE13
Design and Implementation of a Field Programmable CRC Circuit Architecture
2009
VIE14
Scalable MIMO Queues With Application to Variation-Tolerant Architectures
2009
VIE15
Fault Secure Encoder and Decoder for Nano Memory Applications
2009
VIE16
2009
VIE17
A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment Multi-GB/s LDPC Code Design and Implementation
VIE18
High-Throughput Layered LDPC Decoding Architecture
2009
VIE19
Custom Floating-Point Unit Generation for Embedded Systems
2009
VIE20
An improved RC6 algorithm with same structure of encryption and decryption
2009
VIE21
Left to Right Serial Multiplier for Large Numbers on FPGA
2009
VIE22
Superscalar Power Efficient Fast Fourier Transform FFT Architecture
2009
VIE23
A New High-Speed Architecture for Reed-Solomon Decoder
2009
VIE24
Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits
2009
175, First Floor, Kodambakkam Road, Saidapet, Chennai-15 Ph: 044-43322196, Mobile: 9840989556, 9894229496 Mail: [email protected], [email protected] www.hades.in Our branches are in Madurai, Trichy, Salem, Vellore.
2009
2009
Page |1
Hades InfoTech Pvt. Ltd IEEE YEAR 2009
CODE VIE25
VLSI PROJECTS Hardware Algorithm for Variable Precision Multiplication on FPGA
VIE26
A Compact AES Encryption Core on Xilinx FPGA
2009
VIE27
2009
VIE28
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique A Low-Resource AES Encryption Circuit Using Dynamic Reconfiguration
VIE29
HDL Implementation Of Error Detection And Correction Circuit.
2008
VIE30
Generalized Matrix Method for Efficient Residue to Decimal Conversion
2008
VIE31
A Novel Reversible BCD Adder for Nanotechnology Based Systems
2008
VIE32
2008
VIE34
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined FloatingPoint Cores A Novel Carry-look ahead approach to an Unified BCD and Binary Adder/Subtractor Single-precision logarithmic arithmetic unit with floating-point input/output data
VIE35
BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
2008
VIE36
FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating. FPGA Implementation(S) of a Scalable Encryption Algorithm
2008
System Architecture and Implementation of MIMO Sphere Decoders On FPGA Designing Efficient Online Testable Reversible Adders with New Reversible Gate FPGA Implementation of Low Power Parallel Multiplier
2008
2008
VIE42
A Full-Adder-Based Methodology for the Design of Scaling Operation In Residue Number System Design Of Advanced Encryption Standard Using VHDL
VIE43
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
2007
VIE44
Concurrent Error Detection in Reed–Solomon Encoders and Decoders
2007
VIE45
Compact Hardware Design of Whirlpool Hashing Core
2007
VIE33
VIE37 VIE38 VIE39 VIE40 VIE41
175, First Floor, Kodambakkam Road, Saidapet, Chennai-15 Ph: 044-43322196, Mobile: 9840989556, 9894229496 Mail: [email protected], [email protected] www.hades.in Our branches are in Madurai, Trichy, Salem, Vellore.
2008
2008 2008
2008
2008 2008
2008
Page |2
CODE VIE01
VLSI PROJECTS A Dual-Purpose Real/Complex Logarithmic Number System ALU
VIE02
High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications An Asynchronous Field-Programmable VLSI using LEDR/4-Phase-Dual-Rail Protocol Converter Design and FPGA Implementation of High Speed, Low Power Digital Up Converter for Power Line Communication Systems Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters
2009
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations Efficient Asynchronous Protocol Efficient Asynchronous Protocol Converters for Two Converters for Two-Phase Delay Phase Delay- Insensitive Global
2009
VIE03 VIE04 VIE05 VIE06 VIE07
2009 2009 2009
2009
Communication VIE08
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
2009
VIE09
2009
VIE10
On the Exploitation of Narrow-Width Values for Improving Register File Reliability 81.6 GOPS Object Recognition Processor Based on a Memory-Centric NOC
VIE11
Low-Power, High-Speed Transceivers for Network-on-Chip Communication
2009
VIE12
Low-Power Programmable FPGA Routing Circuitry
2009
VIE13
Design and Implementation of a Field Programmable CRC Circuit Architecture
2009
VIE14
Scalable MIMO Queues With Application to Variation-Tolerant Architectures
2009
VIE15
Fault Secure Encoder and Decoder for Nano Memory Applications
2009
VIE16
2009
VIE17
A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment Multi-GB/s LDPC Code Design and Implementation
VIE18
High-Throughput Layered LDPC Decoding Architecture
2009
VIE19
Custom Floating-Point Unit Generation for Embedded Systems
2009
VIE20
An improved RC6 algorithm with same structure of encryption and decryption
2009
VIE21
Left to Right Serial Multiplier for Large Numbers on FPGA
2009
VIE22
Superscalar Power Efficient Fast Fourier Transform FFT Architecture
2009
VIE23
A New High-Speed Architecture for Reed-Solomon Decoder
2009
VIE24
Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits
2009
175, First Floor, Kodambakkam Road, Saidapet, Chennai-15 Ph: 044-43322196, Mobile: 9840989556, 9894229496 Mail: [email protected], [email protected] www.hades.in Our branches are in Madurai, Trichy, Salem, Vellore.
2009
2009
Page |1
Hades InfoTech Pvt. Ltd IEEE YEAR 2009
CODE VIE25
VLSI PROJECTS Hardware Algorithm for Variable Precision Multiplication on FPGA
VIE26
A Compact AES Encryption Core on Xilinx FPGA
2009
VIE27
2009
VIE28
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique A Low-Resource AES Encryption Circuit Using Dynamic Reconfiguration
VIE29
HDL Implementation Of Error Detection And Correction Circuit.
2008
VIE30
Generalized Matrix Method for Efficient Residue to Decimal Conversion
2008
VIE31
A Novel Reversible BCD Adder for Nanotechnology Based Systems
2008
VIE32
2008
VIE34
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined FloatingPoint Cores A Novel Carry-look ahead approach to an Unified BCD and Binary Adder/Subtractor Single-precision logarithmic arithmetic unit with floating-point input/output data
VIE35
BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
2008
VIE36
FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating. FPGA Implementation(S) of a Scalable Encryption Algorithm
2008
System Architecture and Implementation of MIMO Sphere Decoders On FPGA Designing Efficient Online Testable Reversible Adders with New Reversible Gate FPGA Implementation of Low Power Parallel Multiplier
2008
2008
VIE42
A Full-Adder-Based Methodology for the Design of Scaling Operation In Residue Number System Design Of Advanced Encryption Standard Using VHDL
VIE43
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
2007
VIE44
Concurrent Error Detection in Reed–Solomon Encoders and Decoders
2007
VIE45
Compact Hardware Design of Whirlpool Hashing Core
2007
VIE33
VIE37 VIE38 VIE39 VIE40 VIE41
175, First Floor, Kodambakkam Road, Saidapet, Chennai-15 Ph: 044-43322196, Mobile: 9840989556, 9894229496 Mail: [email protected], [email protected] www.hades.in Our branches are in Madurai, Trichy, Salem, Vellore.
2008
2008 2008
2008
2008 2008
2008
Page |2
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