Vhdl Tutorial Handout

VHDL Basic Terminology

VHDL Tutorial

Five primitive constructs call design units Entity declaration Architecture body Configuration declaration Package declaration Package body

Computer Hardware Laboratory (COEN140)

Reference: Bhasker, J. VHDL Primer, 3rd Ed., Prentice Hall, New Jersey, 1999. Page 1 9/9/2002

Entity Declaration

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Architecture Body

Specifies the name of entity being modeled List the set of interface ports 009010011012013014015016017-

Internal details of an entity Three styles of modeling n

ENTITY byteadd IS PORT ( a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);-- addend byte b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);-- addend byte cin: IN STD_LOGIC; -- carry input bit sum: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);-- sum byte cout: OUT STD_LOGIC-- carry output bit ); END byteadd;

n

n

n

Structural – set of interconnected components Dataflow – set of concurrent assignment statements Behavioral – set of sequential assignment statements Can be combined

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Structural Modeling

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Structural Modeling Example architecture HA_STRUCTURE of HALF_ADDER is component XOR2 port(X,Y:in BIT; Z: out BIT); end component; component AND2 port(L,M:in BIT; N: out BIT); end component; begin X1: XOR2 port map (A,B,SUM); A1: AND2 port map (A,B,CARRY); end HA_STRUCTURE;

Declarative Part n

Specifies the component interfaces

Statement Part n n

Component Instantiation Port Map

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 Copyright Richard J. Povinelli

rev 1.2, 9/9/2002

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Dataflow Modeling

Dataflow Examples architecture HA_CONCURRENT of HALF_ADDER is begin SUM <= A xor B after 8ns; CARRY <= A and B after 4ns; end HA_CONCURRENT;

Concurrent signal assignment statements <=, signal assignment operator After statement n n

architecture ACLOCK of CLOCK is begin CLK <= not CLK after 10ns; end ACLOCK;

States the delay in the assignment Can be left off but implies a delta (standard) delay

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Behavioral Modeling

Behavioral Example I

Sequential Statements n

Placed inside of a process

Process n

Sensitivity list w Process statement is invoked whenever there is an event

on any signals in the list

n

Variable declaration

n

Statements

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w Different from signals, assigned instantaneously w Sequential signal assignment statements

architecture decSequential of decoder is begin process(a,b,enable) variable aBar, bBar: bit; begin aBar := not a; bBar := not b; if enable = ‘1’ then z(3) <= not (a and b); z(0) <= not (aBar and bBar); z(2) <= not (a and bBar); z(1) <= not (aBar and b); else z <= “1111”; end if ; end process; end decSequential;

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Behavioral Example II

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Package Declaration

process (a,b,enable) begin

Store a set of common declarations

clk <= ‘0’; wait for 20 ns;

n n

clk <= ‘1’; wait for 12 ns;

n n

end process ;

Imported with the use clause

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 Copyright Richard J. Povinelli

Components Types Procedures Functions

rev 1.2, 9/9/2002

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Package Declaration Example

Package Body Definitions of items declared in the package declaration

LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE adder IS COMPONENT fulladd PORT ( input0: IN STD_LOGIC; input1: IN STD_LOGIC; carry_input: IN STD_LOGIC; sum: OUT STD_LOGIC; carry_output: OUT STD_LOGIC ); END COMPONENT;

n

Functions

n

Procedures

Only one body per package n n

END adder;

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Note this is different than an entity Don’t always need package body statement if there are no functions, procedures, or deferred constants Page 14 9/9/2002

Package Body Example -- interface and architecture definitions for the 1- bit full -adder component follows PACKAGE BODY adder IS ENTITY fulladd IS PORT ( input0: IN STD_LOGIC; input1: IN STD_LOGIC; carry_input: IN STD_LOGIC; sum: O U T STD_LOGIC; carry_output: OUT STD_LOGIC ); END fulladd; ARCHITECTURE fulladd_arch O F fulladd I S SIGNAL tmp: std_logic_vector(1 TO 4); BEGIN sum <= input0 xor input1 x o r carry_input; carry_output <= (input0 and input1) or (input0 and carry_input) or (input1 a n d carry_input); END fulladd_arch; END PACKAGE BODY adder; Page 15 9/9/2002

 Copyright Richard J. Povinelli

rev 1.2, 9/9/2002

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