Vhdl Lab

VHDL PROGRAM FOR FULL ADDER IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY A full adder is a logical circuit that performs an addition operation on three binary digits. The full adders produce a sum and carry value, which are both binary digits.

VHDL code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadder is port( a,b,cin : in bit; s,cout : out bit); end fadder; architecture Behavioral of fadder is

begin s <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); end Behavioral;

UCF file NET NET NET NET NET

"a" LOC="P21" | IOSTANDARD=LVTTL; "b" LOC="P27" | IOSTANDARD=LVTTL; "c" LOC="P29" | IOSTANDARD=LVTTL; "cout" LOC="P26" | IOSTANDARD=LVTTL | SLEW=SLOW; "s" LOC="P20" | IOSTANDARD=LVTTL | SLEW=SLOW;

TRUTH TABLE Cin 0 0 0 0 1 1 1 1

Input B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Output S Cout 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

VHDL PROGRAM FOR ENCODER IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY: An encoder is a device used to change a signal (such as a bit stream) or data into a code. A single bit 4 to 2-encoder takes in 4 bits and outputs 2 bits.

VHDL Code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity encoder is port(a,b,c,d : in bit; x,y : out bit); end encoder; architecture Behavioral of encoder is begin

x <= c or d; y <= d or b;

end Behavioral;

UCF File: NET NET NET NET

"a" "b" "c" "d"

NET NET NET NET NET NET NET NET

"d1" "d2" "d3" "d4" "d5" "d6" "d7" "d8"

LOC="P29" LOC="P37" LOC="P35" LOC="P40" LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = =

| | | |

IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL; IOSTANDARD=LVTTL;

"p20" "p26" "p28" "p34" "p36" "p39" "p42" "p44"

| | | | | | | |

IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD

TRUTH TABLE:

INPUTS I3 I2 I1 0 0 0 0 0 1 0 1 0 1 0 0

I0 1 0 0 0

OUTPUT O1 O0 0 0 0 1 1 0 1 1

= = = = = = = =

LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL

| | | | | | | |

SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW

= = = = = = = =

SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW

; ; ; ; ; ; ; ;

VHDL PROGRAM FOR DECODER IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY: A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. In digital electronics this would mean that a decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. It has n inputs and 2n outputs.

VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder is port(s1,s2,s3:in bit;d1,d2,d3,d4,d5,d6,d7,d8:out bit); end decoder; architecture Behavioral of decoder is begin d1 <= s1 and s2 and s3; d2 <= s1 and s2 and (not s3); d3 <= s1 and (not s2) and s3; d4 <= s1 and (not s2) and (not s3); d5 <= (not s1) and s2 and s3; d6 <= (not s1) and s2 and (not s3); d7 <= (not s1) and (not s2) and s3; d8 <= (not s1) and (not s2) and (not s3); end Behavioral;

UCF File: NET "s1" NET "s2" NET "s3"

LOC = "p21" | IOSTANDARD = LVTTL ; LOC = "p27" | IOSTANDARD = LVTTL ; LOC = "p29" | IOSTANDARD = LVTTL ;

NET NET NET NET NET NET NET NET

LOC LOC LOC LOC LOC LOC LOC LOC

"d1" "d2" "d3" "d4" "d5" "d6" "d7" "d8"

= = = = = = = =

"p20" "p26" "p28" "p34" "p36" "p39" "p42" "p44"

| | | | | | | |

IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD

= = = = = = = =

LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL

| | | | | | | |

SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW

= = = = = = = =

SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW

; ; ; ; ; ; ; ;

TRUTH TABLE: Decimal Digit 0 1 2

0 1 0

D0 1 0 0

D1 0 1 0

D2 0 0 1

Outputs D3 D4 D5 0 0 0 0 0 0 0 0 0

0 0 0

0 0 1

D6 0 0 0

D7 0 0 0

3

0

1

1

0

0

0

1

0

0

0

0

4 5

1 1

0 0

0 1

0 0

0 0

0 0

0 0

1 0

0 1

0 0

0 0

6 7

1 1

1 1

0 1

0 0

0 0

0 0

0 0

0 0

0 0

1 0

0 1

S2 S1

S0

VHDL PROGRAM FOR MULTIPLEXER IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY: A multiplexer or mux is a device that performs multiplexing; it selects one of many analog or digital input signals and outputs that into a single line. In digital circuit design, the selector wires are of digital value. The number of selector pins is equal to where n is the number of inputs. If A, B, C, D are input to a 4 input multiplexer and S0 and S1 are select lines then the output is

VHDL code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is port(I:in bit_vector(3 downto 0);C0,C1:in bit;f:out bit); end mux; architecture Behavioral of mux is begin f<=((NOT C0)AND(NOT C1)AND I(0))OR(C0 AND(NOT C1)AND I(1))OR((NOT C0)AND C1 AND I(2))OR(C0 AND C1 AND I(3)) after 10 ns; end Behavioral;

UCF file NET NET NET NET NET NET NET

"I(0)" LOC="P29" | IOSTANDARD=LVTTL; "I(1)" LOC="P37" | IOSTANDARD=LVTTL; "I(2)" LOC="P35" | IOSTANDARD=LVTTL; "I(3)" LOC="P40" | IOSTANDARD=LVTTL; "C0" LOC="P21" | IOSTANDARD=LVTTL; "C1" LOC="P27" | IOSTANDARD=LVTTL; "f" LOC="P44" | IOSTANDARD=LVTTL | SLEW=SLOW;

TRUTH TABLE: C1 0 0 1 1

C0 0 1 0 1

F I0 I1 I2 I3

VHDL PROGRAM FOR DEMULTIPLEXER IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY: A demultiplexer (DMUX) is a device which essentially performs the opposite operation to the MUX. That is, it functions as an electronic switch to route an incoming data signal to one of several outputs.

VHDL Code:

entity demultiplexer is Port ( input : in std_logic_vector(0 downto 0); s0 : in std_logic_vector(0 downto 0); s1 : in std_logic_vector(0 downto 0); s2 : in std_logic_vector(0 downto 0); o0 : out std_logic_vector(0 downto 0); o1 : out std_logic_vector(0 downto 0); o2 : out std_logic_vector(0 downto 0); o3 : out std_logic_vector(0 downto 0); o4 : out std_logic_vector(0 downto 0); o5 : out std_logic_vector(0 downto 0); o6 : out std_logic_vector(0 downto 0); o7 : out std_logic_vector(0 downto 0)); end demultiplexer; architecture Behavioral of demultiplexer is begin o0 o1 o2 o3 o4 o5 o6 o7 end Behavioral;

<= (not s0 and not s1 and not s2 and input); <= ( s0 and not s1 and not s2 and input); <= ( not s0 and s1 and not s2 and input); <= ( s0 and s1 and not s2 and input); <= (not s0 and not s1 and s2 and input); <= ( s0 and not s1 and s2 and input); <= (not s0 and s1 and s2 and input); <= ( s0 and s1 and s2 and input);

UCF File : NET "s0" NET "s1" NET "s2"

LOC = "p21" | IOSTANDARD = LVTTL ; LOC = "p27" | IOSTANDARD = LVTTL ; LOC = "p29" | IOSTANDARD = LVTTL ;

NET "input" NET NET NET NET NET NET NET NET

"o0" "o1" "o2" "o3" "o4" "o5" "o6" "o7"

LOC LOC LOC LOC LOC LOC LOC LOC

LOC = "p35 " | IOSTANDARD = LVTTL ; = = = = = = = =

"p20" "p26" "p28" "p34" "p36" "p39" "p42" "p44"

| | | | | | | |

IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD

= = = = = = = =

LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL

| | | | | | | |

SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW

= = = = = = = =

SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW

; ; ; ; ; ; ; ;

TRUTH TABLE:

A2 0 0 0 0 1 1 1 1

A1 0 0 1 1 0 0 1 1

A0 0 1 0 1 0 1 0 1

OUT D0 D1 D2 D3 D4 D5 D6 D7

VHDL PROGRAM FOR D FLIP-FLOP IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY: A flip-flop is a kind of bistable multivibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the reset through an inverter. The result may be clocked.

VHDL code : use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is port(D,CLK:in bit; Q:out bit; QN:out bit:= '1'); end dff;

architecture Behavioral of dff is begin process(CLK) begin if CLK= '1' then Q <= D after 10 ns; QN <= not D after 10 ns; end if; end process;

end Behavioral;

UCF file: NET NET NET NET

"D" LOC="P21" | IOSTANDARD=LVTTL; "CLK" LOC="P27" | IOSTANDARD=LVTTL; "Q" LOC="P20" | IOSTANDARD=LVTTL | SLEW=SLOW; "QN" LOC="P26" | IOSTANDARD=LVTTL | SLEW=SLOW;

TRUTH TABLE: Clock D Q Qprev Rising edge 0 0 X Rising edge 1 1 X Non-Rising X constant

VHDL PROGRAM FOR JK FLIP-FLOP IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY:

The J-K flip-flop is the most versatile of the basic flip-flops. It has the inputfollowing character of the clocked D flip-flop but has two inputs, traditionally labeled J and K. If J and K are different then the output Q takes the value of J at the next clock edge. If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together. This toggle application finds extensive use in binary counters.

VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkflipflop is

port (SN, RN, J,K, CLK:in bit; Q: inout bit; QN: out bit:='1'); end jkflipflop; architecture Behavioral of jkflipflop is begin process (SN, RN, CLK) begin if RN='0' then Q<='0' after 10 ns; elsif SN='0' then Q<='1' after 10 ns; elsif CLK='0' and CLK'event then Q<= (J and not Q) or (not K and Q) after 10 ns; end if; QN<= not Q; end process; end Behavioral;

UCF File NET NET NET NET NET NET NET

"J" LOC="P21" | IOSTANDARD=LVTTL; "K" LOC="P27" | IOSTANDARD=LVTTL; "SN" LOC="P29" | IOSTANDARD=LVTTL; "RN" LOC="P35" | IOSTANDARD=LVTTL; "CLK" LOC="P37" | IOSTANDARD=LVTTL; "Q" LOC="P20" | IOSTANDARD=LVTTL | SLEW=SLOW; "QN" LOC="P26" | IOSTANDARD=LVTTL | SLEW=SLOW;

TRUTH TABLE : J K Qnext Comment 0 0 hold state 0 1 reset 1 0 set 1 1 toggle

VHDL PROGRAM FOR T FLIP-FLOP IN XILINX INTEGRATED SOFTWARE ENVIRONMENT THEORY: The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input. It is useful for constructing binary counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both of its inputs high.

VHDL code: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tflip is port (T, CLK:in bit; Q: inout bit; QN: out bit); end tflip; architecture Behavioral of tflip is

begin process (CLK) begin if CLK='0' and CLK'event then Q<= (T and not Q) or (not T and Q) after 10 ns; end if; QN<= not Q; end process; end Behavioral;

UCF File NET NET NET NET

"T" LOC="P21" | IOSTANDARD=LVTTL; "CLK" LOC="P35" | IOSTANDARD=LVTTL; "Q" LOC="P20" | IOSTANDARD=LVTTL | SLEW=SLOW; "QN" LOC="P26" | IOSTANDARD=LVTTL | SLEW=SLOW;

TRUTH TABLE: T 0 0 1 1

Q 0 1 0 1

Qnext 0 1 1 0

Comment Hold state Hold state Toggle Toggle