Various Type Of Register

An Assignment On Registers of Microprocessors

Microprocessor & Microcomputer Lab Course Code: CSE – 312

© Moshiur Rahman Khan CSE 1st Batch, PSTU.

Submitted To Md. Ileas Pramanik Lecturer, CSE Faculty, PSTU.

Submitted By Md.Moshiur Rahman Khan Reg No.: 00600 Roll No.: 21 L-IV, S- I [email protected] CSE, PSTU.

Submission Date: 24-10-2008

Signature of the Course Teacher:

Patuakhali Science & Technology University, Patuakhali.

Acknowledgments

I am very grateful to my honorable teacher Md. Ileas Pramanik, Lecturer, Faculty of CSE, PSTU, who assigns me this assignment & allowed me to complete this assignment. I would also like to thank to my teacher for his kind help to complete the assignment & making this possible. I am grateful to Ileas Sir for the fellowship, and many discussions and comments that led to this assignment. Finally, this work describes about technical review of Registers in Microprocessor.

Contents Introduction

01

Categories of Registers

01

System Register & Status Register

02

Pointer Register & Index Register

03

Hardware register

03

Instruction Register & Control Register

04

Memory Management Register & Address Register

05

Memory Data Register and Buffer Register

06

Segment Register

06

Shift Register & Stack Register

07

Test Register & Task Register

07

Accumulator Register

08

EFLAGS Register

09

Base Address Register & Interrupt Command Register

10

Memory Type Range Register & IA32_MCG_CAP MSR

11

IA32_MCG_STATUS MSR & IA32_MCi_CTL_MSRs

12

IA32_MCi_STATUS_MSRs & Machine Check Type Register

13

Conclusion

14

References

15

Introduction In computer architecture, a processor register is a small amount of storage available on the CPU whose contents can be accessed more quickly than storage available elsewhere. Most, but not all, modern computer architectures operate on the principle of moving data from main memory into registers, operating on them, then moving the result back into main memory—a so-called load-store architecture. A common property of computer programs is locality of reference: the same values are often accessed repeatedly; and holding these frequently used values in registers improves program execution performance. Allocating frequently used variables to registers can be critical to a program's performance. This action, namely register allocation is performed by a compiler in the code generation phase.

Categories of Registers Registers are normally measured by the number of bits they can hold, for example, an "8-bit register" or a "32-bit register". Registers are now usually implemented as a register file, but they have also been implemented using individual flip-flops, high speed core memory, thin film memory, and other ways in various machines. A processor often contains several kinds of registers, that can be classified according to their content or instructions that operate on them:  

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     

User-accessible Registers - The most common division of user-accessible registers is into data registers and address registers. Data registers are used to hold numeric values such as integer and floating-point values. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations. Address registers hold addresses and are used by instructions that indirectly access memory. o Some processors contain registers that may only be used to hold an address or only to hold numeric values (in some cases used as an index register whose value is added as an offset from some address); others allow registers hold either kind of quantity. A wide variety of possible addressing modes, used to specify the effective address of an operand, exist. o A stack pointer, sometimes called a stack register, is the name given to a register that can be used by some instructions to maintain a stack (data structure). Conditional registers hold truth values often used to determine whether some instruction should or should not be executed. General purpose registers (GPRs) can store both data and addresses, i.e., they are combined Data/Address registers. Floating point registers (FPRs) store floating point numbers in many architectures. Constant registers hold read-only values such as zero, one, or pi. Vector registers hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data). Special purpose registers hold program state; they usually include the program counter (aka instruction pointer), stack pointer, and status register (aka processor status word). o Instruction registers store the instruction currently being executed.

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 

In some architectures, model-specific registers (also called machine-specific registers) store data and settings related to the processor itself. Because their meanings are attached to the design of a specific processor, they cannot be expected to remain standard between processor generations. Control and status registers - It has three types. Program counter, instruction registers, Program status word (PSW). Registers related to fetching information from RAM, a collection of storage registers located on separate chips from the CPU (unlike most of the above, these are generally not architectural registers): o Memory buffer register o Memory data register o Memory address register o Memory Type Range Registers

Hardware registers are similar, but occur outside CPUs.

System Registers To assist in initializing the processor and controlling system operations, the system architecture provides system flags in the EFLAGS register and several system registers: • The system flags and IOPL field in the EFLAGS register control task and mode switching, interrupt handling, instruction tracing, and access rights. • The control registers (CR0, CR2, CR3, and CR4) contain a variety of flags and data fields for controlling system-level operations. Other flags in these registers are used to indicate support for specific processor capabilities within the operating system or executive. • The debug registers allow the setting of breakpoints for use in debugging programs and systems software. • The GDTR, LDTR, and IDTR registers contain the linear addresses and sizes (limits) of their respective tables. • The task register contains the linear address and size of the TSS for the current task. • Model-specific registers.

Status register A status register (also: flag register or condition code register (CCR)) is a collection of flag bits for a processor. A popular example of a status register is the FLAGS register of x86 architecture based microprocessors.

Common status register flags  

     

Z — Zero flag. Indicates that the result of a mathematical or logical operation was zero. C — Carry flag. Indicates that the result of an operation produced an answer greater than the number of available bits. (This flag may also be set before a mathematical operation as an extra operand to certain instructions, e.g. "add with carry".) X — Extend bit. N (or S) — Negative or Sign flag. Indicates that the result of a mathematical operation is negative. V (or O or W) — Overflow flag. Indicates that the result of an operation has overflowed according to the CPU's word representation, similar to the carry flag but for signed operations. I (or E) — Interrupt enable flag. Interrupts can be enabled or disabled by respectively setting or clearing this flag. P — Parity flag. Indicate that the number of bits of the result is odd or even. D (or T) — Debug or Trap flag. Specifies that a special tracing interrupt is generated immediately after each single instruction is executed. This is used to implement program code debuggers.

Pointer Register A bit information is first calculated in ALU 7 from the address among the control space address map that has been designated by the address of the above-described STC (store-control-space) instruction. The specific register in the general-purpose register group 8 is no longer required to be designated by the instruction field "X3" of the microinstruction register 4, but this specific register can be accessed by merely, commonly designating the general-purpose register group 8 by way of the selection field "X2" of the microinstruction register 4, based upon the bit information temporarily stored in the pointer register 10.

Index Register An index register in a computer's CPU is a processor register used for modifying operand addresses during the run of a program, typically for doing vector/array operations. Index registers were first used in the British Manchester Mark I computer, in 1949.

Index registers are used for a special kind of indirect addressing where an immediate constant is added to the contents of a register to form the address to the actual operand or data; architectures which allow more than one register to be used this way naturally have an opcode field for specifying which register to use.

Hardware Register In digital electronics, especially computing, a hardware register stores bits of information, in a way that all the bits can be written to or read out simultaneously. The hardware registers inside a central processing unit (CPU) are called processor registers. Signals from a state machine to the register control when registers transmit to or accept information from other registers.

Instruction register In computing, an instruction register is the part of a CPU's control unit that stores the instruction currently being executed. In simple processors each instruction to be executed is loaded into the instruction register which holds it while it is decoded, prepared and ultimately executed, which can take several steps. Decoding the opcode in the instruction register includes determining the instruction, determining where its operands are in memory, retrieving the operands from memory, allocating processor resources to execute the command etc. It holds the instruction and tell what instruction to be executed. Its main work is to hold the instruction. Without this, it does not perform any task.

Control Registers

Figure 1. Control Registers Control registers (CR0, CR1, CR2, CR3, and CR4; in Figure 1) determine operating mode of the processor and the characteristics of the currently executing task.These registers are 32 bits in all 32-bit modes and compatibility mode. Control Register 4 (CR4) Extensions Control register 4 contains bits that enable or specify many of the extensions to the 486 architecture. The majority of the bits in CR4 are reserved. The default state for all bits in CR4 is all zeros. Figure 2 shows the format of CR4.

Figure 2. Control Register 4 (CR4)

Memory-Management Registers The processor provides four memory-management registers (GDTR, LDTR, IDTR, and TR) that specify the locations of the data structures which control segmented memory management (in Figure 3). Special instructions are provided for loading and storing these registers.

Figure 3. Memory Management Registers

Memory Address Register The memory address register holds the address of the next memory location where the next instruction is to be executed. While the first instruction is being executed, the address of the next memory location is held by it. The computer’s CPU uses the address bus to communicate which memory address it wants to access, and the memory controller reads the address and then puts the data stored in that memory address back onto the address bus for the CPU to use. The Memory Address Register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register.

Memory Buffer Register The Memory Buffer Register (MBR) is the register in the central processor that stores the data being transferred to and from the immediate access store. It acts as a buffer allowing the central processor and memory units to act independently without being affected by minor differences in operation. A data item will be copied to the MBR ready for use at the next clock pulse when it can be either used by the central processor or stored in main memory. This register holds the contents of the memory which are to be transferred from memory to other components or vice versa. A word to be stored must be transferred to the MBR from where it goes to the specific memory location and the arithmetic data to be processed in the ALU first goes to MBR and then to accumulated register and then it is processed in the ALU.

Memory Data Register The memory data register (MDR) is the register of a computer's control unit that contains the data to be stored in the computer storage (e.g. RAM), or the data after a fetch from the computer storage. It acts like a buffer and holds anything that is copied from the memory ready for the processor to use it. The memory data register is half of a minimal interface between a microprogram and computer storage, the other half is a memory address register.

Segment Registers To reduce address translation time and coding complexity, the processor provides registers for holding up to 6 segment selectors (in Figure 4). Each of these segment registers support a specific kind of memory reference (code, stack, or data). The processor also provides three additional data-segment registers (ES, FS, and GS), which can be used to make additional data segments available to the currently executing program (or task).

Figure 4. Segment Registers Every segment register has a “visible” part and a “hidden” part. (The hidden part is sometimes referred to as a “descriptor cache” or a “shadow register.”) When a segment selector is loaded into the visible part of a segment register, the processor also loads the hidden part of the segment register with the base address, segment limit, and access control information from the segment descriptor pointed to by the segment selector. The information cached in the segment register (visible and hidden) allows the

processor to translate addresses without taking extra bus cycles to read the base address and limit from the segment descriptor.

Shift Register In digital circuits a shift register is a group of flip flops set up in a linear fashion which have their inputs and outputs connected together in such a way that the data is shifted down the line when the circuit is activated. Shift registers can have a co parallel inputs and outputs, including serial-in, parallel-out (SIPO) and parallel-in, serial-out (PISO) types. There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow you to vary the direction of the shift register. The serial input and outputs of a register can also be connected together to create a circular shift register. One could also create multi-dimensional shift registers, which can perform more complex computation.

Stack Register A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register such as SP on an Intel x86 machine. On a general register machine, it may be a register which is reserved by convention, such as on the PDP-11 or RISC machines. Some designs such as the Data General Eclipse had no dedicated register, but used a reserved hardware memory address for this function. A stack machine has 2 or more stack registers — one of them keeps track of a call stack, the other(s) keep track of other stack(s).

Test register Test register was a register used by the processor, usually to do a self-test. Most of these registers were undocumented, and used by specialized software. In the x86 series, these registers were marked TR4 to TR7. Usually, regular programs don't require these registers to work. In the newer CPU sets, the test registers are removed. Two test registers, TR6 and TR7, were provided for the purpose of testing. TR6 was the test command register, and TR7 was the test data register. The MOV instructions are defined in both real-address mode and protected mode. The test registers are privileged resources. In protected mode, the MOV instructions that access them can only be executed at privilege level 0. An attempt to read or write the test registers when executing at any other privilege level causes a general protection exception.

Task Register The task register holds the 16-bit segment selector and the entire segment descriptor (32-bit base address, 16-bit segment limit, and descriptor attributes) for the TSS of the current task (in Figure 5). This

information is copied from the TSS descriptor in the GDT for the current task. Figure 5 shows the path the processor uses to access the TSS (using the information in the task register).

Figure 5. Task Register

Accumulator Register Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate data include a reserved bit-switch (in the form of a two bit field) whose status (A0) causes the instruction to be executed once to operate on a single word of data, or whose status (A0S) causes the instruction to be repeatedly executed as the instruction operates on a chain or list of sequential data, for example a data chain including N 16-bit words of data, wherein N is an integer. Every instruction word that manipulates data has a reserved bit switch that will cause the instruction to be executed either once operating on single word data or as a repeated execution of the same instruction operating on a chain or list of sequential data (n words).

EFLAGS Register

Figure 6. EFLAGS Register

System FLAGS and fields in the EFLAGS Register The system flags and IOPL field of the EFLAGS register control I/O, maskable hard-ware interrupts, debugging, task switching, and the virtual-8086 mode (in Figure 7). Only privileged code (typically operating system or executive code) should be allowed to modify these bits.

Figure 7. System Flags in the EFLAGS Register

Base Address Register The system uses deviations to generate corrective instructions to take the computer from a storage position where it is,to a position where it isn't; arriving at the position where it wasn't, it now is. Consequently, the position where it was, is now the position where it wasn't, and it follows that the position where it was is the position where it isn't. In the event the position where it is now, is not the position where it wasn't, the system has acquired a variation, the variation being the difference between where the computer is and where it wasn't. However, the computer is sure where it isn't, and it knows where it wasn't, and by differentiating this from the algebraic difference between where it shouldn't be and where it was, it is able to obtain the difference between its deviation and its variation which is called ERROR!

Interrupt Command Register (ICR)

Figure 8. Interrupt Command Register (ICR) The interrupt command register (ICR) is a 64-bit local APIC register (in Figure 8) that allows software running on the processor to specify and send interprocessor interrupts (IPIs) to other processors in the system.To send an IPI, software must set up the ICR to indicate the type of IPI message to be sent and

the destination processor or processors. (All fields of the ICR are read-write by software with the exception of the delivery status field, which is read-only.) The act of writing to the low doubleword of the ICR causes the IPI to be sent.

Memory Type Range Registers (MTRRS) Memory type range registers (MTRRs) were introduced into the IA-32 architecture with the Pentium Pro processor. They allow the type of caching (or no caching) to be specified in system memory for selected physical address ranges. They allow memory accesses to be optimized for various types of memory such as RAM, ROM, frame buffer memory, and memory-mapped I/O devices. Figure 9 shows the mapping of physical memory with MTRRs.

Figure 9. Mapping Physical Memory With MTRRs

IA32_MCG_CAP MSR The IA32_MCG_CAP MSR is a read-only register that provides information about the machine-check architecture of the processor. Figure 10 shows the structure of the register in Pentium 4, Intel Xeon, and P6 family processors.

Figure 10. IA32_MCG_CAP Register

IA32_MCG_STATUS MSR The IA32_MCG_STATUS MSR describes the current state of the processor after a machine-check exception has occurred (see Figure 11).

Figure 11. IA32_MCG_STATUS Register

IA32_MCi_CTL MSRs The IA32_MCi_CTL MSR controls error reporting for errors produced by a particular hardware unit (or group of hardware units). Each of the 64 flags (EEj) represents a potential error. Setting an EEj flag enables reporting of the associated error and clearing it disables reporting of the error. The processor does not write changes to bits that are not implemented. Figure 12 shows the bit fields of IA32_MCi_CTL.

Figure 12. IA32_MCi_CTL Register

IA32_MCi_STATUS MSRS Each IA32_MCi_STATUS MSR contains information related to a machine-check error if its VAL (valid) flag is set (see Figure 13). Software is respon sible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection exception.

Figure 13. IA32_MCi_STATUS Register

Machine-Check Type Register (MCTR) The processor latches the cycle definition and other information about the current bus cycle in its 64-bit Machine-Check Type Register (MCAR) at the same times that the Machine-Check Address Register (MCAR) latches the cycle address: when a bus-cycle error occurs. These errors are indicated either by (a) system logic asserting BUSCHK, or (b) the processor asserting PCHK while system logic asserts PEN. The MCTR can be read with the RDMSR instruction when the ECX register contains the value 01h. Figure 15 shows the formats of the MCTR register. The contents of the register can be read with the RDMSR instruction. The processor clears the CHK bit (bit 0) in MCTR when the register is read with the RDMSR instruction.

Figure 15. Machine-Check Type Register (MCTR)

Conclusion Processor registers are at the top of the memory hierarchy, and provide the fastest way for a CPU to access data. The term is often used to refer only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. More properly, these are called the "architectural registers". For instance, the x86 instruction set defines a set of eight 32-bit registers, but a CPU that implements the x86 instruction set will often contain many more registers than just these.

References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20.

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