Uart

Implementation of UART library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart is Port ( sci_sel,r_w,clk,rxd : in std_logic; add2 : in std_logic_vector(1 downto 0); sci_irq,txd : out std_logic); end uart; architecture uart1 of uart is component uart_receiver port(rxd,bclkx8,sysclk,rst_b,rdrf:in std_logic; rdr:out std_logic_vector(7 downto 0); setrdrf,setoe,setfe:out std_logic ); end component; component uart_transmitter port(bclk,sysclk,rst_b,tdre,loadtdr:in std_logic; dbus:in std_logic_vector(7 downto 0); settdre,txd : out std_logic); end component; component clk_divider port(sysclk,rst_b:in std_logic; sel:in std_logic_vector(2 downto 0); bclkx8,bclk:out std_logic); end component; signal dbus:std_logic_vector(7 downto 0); signal rdr:std_logic_vector(7 downto 0); signal scsr:std_logic_vector(7 downto 0); signal sccr:std_logic_vector(7 downto 0); signal tdre,rdrf,oe,fe,tie,rie:std_logic; signal baudsel:std_logic_vector(2 downto 0); signal settdre,setrdrf,setoe,setfe,loadtdr,loadsccr:std_logic; signal clrrdrf,bclk,bclkx8,sci_read,sci_write:std_logic;

begin rcvr:uart_receiver port map(rxd,bclkx8,clk,rst_b,rdrf,rdr,setrdrf,setoe,setfe); xmit:uart_transmitter port map(bclk,clk,rst_b,tdre,loadtdr,dbus,settdre,txd); clkdiv:clk_divider port map (clk,rst_b,baudsel,bclkx8,bclk); ----process to update control & status register process(clk,rst_b) begin if(rst_b = '0') then tdre<='1'; rdrf<='0'; oe<='0'; fe<='0'; tie<='0'; rie<='0'; elsif(rising_edge(clk)) then tdre<=(settdre and not tdre) or (not loadtdr and tdre); rdrf<=(setrdrf and not rdrf) or (not clrrdrf and rdrf); oe<=(setoe and not oe) or (not clrrdrf and oe); fe<=(setfe and not fe) or (not clrrdrf and fe); if(loadsccr = '1') then tie<=dbus(7); rie<=dbus(6); baudsel<=dbus(2 downto 0); end if; end process; ---- logic for IRQ generation sci_irq <='1' when (rie ='1' and (rdrf = '1' or oe='1')) or (tie='1' and tdre='1')) else '0'; ----bus interface scsr <= tdre & rdrf & "0000" & oe & fe; sccr <= tie & rie & "000" & baudsel; sci_read <= '1' when (sci_sel ='1' and r_w ='0') else '0';

sci_write<= '1' when (sci_sel ='1' and r_w ='1') else '0'; clrrdrf <= '1' when (sci_read ='1' and addr ="00") else '0'; loadtdr<='1' when (sci_write ='1' and addr ="00") else '0'; loadsccr<='1' when (sci_read ='0' and addr ="10") else '0'; dbus<="zzzzzzzz" when (sci_read ='0') else rdr when (addr ="00"); else scsr when (addr="01") else sccr; end uart1; BAUD RATE GENERATOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity clk_divider is Port ( sysclk,rst_b : in std_logic; sel : in std_logic_vector(2 downto 0); bclkx8 : buffer std_logic; bclk : out std_logic); end clk_divider; architecture baud of clk_divider is signal ctr1:std_logic_vector(3 downto 0):="0000"; signal ctr2:std_logic_vector(7 downto 0):="00000000"; signal ctr3:std_logic_vector(2 downto 0):="000"; signal clkdiv:std_logic; begin process(sysclk) begin if(sysclk'event and sysclk='1') then if(ctr1="1100" ) then ctr1<="0000"; else ctr1<=ctr1+1; end if; end if; end process;

clkdiv<=ctr1(3); process(clkdiv) begin if(rising_edge(clkdiv)) then ctr2<=ctr2+1; end if; end process; process(bclkx8) begin if(rising_edge(bclkx8)) then ctr3<=ctr3+1; end if; end process; bclk<=ctr3(2); end baud; =============================================================== ========== * Final Report * =============================================================== ========== Final Results RTL Top Level Output File Name : clk_divider.ngr Top Level Output File Name : clk_divider Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs Macro Statistics : # Registers # 3-bit register

:7 :1 :1

Cell Usage : # BELS :1 # GND :1 # IO Buffers :2 # OBUF :2 =============================================================== ==========

Device utilization summary: --------------------------Selected Device : v300pq240-4 Number of bonded IOBs:

2 out of

170

1%

=============================================================== ========== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns) =============================================================== ========== CPU : 2.31 / 3.23 s | Elapsed : 2.00 / 3.00 s --> Total memory usage is 61088 kilobytes

RECEIVER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart_receiver is Port ( rxd,bclkx8,sysclk,rst_b,rdrf : in std_logic; rdr : out std_logic_vector(7 downto 0); setrdrf,setoe,setfe : out std_logic); end uart_receiver; architecture rcvr of uart_receiver is type statetype is(idle,start_detected,recv_data); signal state,nextstate:statetype; signal rsr:std_logic_vector(7 downto 0); signal ct1:integer range 0 to 7; signal ct2:integer range 0 to 8; signal inc1,inc2,clr1,clr2,shftrsr,loadrdr,bclkx8_rising,bclkx8_delayed:std_logic; begin

bclkx8_rising <= bclkx8 and (not bclkx8_delayed); rcvr_control: process(state,rxd,rdrf,ct1,ct2,bclkx8_rising) begin inc1<='0';inc2<='0';clr1<='0';clr2<='0'; shftrsr<='0';loadrdr<='0' ;setrdrf<='0' ;setoe<='0';setfe<='0'; case state is when idle=> if(rxd='0') then nextstate<=start_detected; else nextstate<= idle; end if; when start_detected => if(bclkx8_rising='0') then nextstate<=start_detected; elsif(rxd='1') then clr1<='1'; nextstate<=idle; elsif(ct1=3) then clr1<='1'; nextstate<= recv_data; else inc1<='1'; nextstate<=start_detected; end if; when recv_data=> if(bclkx8_rising='0') then nextstate<=recv_data; elsif(ct2/=8) then shftrsr <='1';inc2<='1';clr1<='1'; nextstate<=recv_data; else nextstate<=idle; setrdrf<='1'; clr1<='1'; clr2<='1'; if(rdrf='1') then setoe<='1'; elsif(rxd='0') then setfe<='1'; else loadrdr<='1'; end if; end if; end case; end process; rcvr_update:process(sysclk,rst_b) begin if(rst_b='0') then state<=idle; bclkx8_delayed<='0'; ct1<=0;ct2<=0; elsif(sysclk'event and sysclk='1') then state<=nextstate;

if (clr1='1')then ct1<=0 ; elsif(inc1='1') then ct1<=ct1+1; end if; if (clr2='1')then ct2<=0 ; elsif(inc2='1') then ct2<=ct2+1; end if; if(shftrsr='1') then rsr<=rxd & rsr(7 downto 1); end if; if(loadrdr='1')then rdr<=rsr; end if; bclkx8_delayed<=bclkx8; end if; end process; end rcvr; =============================================================== ========== * Final Report * =============================================================== ========== Final Results RTL Top Level Output File Name : uart_receiver.ngr Top Level Output File Name : uart_receiver Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs

: 16

Macro Statistics : # Registers # 1-bit register # 3-bit register # 8-bit register # Counters # 4-bit up counter # Multiplexers # 2-to-1 multiplexer

: 11 :9 :1 :1 :1 :1 :1 :1

Cell Usage : # BELS # GND # LUT1 # LUT2

: 38 :1 :1 :2

# LUT2_D :1 # LUT2_L :1 # LUT3 :4 # LUT3_L :3 # LUT4 :8 # LUT4_D :2 # LUT4_L :6 # MUXCY :4 # VCC :1 # XORCY :4 # FlipFlops/Latches : 27 # FDC :3 # FDCE :3 # FDCPE :4 # FDE : 16 # FDP :1 # Clock Buffers :1 # BUFGP :1 # IO Buffers : 15 # IBUF :4 # OBUF : 11 =============================================================== ========== Device utilization summary: --------------------------Selected Device : v300pq240-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of bonded IOBs: Number of GCLKs:

21 out of 3072 0% 27 out of 6144 0% 28 out of 6144 0% 15 out of 170 8% 1 out of 4 25%

=============================================================== ========== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information:

----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ sysclk | BUFGP | 27 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -4 Minimum period: 9.914ns (Maximum Frequency: 100.867MHz) Minimum input arrival time before clock: 9.608ns Maximum output required time after clock: 15.783ns Maximum combinational path delay: 15.477ns Timing Detail: -------------All values displayed in nanoseconds (ns) ------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'sysclk' Delay: 9.914ns (Levels of Logic = 3) Source: bclkx8_delayed (FF) Destination: rdr_7 (FF) Source Clock: sysclk rising Destination Clock: sysclk rising Data Path: bclkx8_delayed to rdr_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDC:C->Q 8 1.372 2.255 bclkx8_delayed (bclkx8_delayed) LUT4:I0->O 1 0.738 1.265 Ker1079_SW117_SW0 (N1456) LUT4_D:I3->O 4 0.738 1.760 Ker1079_SW117 (setrdrf_OBUF) LUT4_L:I3->LO 8 0.738 0.100 _n00361 (_n0036) FDE:CE 0.948 rdr_0 ---------------------------------------Total 9.914ns (4.534ns logic, 5.380ns route) (45.7% logic, 54.3% route) ------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk' Offset: 9.608ns (Levels of Logic = 4) Source: bclkx8 (PAD) Destination: rdr_7 (FF)

Destination Clock: sysclk rising Data Path: bclkx8 to rdr_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 9 0.989 2.332 bclkx8_IBUF (bclkx8_IBUF) LUT4:I3->O 1 0.738 1.265 Ker1079_SW117_SW0 (N1456) LUT4_D:I3->O 4 0.738 1.760 Ker1079_SW117 (setrdrf_OBUF) LUT4_L:I3->LO 8 0.738 0.100 _n00361 (_n0036) FDE:CE 0.948 rdr_0 ---------------------------------------Total 9.608ns (4.151ns logic, 5.457ns route) (43.2% logic, 56.8% route) ------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk' Offset: 15.783ns (Levels of Logic = 4) Source: bclkx8_delayed (FF) Destination: setfe (PAD) Source Clock: sysclk rising Data Path: bclkx8_delayed to setfe Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDC:C->Q 8 1.372 2.255 bclkx8_delayed (bclkx8_delayed) LUT4:I0->O 1 0.738 1.265 Ker1079_SW117_SW0 (N1456) LUT4_D:I3->O 4 0.738 1.760 Ker1079_SW117 (setrdrf_OBUF) LUT2:I1->O 1 0.738 1.265 setoe1 (setoe_OBUF) OBUF:I->O 5.652 setoe_OBUF (setoe) ---------------------------------------Total 15.783ns (9.238ns logic, 6.545ns route) (58.5% logic, 41.5% route) ------------------------------------------------------------------------Timing constraint: Default path analysis Delay: 15.477ns (Levels of Logic = 5) Source: bclkx8 (PAD) Destination: setfe (PAD) Data Path: bclkx8 to setfe Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 9 0.989 2.332 bclkx8_IBUF (bclkx8_IBUF)

LUT4:I3->O 1 0.738 1.265 Ker1079_SW117_SW0 (N1456) LUT4_D:I3->O 4 0.738 1.760 Ker1079_SW117 (setrdrf_OBUF) LUT2:I1->O 1 0.738 1.265 setoe1 (setoe_OBUF) OBUF:I->O 5.652 setoe_OBUF (setoe) ---------------------------------------Total 15.477ns (8.855ns logic, 6.622ns route) (57.2% logic, 42.8% route) =============================================================== ========== CPU : 1.97 / 2.91 s | Elapsed : 2.00 / 3.00 s --> Total memory usage is 62112 kilobytes

TRANSMITTER library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart_transmitter is Port ( bclk,sysclk,rst_b,tdre,loadtdr : in std_logic; dbus : in std_logic_vector(7 downto 0); settdre,txd : out std_logic); end uart_transmitter; architecture xmit of uart_transmitter is type statetype is(idle,synch,tdata); signal state,nextstate:statetype; signal tsr:std_logic_vector(8 downto 0); signal tdr:std_logic_vector(7 downto 0); signal bct:integer range 0 to 9; signal inc,clr,loadtsr,shfttsr,start,bclk_rising,bclk_delayed,tsrout:std_logic; begin txd <= tsr(0); settdre <= loadtsr; bclk_rising<=bclk and (not bclk_delayed); xmit_control : process(state,tdre,bct,bclk_rising) begin inc<='0'; clr<='0'; loadtsr<='0'; shfttsr<='0'; start<='0'; case state is when idle => if(tdre='0') then loadtsr <='1'; nextstate<=synch; else nextstate<=idle; end if;

when synch => if(bclk_rising ='1') then start <='1'; nextstate<=tdata; else nextstate<=synch; end if; when tdata => if(bclk_rising ='1') then nextstate<=tdata; elsif(bct/=9) then shfttsr<='1'; inc<='1'; nextstate<=tdata; else clr<='1'; nextstate<=idle; end if; end case; end process; xmit_update:process(sysclk,rst_b) begin if(rst_b = '0') then tsr<= "111111111"; state<=idle; bct<=0; bclk_delayed<='0'; elsif(sysclk'event and sysclk='1') then state <= nextstate; if (clr='1') then bct<=0; elsif (inc='1') then bct<=bct+1; end if; if (loadtdr='1') then tdr<=dbus; end if; if (loadtsr='1') then tsr<=tdr & '1'; end if; if (start='1') then tsrout<='0'; end if; if (shfttsr='1') then tsr<='1' & tsr(8 downto 1); end if; bclk_delayed<=bclk; end if; end process; end xmit;

=============================================================== ========== * Final Report * =============================================================== ========== Final Results RTL Top Level Output File Name : uart_transmitter.ngr Top Level Output File Name : uart_transmitter Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs Macro Statistics : # Registers # 1-bit register # 8-bit register # 9-bit register # Counters # 4-bit up counter # Multiplexers # 2-to-1 multiplexer Cell Usage : # BELS # GND # LUT1 # LUT2 # LUT3_D # LUT3_L # LUT4 # LUT4_D # LUT4_L # MUXCY # VCC # XORCY # FlipFlops/Latches # FDC # FDCPE # FDE # FDP # FDPE # Clock Buffers # BUFGP

: 15 :3 :1 :1 :1 :1 :1 :1 :1 : 33 :1 :1 :3 :1 :4 :4 :2 :8 :4 :1 :4 : 25 :3 :4 :8 :1 :9 :1 :1

# IO Buffers : 14 # IBUF : 12 # OBUF :2 =============================================================== ========== Device utilization summary: --------------------------Selected Device : v300pq240-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of bonded IOBs: Number of GCLKs:

18 out of 3072 0% 25 out of 6144 0% 23 out of 6144 0% 14 out of 170 8% 1 out of 4 25%

=============================================================== ========== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ sysclk | BUFGP | 25 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -4 Minimum period: 10.396ns (Maximum Frequency: 96.191MHz) Minimum input arrival time before clock: 8.437ns Maximum output required time after clock: 10.787ns Maximum combinational path delay: 10.404ns Timing Detail: --------------

All values displayed in nanoseconds (ns) ------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'sysclk' Delay: 10.396ns (Levels of Logic = 2) Source: bct_1 (FF) Destination: tsr_8 (FF) Source Clock: sysclk rising Destination Clock: sysclk rising Data Path: bct_1 to tsr_8 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDCPE:C->Q 3 1.372 1.628 bct_1 (bct_1) LUT4_D:I1->O 12 0.738 2.640 _n00201 (_n0020) LUT4:I0->O 9 0.738 2.332 _n00251 (_n0025) FDPE:CE 0.948 tsr_0 ---------------------------------------Total 10.396ns (3.796ns logic, 6.600ns route) (36.5% logic, 63.5% route) ------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk' Offset: 8.437ns (Levels of Logic = 4) Source: bclk (PAD) Destination: bct_3 (FF) Destination Clock: sysclk rising Data Path: bclk to bct_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 5 0.989 1.914 bclk_IBUF (bclk_IBUF) LUT3_D:I1->O 14 0.738 2.860 Ker8031 (N805) LUT3_L:I1->LO 0 0.738 0.000 bct_inst_lut3_31 (bct_inst_lut3_3) XORCY:LI->O 1 0.433 0.000 bct_inst_sum_3 (bct_inst_sum_3) FDCPE:D 0.765 bct_3 ---------------------------------------Total 8.437ns (3.663ns logic, 4.774ns route) (43.4% logic, 56.6% route) ------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk' Offset: 10.787ns (Levels of Logic = 2) Source: state_FFd3 (FF)

Destination: settdre (PAD) Source Clock: sysclk rising Data Path: state_FFd3 to settdre Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDP:C->Q 4 1.372 1.760 state_FFd3 (state_FFd3) LUT2:I0->O 1 0.738 1.265 loadtsr1 (settdre_OBUF) OBUF:I->O 5.652 settdre_OBUF (settdre) ---------------------------------------Total 10.787ns (7.762ns logic, 3.025ns route) (72.0% logic, 28.0% route) ------------------------------------------------------------------------Timing constraint: Default path analysis Delay: 10.404ns (Levels of Logic = 3) Source: tdre (PAD) Destination: settdre (PAD) Data Path: tdre to settdre Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 4 0.989 1.760 tdre_IBUF (tdre_IBUF) LUT2:I1->O 1 0.738 1.265 loadtsr1 (settdre_OBUF) OBUF:I->O 5.652 settdre_OBUF (settdre) ---------------------------------------Total 10.404ns (7.379ns logic, 3.025ns route) (70.9% logic, 29.1% route) =============================================================== ========== CPU : 1.75 / 2.66 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 61088 kilobytes