Types Of Random Access Memories

Types of Random Access Memories

Types of Random Access Memories

SDRAM

RAM • Memories provide storage for computers Summary • Memories are organized in words – Selected by addresses

• SRAMs store data in latches – Accessed by surrounding circuitry

• RAM waveforms indicate the control signals needed for access • Words in SRAMs are accessed with decoders – Only one word selected at a time

ROM • Read-only memory can normally only be read Overview • Internal organization similar to SRAM • ROMs are effective at implementing truth tables – Any logic function can be implemented using ROMs

• Multiple single-bit functions embedded in a single ROM • Also used in computer systems for initialization – ROM doesn’t lose storage value when power is removed

Read-Only Memory (ROM) • An array of semiconductor devices – diodes – transistors – field effect transistors

• 2N words by M bits • Data can be read but not changed – (normal operating conditions)

Read-Only Memory (ROM) • N input bits • 2N words by M bits • Implement M arbitrary functions of N variables – Example 8 words by 5 bits: 3 Input Lines

A B C

ROM 8 words x 5 bits

F0

F 1 F2

F3

F4

5 Output Lines

ROM Implementation • ROM = "Read Only Memory"

– values of memory locations are fixed ahead of time

• A ROM can be used to implement a truth table

– if the address is m-bits, we can address 2m entries in 0 0 0 0 0 1 1 the ROM. 0 1 1 1 0 0 – ourm outputs aren the bits of data 00that points 1 0 the 1 1 address 0 0 to. 0 1 1 1 0 0 0 1 1 1 1

0 0 1 1

0 1 0 1

0 0 0 0

0 0 1 1

0 0 1 1

0 1 0 1

ROM Implementation

• Suppose there are 10 inputs 10 address lines (i.e., 210 = 1024 different addresses) • Suppose there are 20 outputs • ROM is 210 x 20 = 20K bits (and a rather unusual size) • Rather wasteful, since lots of storage bits – For functions, doesn’t take advantage of K-maps, other minimization

Read-Only Memory Each minterm of each function can(ROM) be specified 3 Inputs Lines

A B C

ROM 8 words x 5 bits

F0

F1 F2

F3

F4

5 Outputs Lines

A

B

C

F0

F1 F 2 F 3 F 4

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 1 0 0 1 1

1 1 0 1 1 1 0 1

0 1 0 1 0 1 1 0

1 1 1 0 1 1 0 1

0 0 1 1 0 1 1 0

ROM Internal Structure n Inputs Lines .. .

n bit decoder

. . .

Memory Array 2n words x m bits

...

m Outputs Lines

Inside the ROM • Alternate view – Each possible horizontal/vertical intersection indicates a possible connection

• Or gates at bottom output the word selected by the decoder (32 x 8)

ROM Types • MROM – NMOS Type Access time 200ns – CMOS type Access time 100ns – 47256 32K x 8

• PROM – Field Programmable ROM or OTP – CMOS type access time 100-250ns – 27256 32K x 8

• EPROM – – – – – – –

CMOS type access time 200ns Special voltage level for programming 10v-25v Erasing 15-20 minutes UV light exposure Write time 100µs/byte Bulk erase only High density and low cost 2764 8K x 8

ROM Types • EEPROM – CMOS type access time 200ns – Special voltage for programming 21v and reverse voltage for erasing. – Write time 5µs/byte – Byte erase possible – Low density, high cost and highly complex – 2864 8K x 8

• Flash PROM – CMOS type access time 120ns – Both sector (512 byte) erase and bulk erase in milliseconds possible. – Write time 10µs/byte – Average density and lower cost than EEPROM. – 28256 32K x 8

MROM / PROM

MROM / PROM

ROM Memory Array m0=A’B’C’ m1=A’B’C

A B C

m2=A’BC’

3 to 8 decoder

m3=A’BC m4=AB’C’ m5=AB’C m6=ABC’ m7=ABC

F0

F1

F2

F3

F4

EEPROM / Flash PROM

Commercial EEPROM

EEPROM Programming

Speed

Price

SRAM

DRAM

(3ns min access time)

access time) Access modes speed up (DDR SDRAM, Cheapestetc.)

ROM

EEROM

Memory Type Comparisons Slow (15ns min Varies Fastest Slow Expensive

Volatili Erased on ty Power off

Erased on Power off

Uses

Large memories for computers

1. Highspeed memory 2. Small memories

Cheap

(read – 100ns) (write – 4700ns)

Expensive

Indestructibl Non-volatile e (may have limits) Program Any data that memory for needs to specialpersist after purpose power off systems

ROM Example A B C implements: F G H Specify a truth table for a ROM which F = AB + A’BC’

0 G = A’B’C + C’ 0 H = AB’C’ + ABC’ + A’B’C 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

ROM Example A B C implements: F G H Specify a truth table for a ROM which F = AB + A’BC’

0 G = A’B’C + C’ 0 H = AB’C’ + ABC’ + A’B’C 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 0 0 0 1 1

ROM Example A B C implements: F G H Specify a truth table for a ROM which F = AB + A’BC’

0 G = A’B’C + C’ 0 H = AB’C’ + ABC’ + A’B’C 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 0 0 0 1 1

1 1 1 0 1 0 1 0

0 1 0 0 1 0 1 0

Function Implementation m0=A’B’C’ m1=A’B’C

A B

m2=A’BC’

3 to 8 decoder

C

m3=A’BC m4=AB’C’ m5=AB’C m6=ABC’ m7=ABC

Each column is a new function Note: two outputs unused!

F

G

H

ROM • ROMs provide stable storage for data Summary • ROMs have address inputs and data outputs – ROMs directly implement truth tables

• In normal use ROMs are read-only – They are only read, not written

• ROMs are often used by computers to store critical information – Unlike SRAM, they maintain their storage after the power is turned off

PLD Overview • Programmable logic offers designers opportunity to customize chips • Programmable logic devices have a fixed logic structure • Programmable array logic contain AND-OR circuits – First introduced in early 1980’s

• Field programmable gate arrays (FPGAs) contain small blocks that implement truth tables – First introduced in 1985 (Xilinx Corporation)

• Software used to convert user designs to programming information

Roadmap • • • • •

PROM PLA PAL CPLD FPGA

NRE and unit cost metrics • Unit cost – the monetary cost of manufacturing each copy of the system, excluding NRE cost

• NRE cost (Non-Recurring Engineering cost) – The one-time monetary cost of designing the system

• total cost = NRE cost + unit cost * # of units • per-product cost = total cost / # of units = (NRE cost / # of units) + unit cost

Vahid & Givargis

PLD • Programmable Logic Device (PLD): – An integrated circuit chip that can be configured by end use to implement different digital hardware – Also known as “Field Programmable Device (FPD) “

• All layers already exist – Designers can purchase an IC – Connections on the IC are either created or destroyed to implement desired functionality – Field-Programmable Gate Array (FPGA) very popular

• Benefits – Low NRE costs, almost instant IC availability

• Drawbacks

PLD Advantages • Short design time Nonrecurring engineering cost• Less expensive at low PLD volume Cost

ASIC

Volume

PLD Categorization PLD

HCPL HighD Capacity PLD

SPLD Simple PLD

PLA Programmable Logic Array

PAL Programmable Array Logic

CPLD Complex PLD

FPGA Field Programmable Gate Array

PLD Logic Capacity • SPLD: about 200 gates – PLA, PAL

• CPLD – – – –

About 50 SPLD devices equivalent Altera MAX7000 (5K logic gates) Altera MAX (9K logic gates) Xilinx XC9500

• FPGA – Evolved from Mask-Programmable Gate Array (MPGA) in which customization is done during chip fabrication. – Xilinx Vertex-E ( 3 million logic gates)

Electrically Erasable PLDs • Conventional PLDs are either – One-time programmable Erasable • –EEUV PLDs can be programmed and erased in place • Must placed a programmer toaprogram them • A be small (fourin wire) connection to computer is needed • Once programmed, will retain program indefinitely • Never have to take the chip out of its circuit

Programmable ROM (PROM) N input

2

N

xM ROM

M output

• Address: N bits; Output word: M bits • ROM contains 2

N

words of M bits each

• The input bits decide the particular word that becomes availabl on output lines

Logic Diagram of 8x3 PROM

Sum of minterms

Combinational Circuit Implementation I0 I1 I2 F0 F1using F2 PROM 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 1 0 0 1 0

0 1 1 0 1 0 0 1

0 0 1 0 0 1 0 0

F0

F1

F2

PROM Types • Programmable PROM – Break links through current pulses – Write once, Read multiple times

• Erasable PROM (EPROM) – Program with ultraviolet light – Write multiple times, Read multiple times

• Electrically Erasable PROM (EEPROM)/ Flash Memory – Program with electrical signal – Write multiple times, Read multiple times

PROM: Advantages and Disadvantages • Widely used to implement functions with large number of inputs and outputs • Design of control units (Micro-programmed control units) • For combinational circuits with lots of don’t care terms, PROM is a wastage of logic resources

Programmed Array Logic (PAL) C

B

A

Fusable links – Links may be “blown”. Once blown, they are permanently open.

Fusable links

F1

+

12V

-

Current

Complex wiring is replaced with programming

F2 PALs support multiple functions of the same inputs C’ C B’ B A’ A

PAL Example C

B

A

Program F1=A’B’+A’C

A’B’

Blow all unused links

F1

A’C

A’BC

0

C’ C B’ B A’ A

Program F2=A’BC

F2

Leave unused product terms alone (AA’BB’CC’)

Schematic Representation x’s mark Connections – Fuses D C B A are not blown of PALs DC D’C’

F1=DC + D’C’ + BA’ + B’A

BA’ B’A DA CB’

F2=DA + CB’ + D’C’BA D’C’BA

0

x1

x2

x3

• Programmable Array Logic (PAL) – The AND gates are programmable, but the OR P1 gates are fixed. P2

f1

P3

P4

AND plane

f2

An example of a PAL

Programmable Array Logic (PAL) • Programmable AND array • Fixed OR array – Each output line permanently connected to a specific set of product terms

• Number of product terms per output > number of product terms in each sum-of-product expression • No sharing of product terms between outputs • Number of switching functions that can be implemented with PAL are more limited than PROM and PLA

Programmable Array – Implements sum-ofLogic products expressions – Four external inputs (and complements) – Feedback path from output F1 – Product term connections made via switches

x

x

Programmable Array – Consider implementing the x x x following expressionLogic x xx x

• I1 I2 I3 + I2 ‘ I 3 ‘ I4 + I 1 I4 = F 1

– Note that only functions of up to three product terms can be implements • Larger functions need to be chained together via the feedback path

x

The Way Things Are: Real PALs Tristate Buffer

2

Input pin I/O pin 4 Vcc

3

Input pin

GND

Output Inversion Ctrl

A More GeneralProgrammable Idea Logic Array

Programmed Array Logic

A PAL has limits on the arrangement of its sum-ofproducts groupings.

A PLA has complete flexibility of its sum-ofproducts groupings.

1 2

n

• Programmable Logic Array (PLA) – A collection of AND gates that feeds a set of OR gates – The inputs to each gate are programmable.

Input buffers and inverters x1 x1

xn xn P1

AND plane

Pk

General structure of a PLA

OR plane

f1

fm

PLA 4 X 6 X 2

Logic Implementation with PLA • Finite number of AND gates => simplify function to minimum number of product terms • Number of literals in a product term is not important since we have all the input variables • Sharing of product terms between outputs => multiple-output minimization

Design with PLA

x

1

x

2

x

3

Programmable connections

P1

OR plane

P2

P3

P4

AND plane

Gate-level diagram of a PLA

f1

f2

x1

x2

x3

OR plane P1

P2

P3

P4

AND plane

Customary schematic of a PLA

f1

f2

Sharing Product Terms in a PLA

D C B A

F = ABC + AD + AD G =ABC + ABC + AD H =ABC + BD J = B + AD

ABC ABC AD AD BD B

F

G

H J

•

Programming Devices PLAs and PALs are programmed using a special programmer

• Most devices are erasable • Don’t use fuses, but instead electrical methods of programming • Erased by exposing to UV light