Topic 7 Latches&flipflop
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Topic 7: Latches and Flip-flop
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
1
Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch
Edge-Triggered Flip-flops
S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop Asynchronous Inputs
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
2
Introduction A sequential circuit consists of a feedback path, and employs some memory elements. Combinational outputs
Memory outputs
Combinational logic
Memory elements
External inputs
Sequential circuit = Combinational logic + Memory Elements
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
3
Introduction There are two types of sequential circuits: synchronous: outputs change only at specific time asynchronous: outputs change at any time
Multivibrator: a class of sequential circuits. They can be: bistable (2 stable states) monostable or one-shot (1 stable state) astable (no stable state)
Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used for changing their state.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
4
Memory Elements Memory element: a device which can remember value indefinitely, or change value on command from its inputs. Q
Memory element
command
stored value
Characteristic table: Command (at time t)
Q(t)
Q(t+1)
Set
X
1
Reset
X
0
Memorise / No Change
FLB 20203 DIGITAL SYSTEMS
0 1
0 1
Q(t): current state Q(t+1) or Q+: next state
Sequential Logic: Latches & Flip-flops
5
Memory Elements Memory element with clock. Flip-flops are memory elements that change
.
state on clock signals
Memory element
command
Clock is usually a square wave.
Q stored value
clock
Positive pulses
Positive edges
FLB 20203 DIGITAL SYSTEMS
Negative edges
Sequential Logic: Latches & Flip-flops
6
Memory Elements Two types of triggering/activation: pulse-triggered edge-triggered
Pulse-triggered latches ON = 1, OFF = 0
Edge-triggered flip-flops positive edge-triggered (ON = from 0 to 1; OFF = other time) negative edge-triggered (ON = from 1 to 0; OFF = other
time)
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
7
S-R Latch
Complementary outputs: Q and Q'. When Q is HIGH, the latch is in SET state. When Q is LOW, the latch is in RESET state. For active-HIGH input S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW) D RESET state S=HIGH (and R=LOW) D SET state both inputs LOW D no change both inputs HIGH D Q and Q' both LOW (invalid)!
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
8
S-R Latch For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH) D RESET state S'=LOW (and R'=HIGH) D SET state both inputs HIGH D no change both inputs LOW D Q and Q' both HIGH (invalid)!
Drawback of S-R latch: invalid condition exists and must be avoided.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
9
S-R Latch Characteristics table for active-high input S-R latch: S
R
Q
Q'
0
0
NC
NC
1 0 1
0 1 1
1 0 0
0 1 0
No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
S
Q
R
Q'
S
Q
R
Q'
Characteristics table for active-low input S'-R' latch:
FLB 20203 DIGITAL SYSTEMS
S'
R'
Q
Q'
1
1
NC
NC
0 1 0
1 0 0
1 0 1
0 1 1
No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
Sequential Logic: Latches & Flip-flops
10
S-R Latch Active-HIGH input S-R latch 10 100 R
Q 11000
10 001 S
Q' 0 0 1 1 0
S 1 0 0 0 1
Active-LOW input S’-R’ latch S'
R'
Q Q'
S'
R' FLB 20203 DIGITAL SYSTEMS
Q Q'
S' R' 1 0 1 1 0 1 1 1 0 0
Sequential Logic: Latches & Flip-flops
R 0 0 1 0 1
Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!
Q Q' 0 1 initial 0 1 (afer S'=1, R'=0) 1 0 1 0 (after S'=0, R'=1) 1 1 invalid!
11
Gated S-R Latch S-R latch + enable input (EN) and 2 NAND gates → gated S-R latch. S
Q
EN
S
Q
EN
Q'
R
Q'
R
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
12
Gated S-R Latch Outputs change (if necessary) only when EN is HIGH. Under what condition does the invalid state occur? Characteristic table: EN=1
FLB 20203 DIGITAL SYSTEMS
Q(t)
S
R
Q(t+1)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 indeterminate 1 0 1 indeterminate
S R 0 0 1 1
Sequential Logic: Latches & Flip-flops
0 1 0 1
Q(t+1) No change Q(t) 0 Reset 1 Set indeterminate
Q(t+1) = S + R'.Q S.R = 0
13
Gated D Latch Make R input equal to S' → gated D latch. D latch eliminates the undesirable condition of invalid state in the SR latch. D
Q
EN
Q
EN
Q'
FLB 20203 DIGITAL SYSTEMS
D
Sequential Logic: Latches & Flip-flops
Q'
14
Gated D Latch When EN is HIGH, D=HIGH → latch is SET D=LOW → latch is RESET
Hence when EN is HIGH, Q ‘follows’ the D (data) input. Characteristic table: EN
D
Q(t+1)
1 1 0
0 1 X
0 1 Q(t)
Reset Set No change
When EN=1, Q(t+1) = D
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
15
Latch Circuits: Not Suitable Latch circuits are not suitable in synchronous logic circuits. When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.
The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.
This leads us to the edge-triggered memory elements called flip-flops.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
16
Edge-Triggered Flip-flops Flip-flops: synchronous bistable devices Output changes state at a specified point on a triggering input called the clock.
Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.
Clock signal Positive edges
FLB 20203 DIGITAL SYSTEMS
Negative edges
Sequential Logic: Latches & Flip-flops
17
Edge-Triggered Flip-flops S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input. S
Q
C R
D
Q
C Q'
J
Q
C Q'
K
Q'
J
Q
Positive edge-triggered flip-flops S
Q
C R
D
Q
C Q'
C Q'
K
Q'
Negative edge-triggered flip-flops FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
18
S-R Flip-flop S-R flip-flop: on the triggering edge of the clock pulse,
S=HIGH (and R=LOW) D SET state R=HIGH (and S=LOW) D RESET state both inputs LOW D no change both inputs HIGH D invalid
Characteristic table of positive edge-triggered S-R flip-flop: S
R
CLK
Q(t+1)
Comments
0 0 1 1
0 1 0 1
X ↑ ↑ ↑
Q(t) 0 1 ?
No change Reset Set Invalid
X = irrelevant (“don’t care”) ↑ = clock transition LOW to HIGH
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
19
S-R Flip-flop It comprises 3 parts: a basic NAND latch a pulse-steering circuit a pulse transition detector (or edge detector) circuit
The pulse transition detector detects a rising (or falling) edge and produces a very short-duration spike.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
20
S-R Flip-flop The pulse transition detector. S
Q
Pulse transition detector
CLK
Q'
R
CLK' CLK
CLK' CLK*
CLK*
CLK
CLK
CLK'
CLK'
CLK*
CLK*
Positive-going transition (rising edge) FLB 20203 DIGITAL SYSTEMS
CLK
Negative-going transition (falling edge)
Sequential Logic: Latches & Flip-flops
21
D Flip-flop D flip-flop: single input D (data) D=HIGH D SET state D=LOW D RESET state
Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter. D CLK
S
Q
C R
Q'
D
CLK
Q(t+1)
1 0
↑ ↑
1 0
Comments Set Reset
↑ = clock transition LOW to HIGH
A positive edge-triggered D flipflop formed with an S-R flip-flop. FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
22
D Flip-flop Application: Parallel data transfer. To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage. D
Q
Q1 = X*
CLK Q'
X
Combinational logic circuit
Y
D
Z
CLK
Q
Q2 = Y*
Q'
D Transfer
Q
Q3 = Z*
CLK Q' * After occurrence of negative-going transition
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
23
J-K Flip-flop J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
No invalid state. Include a toggle state. J=HIGH (and K=LOW) D SET state K=HIGH (and J=LOW) D RESET state both inputs LOW D no change both inputs HIGH D toggle
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
24
J-K Flip-flop J-K flip-flop. J Q
Pulse transition detector
CLK
Q'
K
Characteristic table. J
K
CLK
Q(t+1)
Comments
0 0 1 1
0 1 0 1
↑ ↑ ↑ ↑
Q(t) 0 1 Q(t)'
No change Reset Set Toggle
Q(t+1) = J.Q' + K'.Q FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
Q
J K
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Q(t+1) 0 0 1 1 1 0 1 0 25
T Flip-flop T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together. T Pulse transition detector
CLK
T
Q
J
Q
C
CLK Q'
K
Q'
Characteristic table. T
CLK
Q(t+1)
Comments
Q T
0 1
↑ ↑
Q(t) Q(t)'
No change Toggle
0 0 1 1
0 1 0 1
Q(t+1) 0 1 1 0
Q(t+1) = T.Q' + T'.Q FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
26
T Flip-flop Application: Frequency division. High
High J
CLK
J
Q
C
High
CLK
K CLK
CLK
Q
QA
QA
J
C
C
K
K
QB
QB
Divide clock frequency by 2.
FLB 20203 DIGITAL SYSTEMS
Divide clock frequency by 4.
Sequential Logic: Latches & Flip-flops
27
Asynchronous Inputs S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.
Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]
When PRE=HIGH, Q is immediately set to HIGH. When CLR=HIGH, Q is immediately cleared to LOW. Flip-flop in normal operation mode when both PRE and CLR are LOW.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
28
Asynchronous Inputs A J-K flip-flop with active-LOW preset and clear inputs. PRE
PRE J
J
Q
C
CLK
Q'
K
Q Pulse transition detector Q'
K
CLR
CLR CLK PRE CLR
J = K = HIGH FLB 20203 DIGITAL SYSTEMS
Q
Preset
Sequential Logic: Latches & Flip-flops
Toggle
Clear
29
Master-Slave Flip-flops Another class is pulse-triggered master-slave which largely replaced by edge-triggered device.
Data entered at leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge
Does not allow data to change while the clock pulse is active
Truth table operation same as for the edge-triggered JK flip-flop except the way it is clocked.
Compose of 2 sections: master section and slave section Master section – a gated latch Slave section – the same except it is clocked at an inverted clock pulse and is controlled by the output of master section
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
30
Master-Slave Flip-flops
Master assume state determine by inputs JK at leading edge of clock pulse
The state of master section transfer to slave section at trailing edge since the clock is inverted
At trailing edge of clock pulse, the state of slaves appears on the Q and Q’ outputs
The Q output is connected back to the input of G2 and Q’ to the input G1 to produce the toggle operation when J = K = 1 FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
31
Master-Slave Flip-flops Truth Table for master-slave JK flip-flops
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
32
Master-Slave Flip-flops Logic Symbols for master-slave JK flip-flops
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
33
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
1
Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch
Edge-Triggered Flip-flops
S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop Asynchronous Inputs
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
2
Introduction A sequential circuit consists of a feedback path, and employs some memory elements. Combinational outputs
Memory outputs
Combinational logic
Memory elements
External inputs
Sequential circuit = Combinational logic + Memory Elements
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
3
Introduction There are two types of sequential circuits: synchronous: outputs change only at specific time asynchronous: outputs change at any time
Multivibrator: a class of sequential circuits. They can be: bistable (2 stable states) monostable or one-shot (1 stable state) astable (no stable state)
Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used for changing their state.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
4
Memory Elements Memory element: a device which can remember value indefinitely, or change value on command from its inputs. Q
Memory element
command
stored value
Characteristic table: Command (at time t)
Q(t)
Q(t+1)
Set
X
1
Reset
X
0
Memorise / No Change
FLB 20203 DIGITAL SYSTEMS
0 1
0 1
Q(t): current state Q(t+1) or Q+: next state
Sequential Logic: Latches & Flip-flops
5
Memory Elements Memory element with clock. Flip-flops are memory elements that change
.
state on clock signals
Memory element
command
Clock is usually a square wave.
Q stored value
clock
Positive pulses
Positive edges
FLB 20203 DIGITAL SYSTEMS
Negative edges
Sequential Logic: Latches & Flip-flops
6
Memory Elements Two types of triggering/activation: pulse-triggered edge-triggered
Pulse-triggered latches ON = 1, OFF = 0
Edge-triggered flip-flops positive edge-triggered (ON = from 0 to 1; OFF = other time) negative edge-triggered (ON = from 1 to 0; OFF = other
time)
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
7
S-R Latch
Complementary outputs: Q and Q'. When Q is HIGH, the latch is in SET state. When Q is LOW, the latch is in RESET state. For active-HIGH input S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW) D RESET state S=HIGH (and R=LOW) D SET state both inputs LOW D no change both inputs HIGH D Q and Q' both LOW (invalid)!
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
8
S-R Latch For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH) D RESET state S'=LOW (and R'=HIGH) D SET state both inputs HIGH D no change both inputs LOW D Q and Q' both HIGH (invalid)!
Drawback of S-R latch: invalid condition exists and must be avoided.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
9
S-R Latch Characteristics table for active-high input S-R latch: S
R
Q
Q'
0
0
NC
NC
1 0 1
0 1 1
1 0 0
0 1 0
No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
S
Q
R
Q'
S
Q
R
Q'
Characteristics table for active-low input S'-R' latch:
FLB 20203 DIGITAL SYSTEMS
S'
R'
Q
Q'
1
1
NC
NC
0 1 0
1 0 0
1 0 1
0 1 1
No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
Sequential Logic: Latches & Flip-flops
10
S-R Latch Active-HIGH input S-R latch 10 100 R
Q 11000
10 001 S
Q' 0 0 1 1 0
S 1 0 0 0 1
Active-LOW input S’-R’ latch S'
R'
Q Q'
S'
R' FLB 20203 DIGITAL SYSTEMS
Q Q'
S' R' 1 0 1 1 0 1 1 1 0 0
Sequential Logic: Latches & Flip-flops
R 0 0 1 0 1
Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!
Q Q' 0 1 initial 0 1 (afer S'=1, R'=0) 1 0 1 0 (after S'=0, R'=1) 1 1 invalid!
11
Gated S-R Latch S-R latch + enable input (EN) and 2 NAND gates → gated S-R latch. S
Q
EN
S
Q
EN
Q'
R
Q'
R
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
12
Gated S-R Latch Outputs change (if necessary) only when EN is HIGH. Under what condition does the invalid state occur? Characteristic table: EN=1
FLB 20203 DIGITAL SYSTEMS
Q(t)
S
R
Q(t+1)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 indeterminate 1 0 1 indeterminate
S R 0 0 1 1
Sequential Logic: Latches & Flip-flops
0 1 0 1
Q(t+1) No change Q(t) 0 Reset 1 Set indeterminate
Q(t+1) = S + R'.Q S.R = 0
13
Gated D Latch Make R input equal to S' → gated D latch. D latch eliminates the undesirable condition of invalid state in the SR latch. D
Q
EN
Q
EN
Q'
FLB 20203 DIGITAL SYSTEMS
D
Sequential Logic: Latches & Flip-flops
Q'
14
Gated D Latch When EN is HIGH, D=HIGH → latch is SET D=LOW → latch is RESET
Hence when EN is HIGH, Q ‘follows’ the D (data) input. Characteristic table: EN
D
Q(t+1)
1 1 0
0 1 X
0 1 Q(t)
Reset Set No change
When EN=1, Q(t+1) = D
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
15
Latch Circuits: Not Suitable Latch circuits are not suitable in synchronous logic circuits. When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.
The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.
This leads us to the edge-triggered memory elements called flip-flops.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
16
Edge-Triggered Flip-flops Flip-flops: synchronous bistable devices Output changes state at a specified point on a triggering input called the clock.
Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.
Clock signal Positive edges
FLB 20203 DIGITAL SYSTEMS
Negative edges
Sequential Logic: Latches & Flip-flops
17
Edge-Triggered Flip-flops S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input. S
Q
C R
D
Q
C Q'
J
Q
C Q'
K
Q'
J
Q
Positive edge-triggered flip-flops S
Q
C R
D
Q
C Q'
C Q'
K
Q'
Negative edge-triggered flip-flops FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
18
S-R Flip-flop S-R flip-flop: on the triggering edge of the clock pulse,
S=HIGH (and R=LOW) D SET state R=HIGH (and S=LOW) D RESET state both inputs LOW D no change both inputs HIGH D invalid
Characteristic table of positive edge-triggered S-R flip-flop: S
R
CLK
Q(t+1)
Comments
0 0 1 1
0 1 0 1
X ↑ ↑ ↑
Q(t) 0 1 ?
No change Reset Set Invalid
X = irrelevant (“don’t care”) ↑ = clock transition LOW to HIGH
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
19
S-R Flip-flop It comprises 3 parts: a basic NAND latch a pulse-steering circuit a pulse transition detector (or edge detector) circuit
The pulse transition detector detects a rising (or falling) edge and produces a very short-duration spike.
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
20
S-R Flip-flop The pulse transition detector. S
Q
Pulse transition detector
CLK
Q'
R
CLK' CLK
CLK' CLK*
CLK*
CLK
CLK
CLK'
CLK'
CLK*
CLK*
Positive-going transition (rising edge) FLB 20203 DIGITAL SYSTEMS
CLK
Negative-going transition (falling edge)
Sequential Logic: Latches & Flip-flops
21
D Flip-flop D flip-flop: single input D (data) D=HIGH D SET state D=LOW D RESET state
Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter. D CLK
S
Q
C R
Q'
D
CLK
Q(t+1)
1 0
↑ ↑
1 0
Comments Set Reset
↑ = clock transition LOW to HIGH
A positive edge-triggered D flipflop formed with an S-R flip-flop. FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
22
D Flip-flop Application: Parallel data transfer. To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage. D
Q
Q1 = X*
CLK Q'
X
Combinational logic circuit
Y
D
Z
CLK
Q
Q2 = Y*
Q'
D Transfer
Q
Q3 = Z*
CLK Q' * After occurrence of negative-going transition
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
23
J-K Flip-flop J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
No invalid state. Include a toggle state. J=HIGH (and K=LOW) D SET state K=HIGH (and J=LOW) D RESET state both inputs LOW D no change both inputs HIGH D toggle
FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
24
J-K Flip-flop J-K flip-flop. J Q
Pulse transition detector
CLK
Q'
K
Characteristic table. J
K
CLK
Q(t+1)
Comments
0 0 1 1
0 1 0 1
↑ ↑ ↑ ↑
Q(t) 0 1 Q(t)'
No change Reset Set Toggle
Q(t+1) = J.Q' + K'.Q FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
Q
J K
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Q(t+1) 0 0 1 1 1 0 1 0 25
T Flip-flop T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together. T Pulse transition detector
CLK
T
Q
J
Q
C
CLK Q'
K
Q'
Characteristic table. T
CLK
Q(t+1)
Comments
Q T
0 1
↑ ↑
Q(t) Q(t)'
No change Toggle
0 0 1 1
0 1 0 1
Q(t+1) 0 1 1 0
Q(t+1) = T.Q' + T'.Q FLB 20203 DIGITAL SYSTEMS
Sequential Logic: Latches & Flip-flops
26
T Flip-flop Application: Frequency division. High
High J
CLK
J
Q
C
High
CLK
K CLK
CLK
Q
QA
QA
J
C
C
K
K
QB
QB
Divide clock frequency by 2.
FLB 20203 DIGITAL SYSTEMS
Divide clock frequency by 4.
Sequential Logic: Latches & Flip-flops
27
Asynchronous Inputs S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.
Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]
When PRE=HIGH, Q is immediately set to HIGH. When CLR=HIGH, Q is immediately cleared to LOW. Flip-flop in normal operation mode when both PRE and CLR are LOW.
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Asynchronous Inputs A J-K flip-flop with active-LOW preset and clear inputs. PRE
PRE J
J
Q
C
CLK
Q'
K
Q Pulse transition detector Q'
K
CLR
CLR CLK PRE CLR
J = K = HIGH FLB 20203 DIGITAL SYSTEMS
Q
Preset
Sequential Logic: Latches & Flip-flops
Toggle
Clear
29
Master-Slave Flip-flops Another class is pulse-triggered master-slave which largely replaced by edge-triggered device.
Data entered at leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge
Does not allow data to change while the clock pulse is active
Truth table operation same as for the edge-triggered JK flip-flop except the way it is clocked.
Compose of 2 sections: master section and slave section Master section – a gated latch Slave section – the same except it is clocked at an inverted clock pulse and is controlled by the output of master section
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Master-Slave Flip-flops
Master assume state determine by inputs JK at leading edge of clock pulse
The state of master section transfer to slave section at trailing edge since the clock is inverted
At trailing edge of clock pulse, the state of slaves appears on the Q and Q’ outputs
The Q output is connected back to the input of G2 and Q’ to the input G1 to produce the toggle operation when J = K = 1 FLB 20203 DIGITAL SYSTEMS
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Master-Slave Flip-flops Truth Table for master-slave JK flip-flops
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Master-Slave Flip-flops Logic Symbols for master-slave JK flip-flops
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