Tomi Report- 3rd

68000 Interrupt Structure • The 68000 Interrupt Structure has eight interrupt priority levels • The priority at which the processor is running at any given time is encoded in three bits of the processor status word with level 0 being the lowest priority • A request is accepted only if its priority is higher than that of the processor except for level 7 requests.

Two Types • Internal Interrupt • External Interrupt

Internal Interrupt

• The internal interrupt is a Software Interrupt. • Generated when the 68000 executes a software interruption called TRAP or by some undesirable event.

External Interrupts • has seven level of external interrupt [1-7] • Level 0 indicates no interrupt service is requested • Levels 1 to 6 are levelsensitive • Level 7 is edge trigerred

• The 68000 checks for and accepts requests for interrupts only between instructions • Level 7 are non maskable interrupt. – Always acknowledged – Has the highest priority

• The processor automatically saves the contents of the program counter and the processor status word at the time of the interruption. • Trace Bit (T) • Enables a special type of interrupt called a trace exception

• Supervisor bit (S) • Determines whether the processor is running in the Supervisor mode (S=1) or User mode (S=0)

• RTE (Return-from-exception) – At the end of the exception processing, this instruction restores the 68000 to USER mode

• The 68000 can also provide an autovector facility as an alternative

Pentium Interrupt Structure • Interrupts • Nonmaskable Interrupt (NMI) • Maskable Interrupt • Enabled • Disabled

• Occurences of some interrupt and exception events causes the processor to branch to an interrupt service routine • Advanced Programmable Interrupt Controller (APIC) • EFLAGS – processor status register (INTEL)

• Interrupt Enable Flag (IF) • Trap Flag (TF) • I/O Privilege Level (IOPL)

• Pentium processor has 4 levels of privilege (0-3). • Where Level 0 is the most highly privileged level • Switching from one level to another involves a number of checks implemented in a mechanism called a gate

The processor takes the following actions: • 1. Push processor SR, CS, and EIP onto stack pointed by ESP • 2. If exception resulting from an abnormal execution condition, it pushes code on the stack • 3. Clears the IF • 4. Fetches the starting address from Interrupt Descriptor Table

• After servicing the IRQ, the interruptservice routine returns to the interrupted program. • IRET pops EIP,CS and the processor SR from the stack into the corresponding registers, thus restoring the processor state

Direct Memory Access • The capability provided by some computer bus architectures that allows data to be sent directly from an attached device (such as a disk drive) to the memory on the computer's motherboard.

• DMA controller – control circuit • To initiate transfer, the processor sends the starting address, quantity, destination. • When the entire block is transferred, the controller informs the processor by raising an interrupt signal.

• OS is also responsible for suspending the execution of one program and starting another • The program is in blocked state if the transfer involves DMA

• R/W bit determines the direction of the transfer • IRQ, the controller sets the IRQ bit to 1 when it has requested an interrupt • IE, when this flag is set to 1, it causes the controller to raise an interrupt after it has completed transferring a block of data • When the controller has completed transferring a block of data and is ready to receive another command, the Done flag is set to 1.

DMAC options for data transfer • CYCLE STEAL • BLOCK or BURST mode

Bus Arbitration • The process by which the next device to become the bus master is selected and bus mastership is transferred to it • Two Approaches • Centralized • Distributed

Centralized Arbitration • Bus Request Line – This is a wired-OR line: the controller only knows that a request has been made by a device, but doesn't know which device made the request.

• Bus-Grant – This line is propagated through all of the devices.

Distributed Arbitration • The Distributed arbitration means that all devices waiting to use the bus have equal responsibility in carrying out the arbitration process, without using a central arbiter