Sta

Static Timing Analysis Prashant D. Joshi IBM

Life cycle of a Chip design Circuit Design

Physical Design

Timing Analysis

Logic Design New Stuff Changes

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Hierarchical Design (and analysis)

Prashant D. Joshi IBM

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STA Inputs and Outputs Timing Specs REPORTS

Prashant D. Joshi IBM

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Inputs: Timing Specs •

Targets to which the circuits are to be designed. – capacitive/resistive load to drive – expected arrival times of signals – actual arrival times of signals – slopes of signals – wire types, widths – driver strengths – etc. • These specs enable the correct design of the circuits. – If these specifications change for a circuit, its design has to change accordingly, and all circuits neighboring it could also get affected. Prashant D. Joshi IBM

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Other Inputs…. • Clock definitions define all the clocks that are in use. Use of multiple clocks, relationship between clocks etc. • Design netlist describing what the design “contains”, as well as design rules to indicate what timing constraints apply to the various design points. • Technology and circuit libraries enable calculation of the delays in the appropriate libraries. • Other user defined inputs like, defaults, overrides, adjusts, ignores etc needed. Prashant D. Joshi IBM

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Outputs • Reports showing – Timing violations (What is Setup and Hold?) – Slew/slope violations – Floating/unused signals – Timing related violations in the presence of noise – Feed back new design criteria – etc Prashant D. Joshi IBM

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Basics of Static Timing Clock Timing not being met

Launch Edge

Capture Edge

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Basics of Static Timing… Block A

Block B

Present status Failing Margin

Changed Targets

New Design New Failing Margin

If all three do not get resolved at once, the targets continue to change after each iteration. …..chasing a moving target?

New Targets Chronological Time

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What is Static Timing Analysis (STA) • A thorough and efficient way to determine if the logic being designed will result in the hardware functioning within its timing specifications and constraints. – Do the signals arrive at pins in time. – Do the signals stay long enough at the required state to be useful. – Will the signals propagate with proper slew (slope). – Are clock/data signals wide enough. – Will the hardware run at a specified clock frequency – Identify parts of the path which need attention – Clock distribution and correctness – Etc… Prashant D. Joshi IBM

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Models of lower level designs • Lowest level design blocks – rigorously timed (spice?) – timing model/abstract • Table of PI/PO, etas, at, slew requirements etc • If internals to be viewed then netlist needed

– Pins, names, locations, some internal details.

• Hierarchically time the blocks using STA

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Typical Problems •

New design constraints – What is a fair way to generate them? – Chasing a moving target?

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Incomplete data (early part of project, hopefully) – – – – – –

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Mismatching data inputs (parts of chip out of sync in progress) Layout data incomplete (buffers, shorting, failing layout rules) Pins mismatch (names, location wrt wiring) Blocks missing Wires without proper buffering Parasitics

Multiple instantiation of blocks Amount of data!!! (and despite that lack of some) Changes late in the design phase – Due to noise effects on timing

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Other stuff… – Team sizes, split up geographically, computer resources etc.

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Timing and Noise • Similarities between Timing and Noise analysis methodologies – Lowest level analysis – Abstracts – Extracted data needed for accuracy – Top level analysis and feedback – Interdependency between noise and timing analysis Prashant D. Joshi IBM

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