Spartan3E Presentation by : Nilesh A. shah (p08ec913)
Overview •
All Xilinx FPGAs contain the same basic resources – Slices (grouped into CLBs) • Contain combinatorial logic and register resources – IOBs • Interface between the FPGA and the outside world – Programmable interconnect – Other resources • Memory • Multipliers • Global clock buffers • Boundary scan logic
Xilinx FPGA Architecture • •
• •
Logic Fabric – Gates and flip-flops Embedded Blocks – Memory – DSP/Multipliers – Clock management – High speed serial I/O – Soft/hard processors Programmable I/Os In-system programmable
Logic Fabric •
• •
Logic Cell – Lookup table (LUT) – Flip-Flop – Carry logic – Muxes (not shown) Slice – Two Logic Cells Spartan-3E FPGAs – 2K to 33K logic cells
I3 I2 I1
O
0
1
CE
SET
D
I0
Q RST
I3 I2 I1 I0
O
0
1
SET CE D
Q RST
Memory •
Block RAM – RAM or ROM – True dual port • Separate read and write ports – Independent port size • Data width translation – Excellent for FIFOs
DIA DIPA
DOA DOPA
ADDRA CLKA
DIB DIPB
DOB DOPB
ADDRB CLKB
Multipliers •
18 – – –
18 bit
x 18 Multipliers Signed or unsigned Optional pipeline stage Cascadable 18 bit
36 bit
Clock Management •
Digital Clock Managers (DCMs) – Clock de-skew – Phase shifting – Clock multiplication – Clock division – Frequency synthesis
CLKIN CLK0 CLK90 CLKFX
Programmable I/Os • • • • •
Single-ended Differential / LVDS Programmable I/O standards – Multiple I/O banks DDR I/O registers On-chip termination RegDDR mux Reg
3-State
Input Reg Reg
RegDDR mux PAD Reg Output
I/O Banks
Advanced, Low-Cost Features of SPARTEN 3E • Five devices with 100K to 16M system gates • From 66 to 376 I/Os with package and density migration • Up to 648 Kbits of block RAM and up to 231 Kbits of distributed RAM • Up to 36 embedded 18x18 multipliers for high performance DSP applications • Up to eight Digital Clock Managers
Xilinx Spartan-3E Family 3S100E
3S250E 3S500E 3S1200E 3S1600E
Device Gates
100K
250K
500K
1.2M
1.6M
Logic Cells
2,160
5,508
10,476
19,512
33,192
Maximum I/O
108
172
232
304
376
Block RAM bits
72K
216K
360K
504K
648K
Distributed RAM bits 18x18 Multipliers DCMs
15K
38K
73K
136K
231K
4
12
20
28
36
2
4
4
8
8
Spartan-3E CLB Resources
Available User I/Os and Differential (Diff) I/O Pairs
Spartan-3E Starter Kit
Spartan-3E Kit specific features • • • • • • • •
Parallel NOR Flash configuration MultiBoot FPGA configuration from Parallel NOR Flash PROM SPI serial Flash configuration MicroBlaze™ 32-bit embedded RISC processor PicoBlaze™ 8-bit embedded controller DDR memory interfaces Four-output, SPI-based Digital-to-Analog Converter (DAC) Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-amplifier
Spartan-3E FPGA Board cont. • Connectors and Interfaces – – – – – – – – – –
Ethernet JTAG USB download Two 9-pin RS-232 Serial Port, PS/2- style mouse/keyboard port rotary encoder with push button Four Slide Switches Eight Individual LED Outputs Four Momentary-Contact Push Buttons 100-Pin hirose Expansion Connection Ports Three 6-pin expansion connectors
• Display: 16 character - 2 Line LCD
•A typical FPGA application uses a single non-volatile memory to store configuration images. To demonstrate new Spartan-3E capabilities, the starter kit board has three different configuration memory sources that all need to function well together. The extra configuration functions make the starter kit board more complex than typicalSpartan-3Eapplications. •The starter kit board also includes an on-board USB-based JTAG programming interface.The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable.
Voltages for all Applications:The Spartan-3E Starter Kit board showcases a triple-output regulator developed by Texas Instruments, the TPS75003 specifically to power Spartan-3 and Spartan-3E FPGAs. This regulator is sufficient for most stand-alone FPGA applications. However, the starter kit board includes DDR SDRAM, which requires its own high-current supply. Similarly, the USB-based JTAG download solution requires a separate
Slide Switches
Push-Button Switches
Rotary Push-Button Switch
Available Clock Inputs
On-Board 50 MHz Oscilla Discrete LEDs
FPGA Configuration Options The Spartan-3E Starter Kit board supports a variety of FPGA configuration options: • Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD. • Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode. • Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode. • Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down configuration modes. Further, an FPGA application can dynamically load two different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode.
Detailed Configuration nfiguration Mode Jumper Settings Options
DB9 Serial Port Connecto DB15 VGA Connector
Digital-to-Analog Converter and Associated Header
DCE DTE
Two-Channel Analo Capture Circuit
RJ-45 Ethernet Connector
Expansion Headers
Xilinx Design Process Design Entry Synthesis Constraints
Implementation Constraints
FloorPlanning
Synthesis
Behavioral Simulation
Implementa •tion Translate •Map •Place & Route
Timing Analysis Silicon
Timing Simulation
Thank you QUESTION???