Sn74ls240
This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA
Overview
Download & View Sn74ls240 as PDF for free.
More details
- Words: 912
- Pages: 4
SN54/74LS240 SN54/74LS241 SN54/74LS244
OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.
OCTAL BUFFER / LINE DRIVER WITH 3-STATE OUTPUTS
• Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Input Clamp Diodes Limit High-Speed Termination Effects
LOW POWER SCHOTTKY
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) J SUFFIX CERAMIC CASE 732-03
SN54 / 74LS240 VCC 2G 20
19
1Y1
2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
18
17
16
15
14
13
12
20
11
1
N SUFFIX PLASTIC CASE 738-03
20 1
1 1G
2 1A1
3 4 5 2Y4 1A2 2Y3
6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND
SN54 / 74LS241 VCC 2G 20
19
1Y1
2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
18
17
16
15
14
DW SUFFIX SOIC CASE 751D-03
20
13
12
1
11
ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 1G
2 1A1
3 4 5 2Y4 1A2 2Y3
6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND
SN54 / 74LS244 VCC 2G
1Y1
2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17
20
19
18
16
1 1G
2 1A1
3 4 5 2Y4 1A2 2Y3
15
14
13
12
11
8 9 10 6 7 1A3 2Y2 1A4 2Y1 GND
FAST AND LS TTL DATA 5-1
SN54/74LS240 • SN54/74LS241 • SN54/74LS244 TRUTH TABLES SN54 / 74LS244
SN54 / 74LS240 INPUTS
INPUTS OUTPUT
1G, 2G
D
L L H
L H X
OUTPUT
H L (Z)
1G, 2G
D
L L H
L H X
L H (Z)
SN54 / 74LS241 INPUTS
INPUTS
1G
D
L L H
L H X
OUTPUT
OUTPUT
L H (Z)
2G
D
H H L
L H X
L H (Z)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance
GUARANTEED OPERATING RANGES Min
Typ
Max
Unit
VCC
Symbol Supply Voltage
54 74
4.5 4.75
5.0 5.0
5.5 5.25
V
TA
Operating Ambient Temperature Range
54 74
– 55 0
25 25
125 70
°C
IOH
Output Current — High
54, 74
– 3.0
mA
54 74
– 12 – 15
mA
54 74
12 24
mA
IOL
Parameter
Output Current — Low
FAST AND LS TTL DATA 5-2
SN54/74LS240 • SN54/74LS241 • SN54/74LS244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol
Min
P Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VT+–VT–
Hysteresis
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOZH
Typ
Max
U i Unit
2.0 54
0.7
74
0.8 0.2
0.4 – 0.65
54, 74
2.4
54, 74
2.0
– 1.5
3.4
T Test C Conditions di i
V
Guaranteed Input HIGH Voltage for All Inputs
V
Guaranteed Input p LOW Voltage g for All Inputs
V
VCC = MIN
V
VCC = MIN, IIN = – 18 mA
V
VCC = MIN, IOH = – 3.0 mA
V
VCC = MIN, IOH = MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table
54, 74
0.25
0.4
V
IOL = 12 mA
74
0.35
0.5
V
IOL = 24 mA
Output Off Current HIGH
20
µA
VCC = MAX, VOUT = 2.7 V
IOZL
Output Off Current LOW
– 20
µA
VCC = MAX, VOUT = 0.4 V
20 IIH
Input HIGH Current
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
– 0.2
mA
VCC = MAX, VIN = 0.4 V
IOS
Output Short Circuit Current (Note 1)
– 225
mA
VCC = MAX
A mA
VCC = MAX
– 40
Power Supply Current Total, Output HIGH Total, Output LOW ICC Total at HIGH Z
27 LS240
44
LS241/244
46
LS240
50
LS241/244
54
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol
P Parameter
Min
Typ
Max
U i Unit
tPLH tPHL
Propagation Delay, Data to Output LS240
9.0 12
14 18
ns
tPLH tPHL
Propagation Delay, Data to Output LS241 / 244
12 12
18 18
ns
tPZH
Output Enable Time to HIGH Level
15
23
ns
tPZL
Output Enable Time to LOW Level
20
30
ns
tPLZ
Output Disable Time from LOW Level
15
25
ns
tPHZ
Output Disable Time from HIGH Level
10
18
ns
FAST AND LS TTL DATA 5-3
T Test C Conditions di i
CL = 45 pF, F RL = 667 Ω
CL = 5.0 p pF,, RL = 667 Ω
SN54/74LS240 • SN54/74LS241 • SN54/74LS244
AC WAVEFORMS
VIN
1.3 V
1.3 V tPLH
VOUT
VCC
tPHL
1.3 V
1.3 V
RL
Figure 1
SW1
TO OUTPUT UNDER TEST VIN
1.3 V
1.3 V tPHL 1.3 V
VOUT
5 kΩ
tPLH 1.3 V
CL*
SW2
Figure 2
VE
1.3 V
VE
1.3 V tPZL
SYMBOL
≈ 1.3 V VOL
1.3 V
VOUT
SWITCH POSITIONS tPLZ
0.5 V
Figure 3
SW1
SW2
tPZH
Open
Closed
tPZL
Closed
Open
tPLZ
Closed
Closed
tPHZ
Closed
Closed
Figure 5 VE 1.3 V VE
1.3 V
tPZH VOUT
1.3 V
tPHZ ≥VOH ≈ 1.3 V 0.5 V
Figure 4
FAST AND LS TTL DATA 5-4
OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.
OCTAL BUFFER / LINE DRIVER WITH 3-STATE OUTPUTS
• Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Input Clamp Diodes Limit High-Speed Termination Effects
LOW POWER SCHOTTKY
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) J SUFFIX CERAMIC CASE 732-03
SN54 / 74LS240 VCC 2G 20
19
1Y1
2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
18
17
16
15
14
13
12
20
11
1
N SUFFIX PLASTIC CASE 738-03
20 1
1 1G
2 1A1
3 4 5 2Y4 1A2 2Y3
6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND
SN54 / 74LS241 VCC 2G 20
19
1Y1
2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
18
17
16
15
14
DW SUFFIX SOIC CASE 751D-03
20
13
12
1
11
ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 1G
2 1A1
3 4 5 2Y4 1A2 2Y3
6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND
SN54 / 74LS244 VCC 2G
1Y1
2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17
20
19
18
16
1 1G
2 1A1
3 4 5 2Y4 1A2 2Y3
15
14
13
12
11
8 9 10 6 7 1A3 2Y2 1A4 2Y1 GND
FAST AND LS TTL DATA 5-1
SN54/74LS240 • SN54/74LS241 • SN54/74LS244 TRUTH TABLES SN54 / 74LS244
SN54 / 74LS240 INPUTS
INPUTS OUTPUT
1G, 2G
D
L L H
L H X
OUTPUT
H L (Z)
1G, 2G
D
L L H
L H X
L H (Z)
SN54 / 74LS241 INPUTS
INPUTS
1G
D
L L H
L H X
OUTPUT
OUTPUT
L H (Z)
2G
D
H H L
L H X
L H (Z)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance
GUARANTEED OPERATING RANGES Min
Typ
Max
Unit
VCC
Symbol Supply Voltage
54 74
4.5 4.75
5.0 5.0
5.5 5.25
V
TA
Operating Ambient Temperature Range
54 74
– 55 0
25 25
125 70
°C
IOH
Output Current — High
54, 74
– 3.0
mA
54 74
– 12 – 15
mA
54 74
12 24
mA
IOL
Parameter
Output Current — Low
FAST AND LS TTL DATA 5-2
SN54/74LS240 • SN54/74LS241 • SN54/74LS244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol
Min
P Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VT+–VT–
Hysteresis
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOZH
Typ
Max
U i Unit
2.0 54
0.7
74
0.8 0.2
0.4 – 0.65
54, 74
2.4
54, 74
2.0
– 1.5
3.4
T Test C Conditions di i
V
Guaranteed Input HIGH Voltage for All Inputs
V
Guaranteed Input p LOW Voltage g for All Inputs
V
VCC = MIN
V
VCC = MIN, IIN = – 18 mA
V
VCC = MIN, IOH = – 3.0 mA
V
VCC = MIN, IOH = MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table
54, 74
0.25
0.4
V
IOL = 12 mA
74
0.35
0.5
V
IOL = 24 mA
Output Off Current HIGH
20
µA
VCC = MAX, VOUT = 2.7 V
IOZL
Output Off Current LOW
– 20
µA
VCC = MAX, VOUT = 0.4 V
20 IIH
Input HIGH Current
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
– 0.2
mA
VCC = MAX, VIN = 0.4 V
IOS
Output Short Circuit Current (Note 1)
– 225
mA
VCC = MAX
A mA
VCC = MAX
– 40
Power Supply Current Total, Output HIGH Total, Output LOW ICC Total at HIGH Z
27 LS240
44
LS241/244
46
LS240
50
LS241/244
54
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits S b l Symbol
P Parameter
Min
Typ
Max
U i Unit
tPLH tPHL
Propagation Delay, Data to Output LS240
9.0 12
14 18
ns
tPLH tPHL
Propagation Delay, Data to Output LS241 / 244
12 12
18 18
ns
tPZH
Output Enable Time to HIGH Level
15
23
ns
tPZL
Output Enable Time to LOW Level
20
30
ns
tPLZ
Output Disable Time from LOW Level
15
25
ns
tPHZ
Output Disable Time from HIGH Level
10
18
ns
FAST AND LS TTL DATA 5-3
T Test C Conditions di i
CL = 45 pF, F RL = 667 Ω
CL = 5.0 p pF,, RL = 667 Ω
SN54/74LS240 • SN54/74LS241 • SN54/74LS244
AC WAVEFORMS
VIN
1.3 V
1.3 V tPLH
VOUT
VCC
tPHL
1.3 V
1.3 V
RL
Figure 1
SW1
TO OUTPUT UNDER TEST VIN
1.3 V
1.3 V tPHL 1.3 V
VOUT
5 kΩ
tPLH 1.3 V
CL*
SW2
Figure 2
VE
1.3 V
VE
1.3 V tPZL
SYMBOL
≈ 1.3 V VOL
1.3 V
VOUT
SWITCH POSITIONS tPLZ
0.5 V
Figure 3
SW1
SW2
tPZH
Open
Closed
tPZL
Closed
Open
tPLZ
Closed
Closed
tPHZ
Closed
Closed
Figure 5 VE 1.3 V VE
1.3 V
tPZH VOUT
1.3 V
tPHZ ≥VOH ≈ 1.3 V 0.5 V
Figure 4
FAST AND LS TTL DATA 5-4
Related Documents
Sn74ls240
April 2020 2More Documents from "Diego de Leon Cenoz"
Tl064
April 2020 5
74hc_hct132_cnv_2
April 2020 3
Presentacion Y Objetivos
April 2020 6
Sn74ls240
April 2020 2
Wszedx.docx
December 2019 5