5
D
C
4
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1
Teco_V862 Version Document -------------------------------------------------------------------Main Features: 1. System: ZR36862+16M SDRAM + 8M FLASH 2. Audio: 2ch Audio DAC CS4334 for 2ch out only 3. Motor Driver: AM5888S/AT5669 4. Supported OPUs: SANYO DV342/502W
D
Notes:
C
1.Assembly Note (See comments in every schematics page, and also see the implementation field for each component)
B
B
TECOBEST TECHNOLOGY
TB_V862
A
A
Title
Version Document Size
Document Number
Date:
Saturday, May 28, 2005
Rev V1.2
5
4
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TRACK_S SLED_S SPINDLE_S FOCUS_S
TRACK_S SLED_S SPINDLE_S FOCUS_S
D
R128 R105 R104 R127
RFA
RFB
RFC
SPDL_SENSRFD
VC RFF SPDL_SENS+ RFE
DVD_LD CD_LD MD_DVD MD_CD
Notes: 1. Pin105 to pin203 of ZR36862/8 is 5V & 3.3V tolerant both. 2. ZR36868 is used for 6 or 8 CH audio out application. ZR36862 is used for 2 CH audio out application, and pin111/112 could be used as GPCIO.
R102 0R
51K 30K SLED_PWM 15K SPINDLE_PWM 43K FOCUS_PWM [51K]
FB101
DSPVCC18 DSPVCC33
IRRCV FPC_CLK FPC_DOUT
RFA
RFB
RFC
RFD
RFINN RFINP
IRRCV FPC_CLK FPC_DOUT
OUTSW INSW
L102
FB102
NM [220pF] C114 22pF
220Z
NM [2.7uH]
R113 OSCIN 75R
DRVSB
DUPRD1 DUPTD1
C113
+
DRVSB
TP1 TP1
CD/DVD
RD1 TD1 for HYPER_TERMINAL
CD/DVD
DUPRD0 DUPTD0
CLOSE OPEN
RD0 TD0
TP1 TP1
D
C122 100uF/16V
VDDAFE
VDDPWM
OUTSW INSW
C102 22nF
HOMESW
C101 27nF
CLOSE OPEN
for DOWN_LOAD
C105 1nF
DSPVCC33
+ C121 0.1uF C103 0.1uF
C104 1nF
220Z
R115 100K R101 20K 1%
1nF
C110
1nF
C109
C119 0.1uF
VDDPWM
C120 220uF/10V
Y101 27.000MHz
R112 220K
Assemble C113&L102 when Y101 assemble Third overtone Crystal
RF R129 75R VDDDAC
FB106
220Z
C115
DSPVCC33
OSCOUT
GPCIO[16]/SSCTXD GPCIO[47]/SSCCLK GPCIO[38]/DUPTD1 GPCIO[37]/DUPRD1 GPCIO[36]/DUPTD0 GPCIO[35]/DUPRD0 GPCIO[41]/PWMCO[0] IDGPCIO[4]/PWMCO[6] GPCIO[46]/PWMCO[5] VDDPWM GPCIO[45]/PWMCO[4] GNDPWM GPCIO[44]/PWMCO[3] GPCIO[43]/PWMCO[2] IDGPCIO[7]/SPINDLEPULSE IDGPCIO[6]/SLEDPULSE VDD-IP ICGPCIO[7] ICGPCIO[6] GNDP IDGPCIO[3] VDDP ICGPCIO[5] ICGPCIO[4] GNDC GPCIO[32] VDDC AGND1 AGNDREF DVD_LD CD_LD DVD_MD CD_MD RESOUT VBGAP VC F K E AGND J D H C AVDD SVDD B AVDD1 A G RFN RFP
MEMAD[19:0]
DSPVCC33
1 2
R125 4.7K
VGND
1 D101 LL4148
FS3 FS2 FS1
R116 10K
IAOUT0 R190
33R
AOUT0
SPDIF
R126 4.7K
RAMDAT8 RAMDAT9
PCLK RAMDQM
RAMDAT14 RAMDAT15
ABCLK ALRCLK
RAMDAT12 RAMDAT13
AMCLK
33R 33R
HSYNC VSYNC
RAMDAT10 RAMDAT11
33R
IABCLK R118 R103
2005/05/24
RAMADD4 RAMADD5 RAMADD6 RAMADD7 RAMADD8 RAMADD9
TBR Huang fu kuan HSYNC VSYNC
U102
AMCLK ABCLK ALRCLK AOUT0 SPDIF
SDRAM speed <=7ns
K4S161622C-TC/L70
B
MARK6
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
R122 NM [1K]
+
R114 100
JP102 NM [BOOTSEL1]
RAMDAT1 RAMDAT0
B
Q101 9014 C125 0.1uF
R117
R108 75R 1%
RESET
MUTEC
IAMCLK
R109 75R 1%
RAMDAT3 RAMDAT2
MEMCS0-
C108 10uF/16V RESET
FS3 FS2 FS1
R110 75R 1%
R120 10K
RAMDAT5 RAMDAT4
MEMRD-
R111 75R 1%
VGND
RAMDAT7 RAMDAT6
MEMDA0 MEMAD4 MEMRDMEMAD3 MEMAD2 MEMCS0MEMAD1 MEMAD0
MEMDA[15:0]
OSCIN OSCOUT VDDA RESET
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MEMDA2 MEMAD17 MEMDA9 MEMAD7 MEMDA1 MEMAD6 MEMDA8 MEMAD5
C
CVBS_G_Y
VSS A4 A5 A6 A7 A8 A9 NC CKE CLK UDQM NC VDDQ DQ8 DQ9 VSSQ DQ10 DQ11 VDDQ DQ12 DQ13 VSSQ DQ14 DQ15 VSS
MEMDA10 MEMAD18
Y_R_V CVBS_C
DSPVCC33
VDD A3 A2 A1 A0 A10/AP BA CS RAS CAS WE LDQM VDDQ DQ7 DQ6 VSSQ DQ5 DQ4 VDDQ DQ3 DQ2 VSSQ DQ1 DQ0 VDD
MEMDA11 MEMDA3 MEMAD19
C_B_U
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MEMWR-
R106 392R 1%
RAMADD3 RAMADD2 RAMADD1 RAMADD0 RAMADD10 RAMBA RAMCS0RAMRASRAMCASRAMWERAMDQM
MEMDA12 MEMWRMEMDA4
ZR36862
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
DSPVCC18
2
MEMAD10 MEMDA14 MEMAD9 MEMDA6 MEMAD8 MEMDA13 MEMDA5
GNDDACBS2 GNDDACP RSET C/B/U VDDDAC Y/R/V CVBS/C VDDDAC CVBS/G/Y Y/C GNDDACD GNDDACD GCLK XO VDDA RESET# GNDA GNDP VDD IDGPCIO[2] GPCIO[31] DJTCK/ICGPCIO[3]/VID[0] DJTDO/GPCIO[30]/VID[1] DJTDI/GPCIO[29]/VID[2] DJTMS/GPCIO[28]/VID[3] VDDC GNDC DJTCK2/ICETCK/GPCIO[27]/VID[4] DJTDO2/ICETDO/IDGPCIO[1]/VID[5] DJTDI2/ICETDI/ICGPCIO[2]/VID[6] DJTMS2/ICETMS/GPCIO[26]/VID[7] VDDP COSYNC/CJTMS/ICGPCIO[1]/VCLKx2 GNDP CJTDO/GPCIO[25]/HSYNC CJTDI/GPCIO[24]/VSYNC CJTCK/GPCIO[23]/AIN VDDP-A2 AMCLK GNDP-A2 ABCLK ALRCLK GPAIO AOUT[0] GPCIO[22]/AOUT[1] GPCIO[21]/AOUT[2] SPDIF IDGPCIO[0] ICGPCIO[0] GNDP CPUNMI/GPCIO[20] VDDP
220Z
+ C117 100uF/16V
1
C
SSCRXD/GPCIO[17] MEMCS#[1]/GPCIO[18] VDDP MEMAD[15] MEMAD[16] MEMAD[14] MEMAD[13] MEMAD[12]/PLLCFGA MEMDA[15] MEMAD[11]/PLLCFGP MEMDA[7] GNDP MEMAD[10] MEMDA[14] MEMAD[9] MEMDA[6] MEMAD[8] MEMDA[13] MEMDA[5] MEMAD[20]/GPCIO[19]/MEMCS#[2] VDDP MEMDA[12] MEMWR# MEMDA[4] VDDC MEMDA[11] MEMDA[3] MEMAD[19]/PLLSEL GNDC MEMDA[10] MEMAD[18] GNDP MEMDA[2] MEMAD[17] MEMDA[9] MEMAD[7] MEMDA[1] MEMAD[6] MEMDA[8] MEMAD[5] VDDP MEMDA[0] MEMAD[4] MEMRD# MEMAD[3] MEMAD[2] MEMCS#[0] MEMAD[1]/BOOTSEL2 MEMAD[0]/BOOTSEL1 GNDP VDD-IP VDDP
C116 1nF
3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
MEMAD15 MEMAD16 MEMAD14 MEMAD13 MEMAD12 MEMDA15 MEMAD11 MEMDA7
PH1
Use it to connect the shell of the crystal to ground. FB103 C178 0.1uF
2
FPC_STB
RAMADD[4] RAMADD[3] RAMADD[5] RAMADD[2] RAMADD[6] VDDP RAMADD[1] RAMADD[7] RAMADD[0] GNDP RAMADD[8] VDDC RAMADD[10] GNDC RAMADD[9] VDDP RAMADD[11] RAMCS#[0]/RAMBA1 RAMBA[0] GNDP RAMCS#[1] RAMRAS# RAMCAS# VDDP RAMWE# RAMDQM GNDPCLK PCLK VDDPCLK RAMDAT[8] GNDP RAMDAT[7] RAMDAT[9] RAMDAT[6] VDDP RAMDAT[10] RAMDAT[5] RAMDAT[11] GNDP RAMDAT[4] VDDC RAMDAT[12] GNDC RAMDAT[3] VDDP RAMDAT[13] RAMDAT[2] RAMDAT[14] GNDP RAMDAT[1] RAMDAT[15] RAMDAT[0]
FPC_STB
.
.
1
.
MARK5
1
1
U101A
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
22pF + C124 100uF/16V
C123 0.1uF
RAMDAT1 RAMDAT15 RAMDAT0
RAMDAT13 RAMDAT2 RAMDAT14
RAMDAT12
RAMDAT3
RAMDAT4
RAMDAT10 RAMDAT5 RAMDAT11
IPCLK
RAMDAT7 RAMDAT9 RAMDAT6
RAMDAT8
RAMWERAMDQM
RAMRASRAMCAS-
Short
RAMADD9
Open
RAMCS0RAMBA
JP102:
RAMADD8
Download
RAMADD10
Play
RAMADD1 RAMADD7 RAMADD0
MODE:
RAMADD4 RAMADD3 RAMADD5 RAMADD2 RAMADD6
DSPVCC33 + C158 47uF/16V
NMI
C152 0.1uF
C153 0.1uF
C154 0.1uF
R119 4.7K
R123 PCLK 56R C106 NM [5pF] DSPVCC33 DSPVCC33 C130 10nF
A
C131 10nF
C133 10nF
C134 10nF
C135 10nF
C136 10nF
C137 10nF
C138 10nF
C139 10nF
C140 10nF
A
PCB layout guy: please put these bypass capacitors close to main chip DSPVCC18 C146 10nF
C147 10nF
DSPVCC18 C148 10nF
TECOBEST TECHNOLOGY
C149 10nF
TB_V862 Title
ZR36862 & SDRAM
5
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OPUs Option:
SUPPORT OPUS:SANYO DV342/502W D
D
DV342(default) R221,R224=10R R294,R295=0R R202=2KR R127=43K R205=10K R207=2.2K
502W R221,R224=2.2R R294,R295=91R R202=0R R127=51K R205=3.3K R207=3.3K
C
C
B
B
TECOBEST TECHNOLOGY A
A
TB_V862 Title
ZR36862 & SDRAM
5
4
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Flash speed <= 70 nS. If plan to use 90ns Flash, it needs to be verified by s/w.
MEMDA[15:0]
MEMDA[15:0] D
4
MEMAD[19:0]
MEMAD[19:0]
D
TSOP_VCC
When using INTEL FLASH: R161=0 ohm, R160=NC When using SST FLASH: R160=0 ohm, R161=NC Default is SST mode.
TSOP_VCC MEMAD19 MEMAD15 MEMAD14 MEMAD13 MEMAD12 MEMAD11 MEMAD10 MEMAD9 MEMAD8
TSOP_VCC
C
R160
0R [NM] MEMWR-
RESET
RESET
R166 1R [NM]
U106
R161 TSOP_VCC
R168 4.7K
NM [0R]
MEMAD18 MEMAD17 MEMAD7 MEMAD6 MEMAD5 MEMAD4 MEMAD3 MEMAD2 MEMAD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
A16 BYTE# VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 A19 DQ5 DQ12 DQ4 VCC NC DQ11 NC DQ3 RY/BY# DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
DSPVCC33
MEMAD16 R167 NM [1R]
MEMDA15 MEMDA7 MEMDA14 MEMDA6 MEMDA13 MEMDA5 MEMDA12 MEMDA4 MEMDA11 MEMDA3 MEMDA10 MEMDA2 MEMDA9 MEMDA1 MEMDA8 MEMDA0 MEMRD-
C162 0.1uF
D5V
C541 0.1uF
C
Close to Pin37 & Pin47 of U106
FLASHCSMEMAD0
MEMWR-
MEMWR-
SST39VF800
B
B
MEMRD-
MEMRD-
MEMCS0-
MEMCS0-
TECOBEST TECHNOLOGY A
A
TB_V862 Title
FLASH & EEPROM Size Document Number Custom Date: 5
4
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RF33V
3
2
1
RF33V
2
RFA5V
+ C205 100uF/16V
C201 100uF/16V
C202 0.1uF
Q202 BT2907
C228 47uF/16V
R200 1 10K
DRVSB
D
2
D
R221 10R [2.2R]
3
C231 0.1uF +
R202 2K [0R]
Q204 BT2907
R222 220R
1
DVD_LD
3
RF33V
2
+
Q203 BT2907
C229 47uF/16V
Q205 BT2907
R201 1 10K
R223
1
220R
CD_LD
3
DVDLD
CDLD
RFE
PDIC_SEL
MD_DVD
VR_DVD
R210
0R
MD_CD 3V3_DRV
R294 0R [91R]
R295 0R [91R]
2
RFA5V
Q212 BT3904
Q210 S8550
DSPVCC33
1V8_DRV1
Q211 S8550
R553 0R
3
R208 3.3K
+ C209 47uF/16V PDIC_SEL
Not assemble for HOP1250/SPU3153/DPD20428 OPUs, and assemble for other OPUs
R235
R207 2.2K [3.3K]
DSPVCC18
R206 4.7K [NM]
C276 220uF/10V
3V3_FB
R220 4.3K 1%
1V8_FB + R218 12K 1% [NM]
CD/DVD
CD_DVD : CD=LOW DVD=HIGH
R205 10K [3.3K]
+
C275 220uF/10V
R238 10K 1%
FOR AM5888S, DEFAULT FOR AT5669,R219=0R,R218=NM
1
2
Q201 BT3904
DSPVCC33 R552 0R
NM
3
PDIC_SEL: CD=HIGH DVD=LOW
Default=SANYO HD62 []=502W
C
DSPVCC33
R219 20K 1% [0R]
1
R204 470R
RF33V
R551 0R
S8050/S8550 RF33V
Q213 BT3904
1
3
Close to OPU C204 0.1uF
1
DSPVCC18
RFD RFC
TACTTACT+ FACT+ FACT-
D205 1N4001 22
0R
2
R209
3
RF
D203 1N4001 VR_CD
2
VC RFF RFB RFA RF
3
VC 2.1V
33R
2E 1B 3C
R217 RFF
2
VREF
1
1
PW5V RFE
GND
GND
26
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
R224 10R [2.2R]
C208 0.1uF
25
C
GND-LD DVD-LD NC HFM MD CD-LD VR-DVD VR-CD NC E VCC VC(VREF) GND/PD F B A RF CD/DVD_SW D C TT+ F+ F-
C207 0.1uF
2
CN201 24Pin OPU connector
3
OPU_HFM
C212 1nF
R278 24K
Close to Motor driver
CN504
PW5V
VDDPWM
B
DRVSB
U202 AM5888S/AT5669 1 3V3_DRV
2
1V8_FB
3
R237 10K SLED_S
OUTSW CLOSE INSW OPEN
R246 0R
4 3V3_FB
5
CLOSE
6
OPEN
7
STBY
VINFC CFCERR1(OP2IN-)
BIAS
CFCERR2(OP2IN+)
VINTK
VINSL+
CTKERR1(OP1IN+)
VINSL-(OP2OUT)
CTKERR2(OP1IN-)
VOSL(CLOSE)
VINLD
VNFFC(OPEN)
PREGND
R265
28
26 25
C246 0.1uF R268 0R 1V8_DRV
0R
D5V
B
M5V RFA5V
HEADER 5
D5V
+ C501 220uF/16V
+
TRACK_S
+5V: +5V(+-2.5%)
C504 100uF/16V
R269 0R
23
SPINDLE_S
22
12
FACT-
13
FACT+
14
PGND(VCC2)
VOSL-
VOLD-
VOSL+
VOLD+
VOFC-
VOTK-
VOFC+
HOMESW MOT_SPDL+ MOT_SPDL-
VOTK+
. 20 1
SLED+
PGND(LOAD+)
MARK1
21
H1
19 18
MOT_SPDL-
17
MOT_SPDL+
16
TACT-
15
TACT+
A
3 2 1
RF33V
3 2 1
H2 4 5
4 5
3 2 1
3 2 1
MARK2 4 5
H1 R276 1K
R277 1K
R279 39R
.
11
VNFTK(OP1OUT)
4 5
1
10
SLED-
PVCC1(LOAD-)
MARK3 .
LOAD+
PVCC2
VCC
H2 1
10K
R507
MARK4 .
9
R254 SLED+ SLED-
220Z
24
R299 2K
C251 22nF
29 30
6 5 4 3 2 1
RFA5V
P+5V2FB502
1
CN203
C245 0.1uF
LOAD-
GND GND1
C244 100uF/16V
M5V
0R
M5V 8
RF33V
0R
R506
27
M5V
TRAY
R505 220Z
9 8 7 6
SLED_S
LOADLOAD+
1 2 3 4 5
R292 1K
P+5V1FB501
9 8 7 6
10K
CN204
1K 1%
9 8 7 6
FOCUS_S R236
R243 FOCUS_S 0R
1 2 3 4 5
9 8 7 6
RF33V
1K 1%
DRVSB
P+12V
R264
SPDL_SENS-
A
SPDL_SENS+
SLED & SPINDLE 1 D207
2 LL4148
2 D206
1 LL4148
R203 120R
C274 0.1uF
TECOBEST TECHNOLOGY
TB_V862 Title
OPU Connector & DRIVER & POWER
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Rev V1.2 Sheet 1
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NC
C320
R320
10R
R304 56R [NC]
R309 NC [10R]
SDATA SCLK LRCK MCLK CS4334 [CEI2711]
10uF/16V
10K
C321
3
MJM4558E U303A OP_12V
1nF 8 AOUTL VA VGND AOUTR
R324 1K
8 7 6 5
R332 20K
C330
R330
R325 2K
C332 120pF 6
C333
OP_BIAS
5
+
10K
MJM4558E U303B OP_12V
C303 47uF/16V
8
+ C304 0.1uF
Q312 BT3904
1
R334 1K
7 10uF/16V
LMAIN-OUT
A-RMAIN
R333 3.9K
A_ROUT
10uF/16V MUTE
LMAIN-OUT
3
1 2 3 4
D
C323 1
U301 AOUT0 ABCLK ALRCLK AMCLK
AOUT0 ABCLK ALRCLK AMCLK
2
4
NC
-
CEI2711
C322 120pF
R323 3.9K
A_LOUT
2
56R
A-LMAIN
D5V
C331 1nF
10uF/16V MUTE
RMAIN-OUT
RMAIN-OUT
2
CS4334
1
4
R309
-
R304
+
U301
2
R322 20K
DSPVCC33
Defult:CS4334
D
3
R335 2K
Q313 BT3904
1
C
3
C
R308
H: Mute MUTEC
R307
MUTEC
4.7K
3
P+12V
R310 3.3K
Q303 BT3904
1
+
C317 10uF/16V
2
47K R301 100R
Q304 2
P+12V D5V
BT3906 3
OP_12V 10K 1
R311 R302 10K
R312
+ C301 47uF/25V
C302 0.1uF
D301 1
OP_BIAS
B
100K LL4148 2
B
Q305 2
BT3906 3
MUTE
+ C306 0.1uF
+ C318 220uF/10V
1
C305 47uF/25V
2
R303 10K VGND
R314 2K
1
D302 LL4148
R313 47K
C319 47uF/25V
TECOBEST TECHNOLOGY
A
TB_V862 Title
Audio
5
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A
5
4
3
2
1
JR501
AV-4-405A 7
3
Y_R_V
Y_R_V
P+12V
D502 NM [BAT54S]
FS1: H=RGB L=CVBS
01
TV
10
16:9
2
Video Status C_B_U
C_B_U
4 D504 NM [BAT54S]
5
DSPVCC33
VGND
Q502 BT3904 [NM]
1
CVBS_G_Y
CVBS_G_Y
3
VGND
1
R514 150R [NM]
D503 NM [BAT54S]
2
FS3
RMAIN-OUT
D5V
2
CN501
6
RMAIN-OUT
2
Q501 BT3904 [NM]
1
FS2
D
AUDIO/TV/16:9 R510 1K [NM]
CVBS_G_Y
LMAIN-OUT RMAIN-OUT
8
DSPVCC33
VGND
1
Y_R_V C_B_U CVBS_G_Y SCART_SWITCH CVBS_OUT AUDIO/TV/16:9
VSYNC HSYNC
9 COAX_SPDIF
3
VSYNC HSYNC
12 11 10 9 8 7 6 5 4 3 2 1
R513 2K [NM]
1
SCART/VGA PORT
R509 2K [NM]
SCART CFG 4:3
3
FS2 FS3 00
3
D
2
Q503 BT3904 [NM] SCART_SWITCH
2
1
3 1
FS1
3
LMAIN-OUT
LMAIN-OUT
2
DSPVCC33
VGND
VGND
RGB Status
6
11pF 8
SCART 1.1uH
CVBS_OUT C521 160pF
D506 LL4148
D505 LL4148
7
Y_R_V
3
C_B_U
4
9
4
VGND
5
VGND
9
3
DSPVCC33
2
1 DSPVCC33
1
7
5
C511 150pF
1
L501
CVBS_C
2
CVBS_C
C
8
2
C520
1
JR504
[NM]
2
1K C
6
R516
VGND
CVBS & SVIDEO R501 10K CN503
R502 10K
R503 10K
R504 4.7K
D5V
1 2 3 4 5 6
R540
220R
R541 R542 R543
220R 220R 220R
IRRCV
D5V
FPC_CLK FPC_STB FPC_DOUT
R550 10R
VFD_PORT
C542 NM [100pF]
C535
JR505
+
B
3
100uF/16V
2
R548 68R OPT_SPDIF
KEY
1
D5V SPDIF
Q505
1
IN
C509 0.1uF
2
BT3904
VCC
OPTI
3
R549 33R SPDIF
B
GND
Close to Q505 R529 56R R544
C528 COAX_SPDIF
R530
62R
0.1uF
39R
C510 22pF
A
A
TECOBEST TECHNOLOGY
TB_V862 Title
AV output Size
Document Number
Date:
Saturday, May 28, 2005
Rev V1.2
5
4
3
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