Report_vlsi.docx

Introduction: Flip Flops or the data storage elements are almost an essential component of every sequential circuitry. Among various flip-flops, D flip-flop is commonly used. It captures the value of the D input at a particular predefined portion of the clock pulse (rising or falling edge of the clock) and its output is not affected at other parts of the clock. From the timing perspective, delay produced by flip-flops consumes a large part of the cycle time while the operating frequency increases. this paper investigates for delay and variability various D flip-flops. Selection of a flip-flop has a profound effect in providing more slack time for easier time budgeting and robust circuits in large systems. These reasons are increasing the interest of people in flip-flop design and analysis in recent time. In the present scenario there is an ever increasing demand for fast and robust devices. appropriate selection of elements at the very basic level, i.e., flip-flops is important to obtain the desired characteristics to benefit the bigger system. flip-flop also has a potential internal race condition between the two latches. This race can be exacerbated by skew between the clock and its complement caused by the delay of the inverter When 􀁋 falls, both the clock and its complement are momentarily low as shown in Figure 10.20(b), turning on the clocked pMOS transistors in both transmission gates. If the skew (i.e., inverter delay) is too large, the data can sneak through both latches on the falling clock edge, leading to incorrect operation.. When 􀁋 falls, both the clock and its complement are momentarily low

Working of C²MOS(single edge triggered) clocked CMOS D flip-flop. In this circuit also clock and inverted clock are used. It also consists of master and slave stages. Master follows the D-input when clock (C) = ‘1’. At that time slave is opaque but its regenerative feedback loop is transparent therefore the output at Q is stable. When clock= ‘0’ master is opaque but its regenerative feedback loop is transparent therefore storing the previous D-input. This time slave is on and this D-input stored by the master is reflected at the output and is maintained till another falling edge is encountered. Because each stage inverts, data passes through the nMOS stack of one latch and the pMOS of the other, so skew that turns on both clocked pMOS transistors is not a hazard. However, the flip-flop is still susceptible to failure from very slow edge rates that turn both transistors partially ON.

Why C²MOS? PROS • BETTER ISOLATION • NO RACE CONDITIONS • REDUCED XTOR COUNT VS. CMOS – CONS • MORE COMPLICATED • NEED 2-PHASE CLOCK

Dual edge triggered: Many researchers have proposed flip-flops that sample data on both the rising and falling

edges of the clock to save energy by operating at half the clock frequency. A major drawback is sensitivity to duty cycle variation that increases the skew of the falling clock edge. (The skew from rising edge to rising edge tends to be smaller than the skew from rising edge to falling edge because it involves the same transitions and thus matches better in the face of variation.) To first order, a dual edge-triggered (DET) flip-flop has half the clock frequency and twice the activity factor, so the energy consumed in the flip-flop is unchanged. However, the energy in the global clock distribution network is cut by a factor of two from the reduced frequency. In a well-designed system, the energy is usually dominated by the registers and not by the clock distribution. Moreover, the DET flipflop tends to have some overhead in area, delay, and energy. The extra skew caused by duty cycle variation further increases the sequencing overhead

II. TIMING CHARACTERISTICS OF FLIP FLOPS A common feature among clocked registers is the use of a common synchronizing signal, namely the clock signal, to control the timing of the data storage process. Data is successfully stored within a register if the following timing constraints between the input data signal and the clock signal are satisfied [4]:

A. Setup time This determines the minimum time that the value of the data signal should be valid before the arrival of a latching clock signal figure 1 (a).

B. Hold time That specifies the minimum time that the data signal should remain at a constant value after data storage is enabled by the clock signal figure 1(b). Furthermore, the propagation delay of the output signal of a register is determined in terms of the temporal relationship between the input data and clock signal:

C. Propagation delay Is defined as the delay between a latching event of the clock signal and the time of latched data is available at the output Q/QN of a register figure 1 (c)

D.

C²MOS A C2MOS register with CLK-CLK clocking is insensitive to overlap, as long as the rise and fall times of the clock edges are sufficiently small

C2MOS latch is insensitive to clock overlaps because those overlaps activate either the pull-up or the pull-down networks of the latches, but never both of them simultaneously. If the rise and fall times of the clock are sufficiently slow, however, there exists a time slot where both the NMOS and PMOS transistors are conducting. This creates a path between input and output that can destroy the state of the circuit. Simulations have shown that the circuit operates correctly as long as

the clock rise time (or fall time) is smaller than approximately five times the propagationdelay of the register. The impact of the rise and fall times is illustrated in Figure 7.28, which plots the simulated transient response of a C2MOS D FF for clock slopes of respectively 0.1 and 3 nsec. For slow clocks, the potential for a race condition exists

Working of our circuit: When clock is high, the positive latch composed of transistors M1-M4 is sampling the inverted D input on node X. Node Y is held stable, since devices M9 and M10 are turned off. On the falling edge of the clock, the top slave latch M5-M8 turns on, and drives the inverted value of X to the Q output. During the low phase, the bottom master latch (M1, M4, M9, M10) is turned on, sampling the inverted D input on node Y. Note that the devices M1 and M4 are reused, reducing the load on the D input. On the rising edge, the bottom slave latch conducts, and drives the inverted version of Y on node Q. Data hence changes on both edges. Note that the slave latches operate in a complementary fashion — this is, only one of them is turned on during each phase of the clock.