Publication 2

Digital Circuit Design for Generation of 155.52 Mbps, LVPECL Data for Optical Inter-Satellite Link Kaushik Nagaraj, Abhishek S. M., Adawaita Goswami, A. S. Laxmi Prasad

Indian Space Research Organization (ISRO) Laboratory for Electro-Optics Systems (LEOS) Bangalore, India. Abstract. Optical Inter-satellite links can be established between two Geo-stationary (GEO) satellites, between a Low Earth Orbiting (LEO) satellite and a GEO, or between a deep space probe and a GEO or LEO. The use of optical signals as information carriers in satellite communication system becomes attractive because of their ability to provide very high-speed communications with data rates in the order of Gbps (Giga bit per second) without any mutual interference. Data generated on the LEO satellite needs to be converted to high data rates in order for it to be compatible with the optical devices being used for communication. Currently a laboratory level demonstration of inter satellite link at 1.25Gbps is under progress at LEOS. Data at this high speed needs to be generated and fed to this demonstration model at transmitter end. The current paper gives the circuit design issues related to the conversion of the data coming from a data source to a higher data rate of 155.52 Mbps. Also, the data logic level needs to be converted from TTL to LVPECL (Low Voltage Positive Emitter Coupled Logic). This is fed as input to one of the channels of a 16 channel multiplexer which gives out a data rate of 2.48 Gbps. This, in turn, is fed as input to the Laser Drivers for the necessary conversion of digital data to laser pulses.

1 Introduction Applications of Low Earth Orbit (LEO) and geostationary earth orbit (GEO) satellites are increasing day by day. Over the last decade number of transponders in GEO satellites and number of instruments and their resolution in (LEO) satellites has increased resulting in enormous increase in data generation in such applications. The huge volumes of data need to be transmitted in short time and in some applications immediate transmission is required for instant monitoring. However, the visibility of LEO satellite to ground is limited. Inter Satellite communication between a remote sensing satellite in the LEO and a communication satellite in the GEO can be used to overcome this problem. The data from the LEO satellite can be transferred to the GEO satellite which is constantly visible to the ground. Subsequently, the GEO satellite relays the data to ground station. This inter satellite link can be RF or optical. In optical inter satellite link (OISL) [1, 2, 3, 4] data is transmitted using modulated optical signal with starting and ending information bursts. The advantages of an inter satellite optical communication system as compared to RF link in free space are: 1) Smaller size and weight of the overall system 2) Reduced transmitter power 3) Increased bandwidth 4) Secure communication (narrow beam with low probability of intercept and negligible interlink interference) 5) Jam resistance (small receive FOV) 6) Provides base forever expanding space activities. Optical Inter Satellite links can be established between two Geo-stationary (GEO) satellites, between a Low Earth Orbiting (LEO) satellite and a GEO, or between a deep space probe and a GEO or LEO. Link establishment, link maintenance, and data transfer are the three critical basic functions of any optical inter-satellite communication system. Link establishment and maintenance is critical task because of the low laser beam divergence, the large distance and the vibration of the satellites [5] caused by satellite internal subsystems (such as thruster firing and solar array drive mechanism). LEOS has developed a laboratory concept model operating at 1.25Gbps data rate and efforts are in progress towards the development of space born Optical Inter-satellite communication system.

The block diagram of the Optical Inter-Satellite System is shown in Figure 1. The data source is assumed to be a computer and this data needs to be transmitted from the Transmitter end to the Receiver end as shown in the diagram. The data from the computer is converted to a data rate of 155.52 Mbps which is fed as the input at one of the channels of the 16-channel multiplexer. The output data rate of the multiplexer is 155.52*16=2.48Gbps. This data rate is sufficient to be given as the input to the Laser Drivers which bring about the conversion of the digital data to the laser pulses. These are than transmitted at the transmitter end into free space with the help of a Transmitter Antenna. The Receiver Antenna receives this data and converts it to the digital data with the help of a detector. The data rate is 2.48 Gbps which is given as the input to the Demultiplexer which outputs the data at each of its 16 output channels at a data rate of 155.52 Mbps. This data needs to be read by the computer at the receiver end and displayed in the machine readable form.

LASER DIODE

TRANSMITTER ANTENNA (TELESCOPE)

RECEIVER ANTENNA (TELESCOPE)

Detector (APD)

LASER DRIVER

MULTIPLEXER

PC

DEMULTIPLEXE R

PC

Fig. 1. Block Diagram of the OISL System

This paper discusses a method to bring about the data rate conversion from the rate at which the data is outputted from the computer to 155.52 Mbps at the Transmitter end taking into consideration various other factors that are necessary for the conversion. The multiplexer requires an input data rate of 155.52 Mbps and the input data to be in Low Voltage Positive Emitter Coupled Logic (LVPECL). The multiplexer circuit has already been designed and tested at LEOS. It is important to interface the computer to this circuit by making sure that all the input specifications of the multiplexer are met. This scheme is explained in Figure 2. The data from the computer is assumed to be any file such as PDF, jpeg, bmp, word etc. The data from the computer is read through 8 channels of the PCI bus and given as input to a Digital Input/Output Card (DIO) which brings about the data rate conversion to 19.44 Mbps. The output of the DIO Card, which is at the data rate of 19.44 Mbps on each of the 8 channels, is given to a TTL-to-ECL Translator to convert the data to ECL. This 8 channel data is fed to a Parallel-In-Serial-Out (PISO) Shift Register which gives an output data rate of 155.52 Mbps. The reason for converting the data rate, initially, to 19.44Mbps, and eventually, to 155.52 Mbps rather than converting directly to 155.52 Mbps is that during the initial stages data being handled is TTL. And TTL cannot support data rates higher than 20 Mbps. Thus, it is important to delay the conversion to a data rate higher than 20 Mbps as long as the data being handled is TTL. The purpose of the counter is to drive the clock inputs of each if these blocks. The final data output, which is ECL at the rate of 155.52 Mbps is converted to LVPECL with the help of pull-up resistors and capacitors.

Fig. 2. Block Diagram of Circuit

2 HARDWARE DESCRIPTION The multiplexer card has an on-board clock course which is 155.52 MHz crystal, which is being tapped to give as the clock input to each of the block mentioned above. Some of the blocks require a clock input of 155.52/8=19.44 Mbps which can be brought about with the help of the 4 bit counter.

2.1 DIO CARD The data from the computer is read through the PCI Bus at the rate of 19.44 Mbps; TTL logic level. The rate at which the data is read from the PCI bus can be controlled by programming the DIO card by software. The DIO has a provision to accept the clock from an external source as well as from its in-built clock. The DIO has to be configured to operate in the external clock mode. The clock input to the DIO is 19.44 Mbps. This is the rate at which the 8 channel parallel data reaches the PISO Shift register, thereby, giving a serial data at the rate of 19.44 * 8 = 155.52 Mbps at the output of the PISO. The DIO has an in-built buffer that aids in bringing about the data rate conversion. The input to the DIO is an 8 channel parallel data from the PCI bus. This data is converted to an 8 channel parallel output data at the date rate of 19.44 Mbps.

2.2 CIRCUIT Emitter Coupled Logic (ECL) is a non-saturating logic family capable of high speeds with low rise and fall times. This makes it capable of high switching speeds, and hence, ECL is an ideal choice for high-speed serial communication. The data from the DIO needs to be converted to ECL logic level as TTL cannot support high data rates. The conversion can be brought about with the help of an 8-bit TTL-to-ECL Translator. The clock input to the Translator is 19.44 MHz because the input and the output are required to be driven at the data rate of 19.44 Mbps. The output of the translator is ECL logic level and data has a rate of 19.44 Mbps. It is now possible to reach higher data rates since the data now being handled is ECL. This is given as input to an 8-bit Parallel-in Serial-out Shift Register. The Shift Register has a clock input of 155.52 MHz which is the clock tapped from the multiplexer card. The data is given out serially from the shift register at the rate of the input clock frequency which is 155.52 Mbps. The circuit shown in figure 3 contains the Translator and PISO Shift Register along with the termination circuitry.

Fig. 3. Circuit diagram of Translator and PISO Shift Register A 4-bit ECL counter is made to operate in the count-down mode so that it can be used as a clock divider. The output of the counter is C0, C1, C2, and C3. C3 is left unused since the tapped clock needs to be divided by 8 and not by 16. The tapped clock from the multiplexer card is given as input to this counter which divides it by 8 to provide us with a clock rate of 19.44 MHz. This clock is used as clock input to the DIO card and the translator. The counter is also used to set-reset the select lines required for Parallel load and serial shift in the shift register.

Fig. 4. Four bit Counter generating outputs C0, C1, C2.

Fig. 5. Circuit to generate the Handshake signal to DIO

The ECL data at the rate of 155.52 Mbps is converted to LVPECL using pull-up resistance network. A fanout buffer has been used to assist in pulse shaping for the clock pulses; i.e., to reconstruct certain pulses that may have become distorted. The distortion is likely to occur because the clock is being tapped from an external source and there is no direct contact between the two. A 6-bit ECL-to-TTL Translator has been used to generate the handshake signal for the DIO card. Only one channel of this translator is utilized. The input to this translator is C2 output of the counter and a signal labeled as REQ is obtained. This REQ signal serves as a handshake between the DIO and the translator.

2.3 TERMINATION OF ECL DEVICES ECL outputs are bipolar junction transistors (BJT) configured as emitter followers [9].To maintain their fast switching rates, these emitter followers should operate in the forward active region at all times, requiring them to source current at all times [9]. ECL inputs have large impedance (typically around 75 kΩ) that does not allow for the necessary current sourcing by the ECL output [9]. Instead, this current sourcing is achieved by terminating the ECL output through a resistor, Rt, to a voltage, Vtt, such that Vtt = Vcc – 2.0V Rt = Z0 Where Z0 is the characteristic impedance of the transmission line connecting the ECL output to Rt [9]. ECL outputs are typically 50Ω, thus the terminating resistor as well as the transmission line’s characteristic should be approximately 50Ω [9].

2.4 PROPAGATION DELAY Propagation delay is inherent property of all ICs and circuits. It means that output of a circuit changes in accordance with input after small time delay. This delay is called propagation delay as input takes time to propagate to output. Main time delays that has to considered during design are as 1. Propagation delay 2. Setup time of IC 3. Hold time of IC Setup time of IC is the minimum time required for input to be stable before clock pulse is given to IC so as input propagates to output. Hold time of IC is the minimum time required for input to be stable after clock pulse is given to IC so as input propagates to output. Propagation delay varies with logic used in circuit. For example, propagation

delay is maximum for CMOS logic and minimum for ECL logic. This difference in propagation delay is mainly because of operating point of transistors in each logic. In ECL logic transistors are operated in active region and transistors should be a source of current all the time. Thus ECL logic is a high power network and an excess of heat is produced. Proper heat sink should be provided else due to change in temperature there will be change in propagation delay. Input impedance of ECL circuits is of order of 75kohms, due to which transistors cannot source current for all the time. Thus circuit terminations are required at every interconnection of ICs. Timing diagram considering all propagation delay, setup and hold time is shown in figure 3. While designing the circuit propagation delay is the main criterion in the design because margin for error is very small, in order of nano seconds. Maximum and minimum propagation delay for different temperatures should be considered so that the circuit works with no flaws. The circuit will be immune to constant temperature change. And the circuit designed can work at any extremes of propagation delays and temperature.

2.5 TIMING DIAGRAM The Timing Diagram for the circuit is given in figure 6. In the diagram, clk and clkb are the main signals that are stable and are tapped from the multiplexer. These are used to generate many other signals and also to drive all ICs directly or indirectly. clk and clkb are not enough to generate all signals required to drive all ICs, hence a 4 bit counter is driven by clk to generate, divide by 2, 4, 8 and 16 clk. These supplement signals along with clk and clkb are used to generate select lines and signals for other ICs like translator and shift register.

Fig.6. Timing Diagram of the Circuit Timing diagram shown is the actual behavior of the circuit and this is how circuit is designed to work. In the diagram, construction of circuit is done by taking into account of all maximum and minimum propagation delay of all ICs. Allowances are provided in timing diagram for varying propagation delay. Shift register is used to convert serial data to parallel 8 bit data. Shift register is driven by clkb. Data is shifted left after every clkb pulse. Parallel data is read by translator after 8 pulses. Data is translated to TTL logic by the translator after 8 pulses and this is synchronized by generating a suitable select line. This is given by C2 output of

counter. C2 output of counter is given as handshake signal to DIO card so as to enable DIO card to receive the data from the interface card. This is given through a translator. Setup and hold time of minimum 20 n sec is required along with 50 n sec of handshake signal.

3 SOFTWARE INVOLVED The DIO card is software programmable and needs to be programmed to control the data input/output. The ports on the DIO can be configured as all input ports or all output ports or some as input ports and some as output ports. There will be specific registers for this purpose. It is necessary to program 8 ports as input and 8 ports as output. Also, there is a need to generate the necessary control signals and the handshake signals so that the output is at the data rate of 19.44 Mbps. The data needs to be read into the DIO when data is ready, given, the previous data has been sent out through the output ports. Another possibility is the occurrence of the overflow of the buffer in the DIO resulting in the reading of wrong data at the output ports. When the input data rate is less than the output data rate, there is a possibility of buffer underflow. So, to prevent this, handshake signals must be generated between the DIO card and the circuit. DIO has many modes of operation. The modes selected should be operable at 19.44 MHz. Data from the computer can be of many format types. All these formats have certain headers that contain information pertaining to the data it contains. The information from these headers must be extracted and used for proper coding of data. This is once again done by software.

4 CONCLUSION A digital circuit has been designed to bring about an interface between the computer and the laser drivers at the Transmitter end for Optical Inter-Satellite Link. The various high speed circuit design issues have been highlighted and ways to counter some of these problems have also been briefly discussed. The development activity at LEOS has also been briefly discussed.

REFERENCES [1] R.B Deadrick and W.F Deckelman, “Laser Cross Link Subsystem- A Overview”, SPI Vol.1635,225-235 (1992). [2] Christoph Noldeke, “Survey of Optical Communication System Technology for Free-Space Transmission”, SPIE Vol.1635, 200-212 (1992) [3] J. E. Mulholland and S. A. Cadogan, “Intersatellite laser crosslink,” IEEE Trans. Aerospace and Electron. Sys., vol. 32, no. 3, pp. 1011 – 1020, Jul.1996. [4] W.R. Leeb, “Prospects of laser communications in space,” in Selected Papers on Free-Space Laser Communications II, D.L. Begley, Ed.,vol. MS100 of SPIE Milestone series, pp. 64–74. SPIE, May 1984. [5] Ryan J. Pirkl, “ECL Design Guide”, Propagation Group, Georgia Institute of Technology, May 18, 2005. [6] Paul Shockman, “Termination of ECL Devices with EF (Emitter Follower)Output Structure, ON Semiconductor Logic Applications Engineering. [7] Ranjith.R, Adwaita Goswami, P.Raghu Babu and A.S.Laxmiprasad, “Technology and Design needs for Optical Inter-Satellite Link (OISL)”. [8] Laxmiprasad A.S., R.Ranjith, P.Raghubabu, J.A.Kamalakar, “Optical Inter-Satellite Link (OISL) for Remote Sensing Satellites” in SPIE Proceedings on Asia Pacific Remote Sensing, Panaji, Goa, India, November – 2006. [9] ON Semiconductor. (Aug 2002). “Termination of ECL Logic Devices”. Application Note