Project File

FET CHARACTERSTICS TRAINER KIT Introduction The Field Effect Transistor is a unipolar device that has very similar properties to those of the Bipolar Transistor i.e. high efficiency, instant operation, robust and cheap and they can be used in most circuit applications that use the equivalent Bipolar Junction Transistors (BJT). They can be made much smaller than an equivalent BJT transistor and along with their low power consumption and dissipation make them ideal for use in integrated circuits such as the CMOS range of chips. Field effect transistor (FET) relies on an electric field to control the shape and hence the conductivity of a channel of one type of charge carrier in a semiconductor material. FET are sometimes called unipolar transistors to contrast their single carrier type operation with the dual carrier type operation of bipolar junction transistors (BJT). The concept of the FET predates the BJT, though it was not physically implemented until after BJT due to the limitations of semiconductor materials and the relative ease of manufacturing BJT compared to FET. The Field Effect Transistor has one major benefit over its standard bipolar junction transistor cousins, in that their input impedance is very high (Thousands of Ohms) making them very sensitive to input signals, but this high sensitivity also means that they can be easily damaged by static electricity.This trainer kit is also determine the characterstics of FET and show that how FET works and their principles. 2

This trainer kit is mainly used in labs for practicals and we have to draw the characterstics between drain current and drain voltage at that time when gate voltage are constant. Now we also draw the characterstics between drain current and gate bias circuit for making a drain voltage constant. By drawing this characterstics we will measure the two components such as saturation drain current (IDSS) and peak voltage (Vp). Saturation drain

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current shows that the circuit is in saturation region and they take constant current and if we increase the voltage then current doesn’t effect due to the saturation region the current still constant and we also measure the peak voltage this voltage shows that the trainer kit is operated on its peak value. Now if we exceed more voltage then peak voltage doesn’t effect. This kit is very easily understandable and performing for practical due to the use of FET device. FET is also called as voltage cntrol device because The Field Effect Transistor or simply FET however, use the voltage that is applied to their input terminal to control the output current, since their operation relies on the electric field (hence the name field effect) generated by the input voltage. This then makes the Field Effect Transistor a Voltage operated device. The FET has an extremely high input gate resistance and as such a easily damaged by static electricity if not carefully protected. FET are ideal for use as electronic switches or common source amplifiers as their power consumption is very small.

FET 3

FET can be constructed from a number of semiconductors, silicon being by far the most common. Mostly FET are made with conventional bulk semiconductor processing techniques using the single crystal semiconductor wafer as the active region or channel. Among the more unusual body materials are amorphous silicon, polycrystalline silicon or other amorphous semiconductors in thin film transistors or organic field effect transistors that are based on organic semiconductors and often apply organic gate insulators and electrodes. Field Effect Transistor is a unipolar device as well as Voltage control device . FET have a gate, drain, and source terminal that correspond roughly to the base, collector and emitter of BJT. This gate permits electrons to flow through or blocks their passage by creating or eliminating a channel between the source and drain. Electrons flow from the source terminal towards the drain terminal if influenced by an applied

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voltage. The body simply refers to the bulk of the semiconductor in which the gate, source and drain. The channel of a FET is doped to produce either an N type semiconductor or a P type semiconductor. The drain and source may be doped of opposite type to the channel in the case of depletion mode FET or doped of similar type to the channel as in enhancement mode FET. Field effect transistors are also distinguished by the method of insulation between channel and gate. Fig 1 shows the diagram of FET which is mentioned below and also see their parts.

Fig1. Field Effect Transistor

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Current Control

The current control terminal is called the gate. Remember that the base

terminal of a bipolar transistor passes a small amount of current. The gate on the FET passes virtually no current when driven with D.C. When driving the gate with high frequency pulsed D.C. or A.C. there may be a small amount of current flow. The transistors turn on voltage varies from one FET to another but is approximately 3.3 volts with respect to the source. When FET are used in the audio output section of a Kit the Vgs (voltage from gate to source) is rarely higher than 3.5 volts. When FET are used in switching power supplies the Vgs is usually much higher (10 to 15 volts). When the gate voltage is above approximately 5 volts, it becomes more efficient (which means less voltage drop across the FET and therefore less power

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dissipation). FET are commonly used because they are easier to drive in high current applications (such as the switching power supplies found in car audio amplifiers). If a bipolar transistor is used, a fraction of the collector emitter current must flow through the base junction. In high current situations where there is significant collector emitter current, the base current may be significant. FETs can be driven by very little current (compared to the bipolar transistors). The only current that flows from the drive circuit is the current that flows due to the capacitance. As you already know that when DC is applied to a capacitor there is an initial surge then the current flow stops. When the gate of an FET is driven with a high frequency signal, the drive circuit essentially sees only a small value capacitor. For low to intermediate frequencies, the drive circuit has to deliver little current. At very high frequencies or when many FET are being driven, the drive circuit must be able to deliver more current. The gate of a FET has some capacitance which means that it will hold a charge (retain voltage). If the gate voltage is not discharged the FET will continue to conduct current. This doesn't mean you can charge it and expect the FET to continue to conduct indefinitely but it will continue to conduct until the voltage on the gate is below the threshold voltage. You can make sure it turns off if you connect a pulldown resistor between the gate and source. 5

Gate Current

As with bipolar transistors, each FET is designed to safely pass a

specified amount of current. If the temperature of the FET is above 25c (approx. 77 degrees farenheit), the transistor's safe current carrying capabilities will be reduced. The safe operating area

continues to be

diminished as the temperature rises. As the temperature approaches the maximum safe operating temperature, the transistor's current rating approaches zero.

Gate Voltage

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As you already know that the FET is controlled by its gate voltage. For this FET the maximum safe gate voltage is ±20 volts. If more than 20 volts is applied to the gate (referenced to the source) it will destroy the transistor. The transistor will be damaged because the voltage will arc through the insulator that separates the gate from the drain and source part of the FET.

Drain Source Voltage FET will be damaged if its specified maximum drain and source voltage is exceeded. You can obtain a data sheet from the manufacturer. The data sheet will give you all of the information you need to use it. 6

FET Methodlogy

The Methodlogy which is used for making a FET as shown. (a) Get

the best hardware you can but it’s never good enough.

(b) Create

an As Fit Model Best possible fit to the hardware but it’s

never good enough. (c)

Adjust the model to match the design manual nominal device. This is the centered or nominal model.

(d) Add

tolerance to some model parameters to represent the extreme

variation expected in manufacturing. 7

Mass Action Law

The product of the concentration of the reaction partners with all

concentrations always taken to the power of their stoichiometric factors equals a constant K which has a numerical value that depends on the temperature and pressure. The constant K is called reaction constant. There can be any number of particles reacting or resulting from the reaction and we always bring the results of the reaction (example H2O) to the right side of the equation and assign a negative value to its stoichiometric factors the reaction products thus end up in the denominator of the concentration products. We mostly use integers for the stoichiometric factors but that is not derigeur. An alternative way of writing the reaction equations that

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shows the minus sign more clearly. The mass action law is deceptively simple it is however not so trivial to derive it from thermodynamics including a value for the reaction constant, and it is often quite tricky to use for real cases. 8

Intrinsic Semiconductor

An intrinsic semiconductor also called an undoped semiconductor or i

type semiconductor is a pure semiconductor without any significant dopant species present. The number of charge carriers is therefore determined by the properties of the material itself instead of the amount of impurities. In intrinsic semiconductors the number of excited electrons and the number of holes are equal n = p. The conductivity of intrinsic semiconductors can be due to crystal defects or to thermal excitation. In an intrinsic semiconductor the number of electrons in the conduction band is equal to the number of holes in the valence band. An indirect gap intrinsic semiconductor is one where the maximum energy of the valence band occurs at a different k (kspace wave vector) than the minimum energy of the conduction band. Examples include silicon and germanium. A direct gap intrinsic semiconductor is one where the maximum energy of the valence band occurs at the same k as the minimum energy of the conduction band. Examples include gallium arsenide.

Extrinsic Semiconductor 9

An extrinsic semiconductor is a semiconductor that has been doped, that is into which a doping agent has been introduced, giving it different electrical properties than the intrinsic (pure) semiconductor.Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the semiconductor at thermal equilibrium. Dominant carrier concentrations in an extrinsic semiconductor classify it as either an n type or p type semiconductor. The electrical

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properties of extrinsic semiconductors make them essential components of many electronic devices. 10

Semiconductor doping

Semiconductor doping is the process that changes an intrinsic

semiconductor to an extrinsic semiconductor. During doping, impurity atoms are introduced to an intrinsic semiconductor. Impurity atoms are atoms of a different element than the atoms of the intrinsic semiconductor. Impurity atoms act as either donors or acceptors to the intrinsic semiconductor changing the electron and hole concentrations of the semiconductor. Impurity atoms are classified as donor or acceptor atoms based on the effect they have on the intrinsic semiconductor. Donor impurity atoms have more valence electrons than the atoms they replace in the intrinsic semiconductor lattice. Donor impurities donate their extra valence electrons to a semiconductor conduction band providing excess electrons to the intrinsic semiconductor. Excess electrons increase the electron carrier concentration (n0) of the semiconductor making it n type. Acceptor impurity atoms have less valence electrons than the atoms they replace in the intrinsic semiconductor. They accept electrons from the semiconductor valence band. This provides excess holes to the intrinsic semiconductor. Excess holes increase the hole carrier concentration (p0) of the semiconductor, creating a p type semiconductor. Semiconductor and dopant atoms are defined by the column of the periodic table of elements they fall in. The column definition of the semiconductor determines how many valence electrons its atoms have and whether dopant atoms act as the semiconductor's donors or acceptors. 11

N type semiconductors

Band structure of an n type semiconductor. Dark circles in the

conduction band are electrons and light circles in the valence band are holes. The image shows that the electrons are the majority charge

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carrier.Extrinsic semiconductors with a larger electron concentration than hole concentration are known as n type semiconductors. The phrase n-type comes from the negative charge of the electron. In n type semiconductors, electrons are the majority carriers and holes are the minority carriers. N type semiconductors are created by doping an intrinsic semiconductor with donor impurities. In an n type semiconductor the Fermi energy level is greater than the that of the intrinsic semiconductor and lies closer to the conduction band than the valence band.

P type semiconductors

Band structure of a p type semiconductor. Dark circles in the conduction

band are electrons and light circles in the valence band are holes. The image shows that the holes are the majority charge carrier. As opposed to n type semiconductors, p type semiconductors have a larger hole concentration than electron concentration. The phrase p type refers to the positive charge of the hole. In p type semiconductors, holes are the majority carriers and electrons are the minority carriers. P type semiconductors are created by doping an intrinsic semiconductor with acceptor impurities. P type semiconductors have Fermi energy levels below the intrinsic Fermi energy level. The Fermi energy level lies closer to the valence band than the conduction band in a p type semiconductor.

Conductivity 12

If a body has more or fewer electrons than are required to balance the positive charge of the nuclei then that object has a net electric charge. When there is an excess of electrons the object is said to be negatively charged. When there are fewer electrons than the number of protons in nuclei the object is said to be positively charged. When the number of electrons and the number of protons are equal, their charges cancel each other and the object is said to be electrically neutral. A macroscopic body can develop an electric charge through rubbing, by the triboelectric effect. Independent

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electrons moving in vacuum are termed free electrons. Electrons in metals also behave as if they were free. In reality the particles that are commonly termed electrons in metals and other solids are quasi electrons, quasi particles which has the same electrical charge spin and magnetic moment as real electrons but may have a different mass. When free electrons both in vacuum and metals move they produce a net flow of charge called an electric current which generates a magnetic field. Likewise a current can be created by a changing magnetic field. These interactions are described mathematically by Maxwell's equations.At a given temperature, each material has an electrical conductivity that determines the value of electric current when an electric potential is applied. Examples of good conductors include metals such as copper and gold, whereas glass and Teflon are poor conductors. In any dielectric material, the electrons remain bound to their respective atoms and the material behaves as an insulator. 13

Most semiconductors have a variable level of conductivity that lies between the extremes of conduction and insulation. On the other hand metals have an electronic band structure containing partially filled electronic bands. The presence of such bands allows electrons in metals to behave as if they were free or delocalized electrons. These electrons are not associated with specific atoms so when an electric field is applied they are free to move like a gas (called Fermi gas) through the material much like free electrons.Because of collisions between electrons and atoms the drift velocity of electrons in a conductor is on the order of millimeters per second. However the speed at which a change of current at one point in the material causes changes in currents in other parts of the material

the

velocity of propagation is typically about 75% of light speed. This occurs because electrical signals propagate as a wave, with the velocity dependent on the dielectric constant of the material. Metals make relatively good

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conductors of heat primarily because the delocalized electrons are free to transport thermal energy between atoms. However unlike electrical conductivity, the thermal conductivity of a metal is nearly independent of temperature. This is expressed mathematically by the Wiedemann Franz law which states that the ratio of thermal conductivity to the electrical conductivity is proportional to the temperature. The thermal disorder in the metallic lattice increases the electrical resistivity of the material producing a temperature dependence for electrical current. When cooled below a point called the critical temperature materials can undergo a phase transition in which they lose all resistivity to electrical current in a process known as super conductivity. In BCS theory this behavior is modeled by pairs of electrons entering a quantum state known as a Bose Einstein condensate. These Cooper pairs have their motion coupled to nearby matter via lattice vibrations called phonons, thereby avoiding the collisions with atoms that normally create electrical resistance. Cooper pairs have a radius of roughly 100 nm, so they can overlap each other.However the mechanism by which higher temperature superconductors operate remains uncertain. Electrons inside conducting solids which are quasi particles themselves when tightly confined at temperatures close to absolute zero behave as though they had split into two other quasi particles spinons and holons. The former carries spin and magnetic moment while the latter electrical charge. Fast switching speeds because electrons can start to flow from drain to source as soon as the channel opens.

Bloch Boltzmann theory 14

The long mean free path of electrons in metals is the key to formulating a theory. In a perfect crystal the quantum description of electrons as particle wave entities is similar to the idea of electromagneticwaves confined in a resonant cavity. The wavelengths have to fit the dimensions of the cavity

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which causes quantization of wavelength λ. The individual quantum states or orbitals are labeled by their wavevectors k = 2π/λ. The orbital labeled by k has an energy ε(k) and is pictured as a wave oscillating with a space and time dependence given approximately by cos [kx − ε(k)t] like a traveling electromagneticwave with frequency ω(k)=ε(k). A wave packet built from such orbitals moves with velocity. It has to be measured by photoemission or computed using band theory and varies from metal to metal. The wave packets in real metals do not remain phase coherent over the whole sample only over the distance between collisions. Provided this distance is longer than a wavelength the wavelength and wavevector remain meaningful quantities which can be used to build a theory. Bloch’s theory starts from the recognition of Bloch orbitals with wavevectors k. It then adopts from Boltzmann the notion of the distribution F(k) which gives the probability that the state k is occupied. Because of the Pauli principle, this probability cannot exceed 2 (one for spin up and one for spin down). For states of low energy [ε(k) far below the Fermi level εF] the occupancy is very close to 2 and for states of high energy [ε(k) far above the Fermi level εF] the occupancy is very close to 0. In thermal equilibrium the occupancy F(k) is equal to the Fermi Dirac function. The conductivity is calculated by summing the velocities of the occupied states When the field E is zero the distribution F(k) is f(k) which has j = 0 because states with positive and negative velocities v(k) are equally populated. The effect of the field E is to cause the k vectors of the occupied states to change according to Bloch’s law. This is the quantum version Newtonian acceleration by the electric force using de Broglie’s momentum k of a quantumwave. The acceleration is continuously resisted by scattering. Therefore the total shift of the typical k vector where τ is the time between collisions. The last part of integration by parts after substituting the expression and can be interpreted as electron density times reciprocal effective mass.

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The Bloch theory recovers a result proposed on classical grounds by Paul Drude shortly after the discovery of the electron, namely σ = ne2τ /m. However, the interpretation is quite different. A proper quantum theory for the scattering rate τ is needed, and was provided by Bloch by making a quantum generalization of the Boltzmann scattering operator. An approximate solution of Bloch’s theory knownas the BlochGruneisen formula is often very successful in fitting data for magnesium diboride (MgB2). In this example theory deviates from experiment at higher temperatures because high frequency lattice vibrations involving boron atoms, are not well represented by the form of the approximate theory. Bloch’s theory has failures, but they are out numbered by the successes. One failure is that collective behavior can sometimes be seen at low temperature, the outstanding example being superconductivity. Other examples are more controversial, and include so called Luttinger liquid behavior which definitely happens in ideal one dimensional theoretical models and probably is seen in careful experiments on such systems as carbon nanotubes. Another case is transport by so called sliding charge density waves perhaps seen in quasi one dimensional metals like NbSe3. A more common failure is that in metals which are very impure or which have very strongs cattering, the mean free path between scattering events may become so short that the wavelength and wave vector of electron quantum states is no longer definable. This undermines the basis of Bloch’s theory. Such a failure of the theory (technically, a failure of the quasiparticle picture) showing the resistivity of Ti1−xAlx alloys. At the lower aluminum concentrations, x = 3% and 6%, the ρ(T) curves shift upward, obeying Mattheissen’s rule, given by Eq. (14), where the residual resistivity ρ = ρ0 + ρpure(T) (14) ρ0 is proportional to impurity concentration x. For the larger concentrations, a too short mean free path causes the quasiparticle picture underlying Bloch Boltzmann theory to fail. This in turn causes failure of

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Mattheissen’s rule. The quasiparticle picture also fails at high temperature for all concentrations x. A more abstract formulation of nonequilibrium effects like conductivity exists under the name of Kubo formulas. These provide a route to improved theories. 16

Small Signal Model

The Concept of FET small signal model is to find an equivalent circuit

which interrelates the incremental changes in ID,VGS,VDS etc. Since the changes are small, the small signal equivalent circuit has linear elements only (e.g., capacitors, resistors, controlled sources) and the derivation for that we consider for example the relationship of the increment in drain current due to an increment in gate source voltage when the FET is saturated with all other voltages held constant.

We have the functional dependence of the total drain current in saturation

Taylor expansion around the DC operating point (also called the quiescent point or Q point) defined by the DC voltages Q (VGS,VDS,VBS). If the small signal voltage is really small, then we can neglect all everything past the linear term where the partial derivative is depend as the transconductance. 17

Hall Effect

If an electric current flows through a conductor in a magnetic field the

magnetic field exerts a transverse force on the moving charge carriers which tends to push them to one side of the conductor. This is most evident in a

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thin flat conductor as illustrated. A buildup of charge at the sides of the conductors will balance this magnetic influence producing a measurable voltage between the two sides of the conductor. The presence of this measurable transverse voltage is called the Hall effect. As we know that the direction of the current I in the diagram is that of conventional current so that the motion of electrons is in the opposite direction. That further confuses all the right hand rule manipulations you have to go through to get the direction of the forces. The Hall effect can be used to measure magnetic fields with a Hall probe. The Hall effect is a conduction phenomenon which is different for different charge carriers. In most common electrical applications, the conventional current is used partly because it makes no difference whether you consider positive or negative charge to be moving. But the Hall voltage has a different polarity for positive and negative charge carriers and it has been used to study the details of conduction in semiconductors and other materials which show a combination of negative and positive charge carriers. Low gate signal power requirement. No gate current can flow into the gate after the small gate oxide capacitance has been charged.The Hall effect can be used to measure the average drift velocity of the charge carriers by mechanically moving the Hall probe at different speeds until the Hall voltage disappears showing that the charge carriers are now not moving with respect to the magnetic field as shown in fig 2.

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Fig 2.Hall Effect in FET

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Fermi Energy

The Fermi energy is a concept in quantum mechanics usually referring to

the energy of the highest occupied quantum state in a system of fermions at absolute zero temperature. This article requires a basic knowledge of quantum mechanics.As we know that the term Fermi energy is often confusingly used to describe a different but closely related concept the Fermi level (also called chemical potential).The Fermi energy and chemical potential are the same at absolute zero but differ at other temperatures. In quantum mechanics a group of particles known as fermions ( example electrons, protons and neutrons) obey the Pauli exclusion principle, which states that no two fermions can occupy the same quantum state. The states are labeled by a set of quantum numbers. In a system containing many fermions each fermion will have a different set of quantum numbers. To determine the lowest energy a system of fermions can have, we first group the states into sets with equal energy and order these sets by increasing energy. Starting with an empty system we then add particles one at a time, consecutively filling up the unoccupied quantum states with the lowest energy. When all the particles have been put in, the Fermi energy is the energy of the highest occupied state. What this means is that even if we

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have extracted all possible energy from a metal by cooling it down to near absolute zero temperature (0 kelvin), the electrons in the metal are still moving around; the fastest ones would be moving at a velocity that corresponds to a kinetic energy equal to the Fermi energy. This is the Fermi velocity. The Fermi energy is one of the important concepts of condensed matter physics. It is used for example to describe metals, insulators, and semiconductors. It is a very important quantity in the physics of supe rconductors in the physics of quantum liquids like low temperature helium (both normal and superfluid He) and it is quite important to nuclear physics and to understand the stability of white dwarf stars against gravitational collapse.

Fermi Level 19

In semiconductor physics it is conventional to work mainly with unreferenced energy symbols. This is possible because the relevant formula of semiconductor physics mostly contain differences in energy levels, For example (EC-EF). Thus, for developing the basic theory of semiconductors there is little merit in introducing an absolute energy reference zero. The central task of basic semiconductor physics is to establish formula for the position of the Fermi level EF relative to the energy levels EC and EV (the level of the bottom of the conduction band and the top of the valence band) taking into account the effects of doping. Doping introduces additional electron energy levels into the band gap, that may or may not be populated by electrons dependent on circumstances and temperature, and causes the Fermi level EF to shift from the energy level (relative to the band structure) that it would have had in the absence of doping. This energy level that the Fermi level has in the absence of doping is called the intrinsic Fermi level intrinsic level and is usually denoted by the symbol Ei. The theory of semiconductor physics is constructed in such a fashion that in a situation of complete thermodynamic equilibrium the position of the Fermi level

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relative to the band structure determines both the density of electrons and the density of holes. 20

Fermi Dirac statistics

Fermi Dirac statistics (F D statistics) is a part of the science of physics

that describes the energies of single particles in a system comprising many identical particles that obey the Pauli Exclusion Principle. It is named after Enrico Fermi and Paul Dirac, who each discovered it independently. F D statistics applies to identical particles with half-integer spin in a system in thermal equilibrium. Additionally, the particles in this system are assumed to have negligible mutual interaction. This allows the many particle system to be described in terms of single-particle energy states. The result is the Fermi Dirac distribution of particles over these states and includes the condition that no two particles can occupy the same state which has a considerable effect on the properties of the system. Since Fermi–Dirac statistics applies to particles with half-integer spin, they have come to be called fermions. It is most commonly applied to electrons

which are

fermions with spin 1/2. Fermi Dirac statistics is a part of the more general field of statistical mechanics and uses the principles of quantum mechanics. Suppose we have a number of energy levels, each level having energy εi and containing a total of ni particles. Suppose each level contains gi distinct sublevels, all of which have the same energy, and which are distinguishable. For example, two particles may have different momenta, in which case they are distinguishable from each other, yet they can still have the same energy. The value of gi associated with level i is called the degeneracy of that energy level. The Pauli exclusion principle states that only one fermion can occupy any such sublevel.

FET as a Voltage Variable Resistor

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FET is operated in the constant current portion of its output characteristics for the linear applications .In the region before pinch off , where Vds is small the drain to source resistance rd can be controlled by the bias voltage Vgs.The FET is useful as a voltage variable resistor (VVR) or Voltage Dependent resistor.In FET the drain source conductance gd = Id/Vds for small values of Vds which may be expressed as gd = gdo [ 1( VgsVp)1/2 ] where gdo is the value of drain conductance when the bias voltage Vgs is zero.The variation of the rd with vgs can be closely approximated by rd = ro / 1- KVgs ro – drain resistance at zero gate bias and K constant dependent upon FET type.Small signal FET drain resistance rd varies with applied gate voltage Vgs and FET act like a Variable Passive Resistor.

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FET Source Follower Circuit

When measuring the fet and you observed all the readings moved toward the 0 ohms range then the FET is considered shorted and need to be replace. The common drain amplifier or source follower is a particularly valuable configuration its high input impedance and low output impedance make it very useful for impedance transformations between FET and bipolar transistors. By considering eight circuits (Fig) which represent virtually every source follower configuration, the designer can obtain consistent circuit performance despite wide device variations. There are two basic connections for source followers with and without gate feedback. Each connection comes in several variations. Circuits through have no gate feedback their input impedances therefore are equal to RG. When measuring the fet and you observed all the readings moved toward the 0 ohms range then the FET is considered shorted and need to be replace. Circuits through employ feedback to their gates to increase the input impedance above RG.Before getting into the details of bias circuit design several general observations can be made about the circuits of Fig 3.

19 (a) Circuits

can accept only positive and small negative signals, because

these circuits have their source resistors connected to ground. The other circuits can handle large positive and negative signals limited only by the vailable supply voltages and device breakdown voltage. (b) Circuits

employ current sources to improve drain current (ID) stability

and increase gain. (c) Circuits employ JFET as current sources. (d) Circuits

employ a source resistor RS which may be selected to set the

quiescent output voltage equal to zero. (e) Circuits

use matched FET. RS is selected to set ID .The DC input

output offset voltage is zero.

Fig 3. Source Follower Circuit for FET

Testing of FET 23

Checking components that have two leads such as the resistor, capacitor, diode etc are much easier than checking transistor and FET which have three leads. Quite often technicians get confused with the three leg devices.

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In this report i will share with you on how to accurately check Field Effect Transistor (FET) using analog multimeter. Firstly identify the gate, drain and source pin from semiconductor.Once you have locate each pin of the FET then use your analog meter set to times 10K ohm range. If you are measuring an N channel FET then place the black probe to the drain pin. Then touch the gate pin with the red probe to discharge any internal capacitance in the fet. Now move the red probe to source pin while the black probe still touching the drain pin. Use your finger and touch the gate and drain pin together and you will see the analog meter needle will kick forward to middle range of the meters scale. Removing the red probe from the source pin and touching it back again the source pin the needle will still remain at the center of the meters scale. To discharge it you have to remove the red probe and touch one time on the gate pin. This will discharge the internal capacitance again. Now using the red probe to touch on the source pin again, the needle would not move at all because you already discharge it by touching the gate pin. I know is a little bit of confusion but after some practice you will be able to test all types of FET. When measuring the fet and you observed all the readings moved toward the 0 ohms range then the FET is considered shorted and need to be replace. Checking the P channel is similar to checking an N channel FET just switch the probe polarity when measuring the P channel. If you having an analog multimeter with a times 100k Ohm range then you might not be able to accurately check the FET due to the missing of 9 Volt battery in the meter. The missing of 9 volt battery will have not enough power to trigger the FET. Make sure your meter have the time 10k ohm range. Typical N channel FET part numbers are K792, K1118, IRF630, IRF 840. P channel FET part number are J306, J512, IRF9610 etc.

Types of FET

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There are three types of field-effect transistors, the Junction Field Effect Transistor (JFET) and the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or Insulated Gate Field Effect Transistor (IGFET). In our trainer Kit we use MOSFET because they are easier to drive in high current applications The principles on which these devices operate (current controlled by an electric field) are very similar the primary difference being in the methods by which the control element is made. This difference, however results in a considerable difference in device characteristics and necessitates variances in circuit design. The description of the FET types are mentioned below in this report. 24

Junction Field Effect Transitor

The JFET is a long channel of semiconductor material doped to contain

an abundance of positive charge carriers (P type) or of negative carriers (N type). Contacts at each end form the source and drain. The gate (control) terminal has doping opposite to that of the channel which it surrounds so that there is a PN junction at the interface. Terminals to connect with the outside are usually made ohmic. In its simplest form the junction field effect transistor starts with nothing more than a bar of doped silicon that behaves as a resistor (Fig 4). By convention the terminal into which current is injected is called the source terminal, Since as far as the FET is concerned, current originates from this terminal. The other terminal is called the drain terminal. Current flow between source and drain is related to the drain source voltage by the resistance of the intervening material. In Fig 4 P type regions have been diffused into the N type substrate of Fig 4 leaving an N type channel between the source and drain. (A complementary P type device is made by reversing all of the material types.) These P type regions will be used to control the current flow between the source and the drain and are thus called gate regions. As with any PN junction, a depletion region surrounds the PN junctions when the junctions are reverse biased. As

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the reverse voltage is increased, the depletion regions spread into the channel until they meet, creating an almost infinite resistance between the source and the drain. If an external voltage is applied between source and drain with zero gate voltage, drain current flow in the channel sets up a reverse bias along the surface of the gate, parallel to the channel. As the drain source voltage increases, the depletion regions again spread into the channel because of the voltage drop in the channel which reverse biases the junctions. As VDS is increased, the depletion regions grow until they meet, whereby any further increase in voltage is counter balanced by an increase in the depletion region toward the drain. There is an effective increase in channel resistance that prevents any further increase in drain current. The drain source voltage that causes this current limiting condition is called the pinchoff voltage (Vp). A further increase in drain source voltage produces only a slight increase in drain current. The variation in drain current (ID) with drain source voltage (VDS) at zero gate source voltage (VGS). In the low current region, the drain current is linearly related to VDS. As ID increases, the channel begins to deplete and the slope of the ID curve decreases. When the VDS is equal to Vp, ID saturates and stays relatively constant until drain to gate avalanche, VBR(DSS) is reached. If a reverse voltage is applied to the gates, channel pinchoff occurs at a lower ID level because the depletion region spread caused by the reverse biased gates adds to that produced by VDS. Thus reducing the maximum current for any value of VDS. Due to the difficulty of diffusing impurities into both sides of a semiconductor wafer, a single ended geometry is normally used instead of the two-sided structure. Diffusion for this geometry is from one side only. The substrate is of P type material onto which an N type channel is grown epitaxially. A P type gate is then diffused into the N type epitaxial channel.

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Fig 4. Junction Field Effect Transitor

Contact metallization completes the structure. The substrate, which functions as Gate 2, is of relatively low resistivity material to maximize gain. For the same purpose, Gate 1 is of very low resistivity material allowing the depletion region to spread mostly into the N type channel. In most cases the gates are internally connected together. A tetrode device can be realized by not making this internal connection.

Operation 25

Consider an N channel JFET and it is assumed that the two terminals labeled G are joined together. With VGS a voltage VDS = 0 the application of causes current to flow from the drain to the source. When a negative is applied, the depletion region of the gate channel junction widens and the channel becomes correspondingly narrower thus the channel resistance increases and the current ID (for a given VDS) decreases. Because VDS is small the channel is almost of uniform width. The JFET is simply operating as a resistance whose value is controlled by VGS. If we keep increasing VGS in the negative direction, a value is reached at which the depletion region occupies the entire channel. At this value of VGS the channel is completely depleted of charge carriers (electrons); the channel has in effect disappeared. This value of VGS is therefore the threshold voltage of the

24

device Vt which is obviously negative for an N channel JFET. For JFET the threshold voltage is called the pinchoff voltage and is denoted Vp. Consider next the situation depicted in Fig.5.

Fig 5.Physical Operation of N Channel JFET

Here VGS is held constant at a value greater (that is, less negative) than Vp and VDS is increased. Since VDS appears as a voltage drop across the length of the channel, the voltage increases as we move along the channel from source to drain. It follows that the reverse bias voltage between gate and channel varies at different points along the channel and is highest at the drain end. Thus the channel acquires a tapered shape and the ID, VDS characteristic becomes nonlinear. When the reverse bias at the drain end, VGD falls below the pinchoff voltage Vp the channel is pinched off at the drain end and the drain current saturates. Its characteristics should therefore be similar to those of the depletion type JFET. This is true with a very important exception While it is possible to operate the depletion type JFET in the enhancement mode (by simply applying a positive VGS if the device is

25

n channel) this is impossible in the JFET case. If we attempt to apply a positive VGS, the gate channel PN junction becomes forward biased and the gate ceases to control the channel. Thus the maximum VGS is limited to 0 V though it is possible to go as high as 0.3 V or so since a PN junction remains essentially cut off at such a small forward voltage.

Conductivity of JFET 26

The property of a metal that measures its ability to conduct electricity following Ohms law. Electrical conductivity σ is the reciprocal of the resistivity ρ where resistance R in Ohms is voltage drop V in volts (V) divided by current I in amperes (A). Ohm’s law V = IR may also be written where j is current density and E = V/L is electric field or electrical potential gradient measured in V/m, where V is the voltage drop measured across a length L of material. The conductivity σ is an intrinsic property of a pure material related to the measured conductance G = I/V via G = σA/L, just as resistance R = V/I relates to resistivity ρ via R = ρL/A. Thus a large-gauge conductor of short length has a high conductance, but the physical dimensions do not affect the conductivity σ or the resistivity ρ. Positive current flows from higher to lower voltage and σ is never negative.

Transconductance 27

Transconductance, also known as mutual conductance, is a property of certain electronic components. Conductance is the reciprocal of resistance and transconductance is the ratio of the current at the output port and the voltage at the input ports. It is a contraction of "transfer conductance". The old unit of conductance, the mho (ohm spelled backwards), was replaced by the SI (International System) unit, the siemens, with the symbol S (1 siemens = 1 ampere per volt). For vacuum tubes, transconductance is defined as the change in the plate(anode) cathode current divided by the corresponding change in the grid/cathode voltage, with a constant plate(anode)/cathode voltage. Typical values of gm for a small signal

26

vacuum tube are 1 to 10 millisiemens and the Transresistance, infrequently referred to as mutual resistance, is the dual of transconductance. It is a contraction of transfer resistance. It refers to the ratio between a change of the voltage at two output points and a related change of current through two input points.

Current Voltage Characteristics 28

The current voltage characteristics of the JFET except that for the JFET the maximum VGS allowed is normally 0V. Furthermore, the JFET is specified in terms of the pinchoff voltage Vp (equal to Vt of the FET) and the drain to source current with the gate shorted to the source.Recalling that for an N channel device, Vp is negative, we see that operation in the pinchoff region is obtained when the drain voltage is greater than the gate voltage by at least Vp. Since the gate channel junction is always reverse biased only a leakage current flows through the gate terminal. Although IG is very small, and is assumed zero in almost all applications, it should be noted that the gate current in a JFET is many orders of magnitude greater than the gate current in a JFET. Of course the latter is so tiny because of the insulated gate structure.Another complication arises in the JFET because of the strong

dependence

of

gate leakage

current

on

temperature

approximately doubling for every 10°C rise in temperature, just as in the case of a reverse-biased diode. The VI characteristics of JFET as shown in fig 6 and it can be grouped in three regions viz. ohmic region where it is steeper and has linear relation between ID and VDS, pinchoff region here relation between ID and VDS is remains constant and break down region where ID suddenly increases with small increase in VDS.

27

Fig 6. Output Characterstics and circuit diagram of JFET

Drift Current Drift is by definition charged particle motion in response to an applied electric field. When an electric field is applied across a semiconductor the carriers start moving producing a current. The positively charged holes move with the electric field whereas the negatively charged electrons move against the electric field. The motion of each carrier can be described as a constant drift velocity

vd.This constant takes into consideration the

collisions and setbacks each carrier has while moving from one place to another. It is considered a constant though, because the carriers will eventually go the direction they are supposed to go regardless of any

28

setbacks especially if you look at the direction of all the carriers instead of each one individually. Drift current in a semiconductor is the resultant of carrier drift. Because we are talking about a semiconductor or specific areas in a semiconductor. When dealing with drift current we are interested in the current density due to drift and drift arises in response to an electric field. Drift current also depends on the ability of the carriers to move around in the semiconductor, or the electron and hole mobility. Another parameter drift current depends on is the carrier concentration because you have to have carriers in order for there to be current. Each one of these carriers has a charge but in this case we will only take q as a magnitude. Finally we have that the current density due to drift depends on four parameters such as the electric field, the electron or hole concentration, the mobility constant, and the charge. The reason we use q for both electrons and holes when it's +Q for holes and -Q for electrons is that the electric field takes care of the sign or direction of the current. When a negative electric field is applied the electrons will go opposite the electric field. The electron charge is -Q so the resulting electron drift current will be positive. On the other hand when the electric field is negative the holes will go the direction of the electric field. Their charge is +Q so the resulting hole drift current will be negative.

Diffusion current Diffusion is the process of particles distributing themselves from regions of high concentration to regions of low concentration. If this process is left unperturbed, there will eventually be a uniform distribution of particles. Diffusion does not need external forces to act upon a group of particles. The particles move about using only thermal motion. If we let the particles be carriers so as they move around they take charge with them. The moving of charge will result in a current. We call this current a diffusion current. A faradaic current whose magnitude is controlled by the rate at which a reactant in an electrochemical process diffuses toward an electrode solution

29

interface and sometimes by the rate at which a product diffuses away from that interface.There are two common situations in which a diffusion current can be observed. In one the rate of formation of B from electroinactive C is small and the current is governed by the rate of diffusion of B toward the electrode surface. In the other C predominates at equilibrium in the bulk of the solution, but its transformation into B is fast C diffuses to the vicinity of the electrode surface and is there rapidly converted into B which is reduced. Diffusion current occurs even though there is not an electric field applied to the semiconductor.

Fermi Dirac Distribution 29

The Fermi Dirac distribution applies to fermions particles with half integer spin which must obey the Pauli exclusion principle. Each type of distribution function has a normalization term multiplying the exponential in the denominator which may be temperature dependent. The significance of the Fermi energy is most clearly seem by setting T=0. At absolute zero the probability is =1 for energies less than the Fermi energy and zero for energies greater than the Fermi energy. We picture all the levels up to the Fermi energy as filled, but no particle has a greater energy. This is entirely consistent with the Pauli exclusion principle where each quantum state can have one but only one particle.

Continuous Drain Current 30

MOSFET has an extremely high input gate resistance and as such a easily damaged by static electricity if not carefully protected. MOSFET are ideal for use as electronic switches or common source amplifiers as their power consumption is very small.ID is a rating of the maximum continuous DC current with the die at its maximum rated junction temperature (max) and the case at 25°C and sometimes also at a higher temperature. As we know that there are no switching losses involved in ID and holding the case at 25°C is seldom feasible in practice. Because of this actual switched

30

current is typically less than half of the ID

rating in a hard switched

application one fourth to one third is common. The control of the drain current by a negative gate potential makes the Junction Field Effect Transistor useful as a switch and it is essential that the gate voltage is never positive for an N-channel JFET as the channel current will flow to the gate and not the drain resulting in damage to the JFET. The principles of operation for a P channel JFET are the same as for the N channel JFET except that the polarity of the voltages need to be reversed.

Drain Source Voltage

This is a rating of the maximum drain source voltage without causing

avalanche breakdown, with the gate shorted to the source and the device at 25°C. Depending on temperature, the avalanche breakdown voltage could actually be less than the VDS rating. See the description of V(BR)DSS in Static VI Characteristics.

Gate Source Voltage VGS is a rating of the maximum voltage between the gate and source terminals. The purpose of this rating is to prevent damage of the gate oxide. The actual gate oxide withstand voltage is typically much higher than this but varies due to manufacturing processes so staying within this rating ensures application reliability.

Pulsed Drain Current

This rating indicates how much pulsed current the device can handle

which is significantly higher than the rated continuous DC current. The purposes of the IDM rating are to keep the JFET operating in the Ohmic region of its output characteristic as shown in fig4. There is a maximum drain current for a corresponding gate source voltage that a JFET will conduct. If the operating point at a given gate source voltage goes above the Ohmic region knee in Fig4 any further increase in drain current results in a significant rise in drain source voltage (linear mode operation) and a

31

consequent rise in conduction loss. If power dissipation is too high for too long the device may fail. The IDM rating is set below the knee for typical gate drive voltages. A current density limit to prevent die heating that otherwise could result in a burnout site. To avoid problems with excessive current through the bond wires in case the bond wires are the weak link instead of the die.

Ohmic Region

The depletion layer of the channel is very small and the JFET acts like a

variable resistor.

Cut off Region

The gate voltage is sufficient to cause the JFET to act as an open circuit

as the channel resistance is at maximum.

Saturation or Active Region

The JFET becomes a good conductor and is controlled by the gate-

source voltage (VGS) while the drain source voltage (VDS) has little or no effect.

Breakdown Region The voltage between the drain and source (VDS) is high enough to causes the JFET resistive channel to break down and pass current.

Switching Speed Switching speed and loss are practically unaffected by temperature because the capacitances are unaffected by temperature. Reverse recovery current in a diode however increases with temperature, so temperature effects of an external diode (be it a discrete diode or a MOSFET body diode) in the power circuit affect turn on switching loss. 31

Transfer Characteristic

The transfer characteristic for an JFET. The transfer characteristic

depends on both temperature and drain current. In Figure 7 below 100 Amps the gate source voltage has a negative temperature coefficient (less gate source voltage at higher temperature for a given drain current).Above

32

100 Amps, the temperature coefficient is positive.The gate source voltage temperature coefficient and the drain current at which it crosses over from negative to positive are important for linear mode operation.

Fig 7. Transfer Characterstics of JFET

Threshold Voltage The threshold voltage, denoted as VGS(th) is really a turn off specification. It tells how many milliamps of drain current will flow at the threshold voltage so the device is basically off but on the verge of turning on. The threshold voltage has a negative temperature coefficient meaning the threshold voltage decreases with increasing temperature. This temperature coefficient affects turn on and turn off delay times and hence the dead-time requirement in a bridge circuit. 32

Thermal Characteristics (TJ, RθJC, RθSA, ZθJC(t))

The power loss of the device turns into heat and increases the junction

temperature. This degrades device characteristics and reduces its life span. It is very important to lower the junction temperature by discharging heat from the chip junction. The thermal impedance (ZθJC(t)) is used to monitor.Thermal characteristics terminology is shown below in fig 8. (a) TJ

(Junction Temperature)

33 (b) TC (c)

(Case Temperature).

TS (Heat Sink Temperature).

(d) TA

(Ambient Temperature)

(e) RθJC (f)

(Junction to Case Thermal Resistance)

RθCS (Case to Sink Thermal Resistance)

(g) RθSA

(Sink to Ambient Thermal Resistance)

Fig 8. Parameters of Thermal Characterstics

As shown in Figure 8 the heat produced at the chip junction normally discharges over 80% in the direction and about 20% in the direction. The path of the thermal discharge is the same as the movement of the current, and is represented in Figure after considering thermal resistance. This is true only for DC operation. Most JFET are used in switching operations with a fixed duty factor. Hence, thermal capacitance should be taken into consideration along with thermal resistance. The thermal resistance from the chip junction to the ambient is RθJA (junction to ambient thermal resistance) and the equivalent circuit can be expressed as the following equation.

34

RθJC (Junction to Case Thermal Resistance)

RθJC is the internal thermal resistance from the chip junction to the

package case. Once the size of the die is decided, this thermal resistance of pure package is only determined by the package design, and lead frame material. RθJC can be measured under the condition of TC = 25°C and can be written as the following equation.

The condition TC = 25°C means that the infinite heat sink is mounted. Infinite heat sink. The case temperature of the package is equal to the environment temperature. It is the heat sink, which can realize TC = TA.

RθCS (Case to Sink Thermal Resistance) This is the thermal resistance from the package case to the heat sink. It can vary due to the package and the mounting method to the heat sink.

RθSA (Sink to Ambient Thermal Resistance) This is the thermal resistance from the heat sink to the ambient, and it is determined by heatsink design.

Advantages of JFET 33

JFET has following advantages which are mentioned below. (a) Very high input impedance order of 100 ohm (b) Operation

of JFET depends on the bulk material

current

carriers that do not cross junctions. (c)

Negative temperature coefficients.

(d) Very

high power gain.

(e) Smaller (f)

size longer life and high efficiency.

AC drain resistance rd it is the ratio of change in drain source voltage to the change in drain current at constant gate source voltage.

35 (g) Transconductance

it is the ratio of change in drain current to

the change in gate source voltageat constant drain source voltage . (h) Amplification factor it is the ratio of change in drain source voltage to the change in gate source voltage at constant drain current. 34

Metal Oxide Semiconductor Field Effect Transistor

The MOSFET type of field effect transistor has a Metal Oxide gate

(usually silicon dioxide commonly known as glass) which is electrically insulated from the main semiconductor N channel or P channel. This isolation of the controlling gate makes the input resistance of the MOSFET extremely high in the Mega ohms region and almost infinite. As the gate terminal is isolated from the main current carrying channel No current flows into the gate and like the JFET, the MOSFET also acts like a voltage controlled resistor. Also like the JFET, this very high input resistance can easily accumulate large static charges resulting in the MOSFET becoming easily damaged unless carefully handled or protected. MOSFET is a voltage controlled majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). This device promised extremely low input power levels and no inherent limitation to the switching speed. Consequently the use of MOSFET has been restricted to low voltage (less than about 500 volts) applications where the ON state resistance reaches acceptable values. Inherently fast switching speed of these devices can be effectively utilized to increase the switching frequency beyond several hundred KHz.

36

35

MOS Technology

The bipolar and the MOSFET transistors exploit the same operating

principle. Fundamentally, both type of transistors are charge controlled devices which means that their output current is proportional to the charge established in the semiconductor by the control electrode. When these devices are used as switches, both must be driven from a low impedance source capable of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. From this point of view, the MOSFET have to be driven just as hard during turn on and turn off as a bipolar transistor to achieve comparable switching speeds. Theoretically, the switching speeds of the bipolar and MOSFET devices are close to identical, determined by the time required for the charge carriers to travel across the semiconductor region. Typical values in power devices are approximately 20 to 200 picoseconds depending on the size of the device. The popularity and proliferation of MOSFET technology for digital and power applications is driven by two of their major advantages over the bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in high frequency switching applications. The MOSFET transistors are simpler to drive because their control electrode is isolated from the current conducting silicon, therefore a continuous ON current is not required. Once the MOSFET transistors are turned on

their drive

current is practically zero. Also, the controlling charge and accordingly the storage time in the MOSFET transistors is greatly reduced. This basically eliminates the design trade off between on state voltage drop which is inversely proportional to excess control charge and turn off time. As a result MOSFET technology promises to use much simpler and more efficient drive circuits with significant economic benefits compared to bipolar devices. Furthermore, it is important to highlight especially for power applications, that MOSFET have a resistive nature. The voltage drop

37

across the drain source terminals of a MOSFET is a linear function of the current flowing in the semiconductor. This linear relationship is characterized by the RDS(on) of the MOSFET and known as the on resistance. On resistance is constant for a given gate-to-source voltage and temperature of the device. As opposed to the 2.2mV/°C temperature coefficient of a p n junction, the MOSFET exhibit a positive temperature coefficient of approximately 0.7%/°C to 1%/°C. This positive temperature coefficient of the MOSFET makes it an ideal candidate for parallel operation in higher power applications where using a single device would not be practical or possible. Due to the positive TC of the channel resistance, parallel connected MOSFET tend to share the current evenly among themselves. This current sharing works automatically in MOSFET since the positive TC acts as a slow negative feedback system. The device carrying a higher current will heat up more don’t forget that the drain to source voltages are equal and the higher temperature will increase its RDS(on) value. The increasing resistance will cause the current to decrease, therefore the temperature to drop. Eventually, an equilibrium is reached where the parallel connected devices carry similar current levels. Initial tolerance in RDS(on) values and different junction to ambient thermal resistances can cause significant up to 30% error in current distribution. 36

Construction

MOSFET is a device that evolved from MOS integrated circuit

technology. The first attempts to develop high voltage MOSFET were by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology was called lateral double diffused MOS. However it was soon realized that much larger breakdown voltage and current ratings could be achieved by resorting to a vertically oriented structure. Since then vertical DMOS structure has been adapted by virtually all manufacturers of MOSFET. MOSFET using MOS technology has vertically oriented three

38

layer structure of alternating P type and N type semiconductors which is the schematic representation of a single MOSFET cell structure as shown in fig9. A large number of such cells are connected in parallel to form a complete device same level. The P type middle layer is termed the body (or substrate) and has moderate doping level ( magnitude lower than

n+

regions on both sides). The n- drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The gate terminal is placed over the n- and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also connected together. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions, to same extent, influences the ON state resistance of the MOSFET. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective short circuit between the body and the source the BJT always remain in cut off and its collector base junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a MOSFET.In a MOSFET device no such limitations applies so it is possible to bias the gate in either polarity. This makes MOSFET specially valuable as electronic switches or to make logic gates because with no bias they are normally non conducting and the high gate resistance means that very little control current is needed.

39

Fig 9 MOSFET Construction Diagram

Operating principle of a MOSFET 37

As we know that in first glance it would appear that there is no path for any current to flow between the source and the drain terminals since at least one of the PN junctions (source body and body Drain) will be reverse biased for either polarity of the applied voltage between the source and the drain. There is no possibility of current injection from the gate terminal either since the gate oxide is a very good insulator. However, application of a positive voltage at the gate terminal with respect to the source will covert the silicon surface beneath the gate oxide into an n type layer or channel thus connecting the Source to the Drain. The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide layer and the P body silicon forms a high quality capacitor. When a small voltage is application to this capacitor structure with gate terminal positive with respect to the source (note that body and source are shorted) a depletion region forms at the interface between the SiO2and the silicon as shown in Fig 9. The positive charge induced on the gate metallization repels the

40

majority hole carriers from the interface region between the gate oxide and the P type body. This exposes the negatively charged acceptors and a depletion region is created. Further increase in VGS causes the depletion layer to grow in thickness. At the same time the electric field at the oxide silicon interface gets larger and begins to attract free electrons as shown in Fig 9. The immediate source of electron is electron-hole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source. As VGS increases further the density of free electrons at the interface becomes equal to the free hole density in the bulk of the body region beyond the depletion layer. The layer of free electrons at the interface is called the inversion layer. The inversion layer has all the properties of an N type semiconductor and is a conductive path or channel between the drain and the source which permits flow of current between the drain and the source. Since current conduction in this device takes place through an N type channel created by the electric field due to gate source voltage it is called Enhancement type N channel MOSFET. The value of VGS at which the inversion layer is considered to have formed is called the Gate Source threshold voltage VGS. As VGS is increased beyond VGS the inversion layer gets some what thicker and more conductive, since the density of free electrons increases further with increase in VGS. The inversion layer screens the depletion layer adjacent to it from increasing VGS.The depletion layer thickness now remains constant. This is the active mode of operation of a MOSFET. 38

Current Voltage characteristics of a MOSFET

The MOSFET is a three terminal device where the voltage on the gate

terminal controls the flow of current between the output terminals such as Source and Drain. The source terminal is common between the input and the output of a MOSFET. The output characteristics of a MOSFET is then a

41

plot of drain current (ID) as a function of the Drain Source voltage (VDS) with gate source voltage (VGS) as a parameter. Fig 10 shows such a characteristics. With gate source voltage (VGS) below the threshold voltage (VGS (th)) the MOSFET operates in the cut off mode. No drain current flows in this mode and the applied drain source voltage (VDS) is supported by the body collector PN junction. Therefore the maximum applied voltage should be below the avalanche break down voltage of this junction (VDSS) to avoid destruction of the device. When VGS is increased beyond VGS (th) drain current starts flowing. For small values of VDS (VDS < (VGS – VGS (th)) ID is almost proportional to VDS. Consequently this mode of operation is called ohmic mode of operation. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the VDS ID characteristics in this mode is called the ON state resistance of the MOSFET (RDS (ON)). Several physical resistances as shown in Fig 10 contribute to RDS (ON). As we know that RDS (ON) reduces with increase in VGS. This is mainly due to reduction of the channel resistance at higher value of VGS. Hence, it is desirable in power electronic applications, to use as large a gate source voltage as possible subject to the dielectric break down limit of the gate oxide layer. At still higher value of VDS (VDS > (VGS VGS (th)) the ID -VDS characteristics deviates from the linear relationship of the ohmic region and for a given VGS, ID tends to saturate with increase in VDS. The exact mechanism behind this is rather complex. It will suffice to state that, at higher drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. In addition, at large value of the electric field, produced by the large Drain Source voltage, the drift velocity of free electrons in the channel tends to saturate as shown in Fig 10.

42

Fig 10. MOSFET V-I Characterstics

As a result the drain current becomes independent of VDS and determined solely by the gate source voltage VGS. Simple, first order theory predicts that in the active region the drain current is given approximately by ID = K (VGS - VGS (th)) VDS = VGS - VGS (th) Therefore

ID = K VDS

At the boundary between the ohmic and the active region .However for power MOSFET the transfer characteristics (ID - VGS) is more linear as shown in Fig 7. At this point the similarity of the output characteristics of a MOSFET. Both of them have three distinct modes of operation namely cut off active and ohmic (saturation for MOSFET) modes.

Controlling the MOSFET A major advantage of the power MOSFET is its very fast switching speeds. The drain current is strictly proportional to gate voltage so that the theoretically perfect device could switch in 50 ps±200 ps, the time it takes the carriers to flow from source to drain. Since the MOSFET is a majority carrier device, a second reason why it can outperform the bipolar junction transistor is that its turn-off is not delayed by minority carrier storage time

43

in the base. A MOSFET begins to turn off as soon as its gate voltage drops down to its threshold voltage. 39

Breakdown Voltage

Breakdown voltage BVDSS is the voltage at which the reverse biased body drift diode breaks down and significant current starts to flow between the source and drain by the avalanche multiplication process while the gate and source are shorted together. Current voltage characteristics of a MOSFET are shown in Figure.BVDSS is normally measured at 250mA drain current. For drain voltages below BVDSS and with no bias on the gate no channel is formed under the gate at the surface and the drain voltage is entirely supported by the reverse biased body drift p n junction. Two related phenomena can occur in poorly designed and processed devices punch through and reach through. Punchthrough is observed when the depletion region on the source side of the body drift p n junction reaches the source region at drain voltages below the rated avalanche voltage of the device. This provides a current path between source and drain and causes a soft breakdown characteristics as shown in Figure . The leakage current flowing between source and drain is denoted by IDSS. There are tradeoffs to be made between RDS(on) that requires shorter channel lengths and punch through avoidance that requires longer channel lengths.The reach through phenomenon occurs when the depletion region on the drift side of the body drift p n junction reaches the epilayer substrate interface before avalanching takes place in the epi. Once the depletion edge enters the high carrier concentration substrate a further increase in drain voltage will cause the electric field to quickly reach the critical value of 2x105 V/cm where avalanching begins.

MOSFET Gate Drive 40

MOSFET being a voltage controlled device

does not require a

continuous gate current to keep it in the ON state. However it is required to

44

charge and discharge the gate-source and the gate drain capacitors in each switching operation. The switching times of a MOSFET essentially depends on the charging and discharging rate of these capacitors. Therefore if fast charging and discharging of a MOSFET is desired at fast switching frequency the gate drive power requirement may become significant. Fig 8 shows a typical gate drive circuit of a MOSFET. To turn the MOSFET on the logic level input to the inverting buffer is set to high state so that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 8 shows the equivalent circuit during turn on. Note that, during turn on Q1 remains in the active region. The effective gate resistance is RG + R1 / (β1+1) Where β1 is the DC current gain of Q1. To turn off the MOSFET the logic level input is set to low state. Q3 and Q2 turns on whole Q1 turns off. The corresponding equivalent circuit is given by the bottom circuit.The switching time of the MOSFET can be adjusted by choosing a proper value of RG. Reducing RG will incase the switching speed of the MOSFET. However caution should be exercised while increasing the switching speed of the MOSFET in order not to turn on the parasitic BJT in the MOSFET structure inadvertently. The drain source capacitance (CDS) is actually connected to the base of the parasitic BJT at the P type body region. The body source short has some non zero resistance. A very fast rising drain source voltage will send sufficient displacement current through CDS and RB as shown in Fig 8. The voltage drop across RB may become sufficient to turn on the parasitic BJT. This problem is largely avoided in a modern MOSFET design by increasing the effectiveness of the body source short. Since MOSFET on state resistance has positive temperature coefficient they can be paralleled without taking any special precaution for equal current sharing. To parallel two MOSFETs the drain and source terminals are connected together . However small resistances are connected to individual

45

gates before joining them together. This is because the gate inputs are highly capacitive with almost no losses. Some stray inductance of wiring may however be present. This stray inductance and the MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate voltage that can result in puncture of the gate oxide layer due to voltage increase during oscillations. This is avoided by the damping resistance R.

Fig 8. Gate Drive circuit of MOSFET

MOSFET Gate Charge 41

Although input capacitance values are useful they do not provide accurate

results when comparing the switching performances of two

devices from different manufacturers. Effects of device size and transconductance make such comparisons more difficult. A more useful parameter from the circuit design point of view is the gate charge rather than capacitance. Most manufacturers include both parameters on their data sheets. A typical gate charge waveform and the test circuit. When the gate is connected to the supply voltage, VGS starts to increase until it reaches Vth, at which point the drain current starts to flow and the CGS starts to charge. During the period t1 to t2, CGS continues to charge, the gate voltage continues to rise and drain current rises proportionally. At time t2, CGS is

46

completely charged and the drain current reaches the predetermined current ID and stays constant while the drain voltage starts to fall. With reference to the equivalent circuit model of the MOSFET shown in Figure 13, it can be seen that with CGS fully charged at t2, VGS becomes constant and the drive current starts to charge the Miller capacitance, CDG. This continues until time t3. Charge time for the Miller capacitance is larger than that for the gate to source capacitance CGS due to the rapidly changing drain voltage between t2 and t3 (current = C dv/dt). Once both of the capacitances CGS and CGD are fully charged, gate voltage (VGS) starts increasing again until it reaches the supply voltage at time t4. The gate charge (QGS + QGD) corresponding to time t3 is the bare minimum charge required to switch the device on. Good circuit design practice dictates the use of a higher gate voltage than the bare minimum required for switching and therefore the gate charge used in the calculations is QG corresponding to t4. The advantage of using gate charge is that the designer can easily calculate the amount of current required from the drive circuit to switch the device on in a desired length of time because Q = CV and I = C dv/dt, the Q = Time x current. For example, a device with a gate charge of 20nC can be turned on in 20msec if 1ma is supplied to the gate or it can turn on in 20nsec if the gate current is increased to 1A. These simple calculations would not have been possible with input capacitance values.

Transconductance 42

Transconductance gfs is a measure of the sensitivity of drain current to changes in gate source bias. This parameter is normally quoted for a Vgs that gives a drain current equal to about one half of the maximum current rating value and for a VDS that ensures operation in the constant current region. Transconductance is influenced by gate width, which increases in proportion to the active area as cell density increases. Cell density has increased over the years from around half a million per square inch in 1980

47

to around eight million for planar MOSFET and around 12 million for the trench technology. The limiting factor for even higher cell densities is the photolithography process control and resolution that allows contacts to be made to the source metallization in the center of the cells. Channel length also affects transconductance. Reduced channel length is beneficial to both gfs and on resistance with punch through as a tradeoff. The lower limit of thislength is set by the ability to control the double diffusion process and is around 1- 2mm today. Finally the lower the gate oxide thickness the higher gfs.

Threshold Voltage 43

Threshold voltage Vth is defined as the minimum gate electrode bias required to strongly invert the surface under the poly and form a conducting channel between the source and the drain regions. Vth is usually measured at a drain source current of 250mA. Common values are 2-4V for high voltage devices with thicker gate oxides and 1-2V for lower voltage, logiccompatible devices with thinner gate oxides. With power MOSFET finding increasing use in portable electronics and wireless communications where battery power is at a premium the trend is toward lower values of RDS(on) and Vth. This is the minimum gate bias which enables the formation of the channel between the source andthe drain. The drain current increases in proportion to (VGS–VGS(th)) in the saturation region.

(a) High VGS(th) It is difficult to design gate drive circuitry for the MOSFET because a high gate bias voltage is needed to turn it on.

(b) Low VGS(th) When the VGS(th) of the n-channel power MOSFET becomes negative due to the existence of charges in the gate oxide, it shows the characteristics of a normally on state, where the conductive channel exists even in a zero gate bias voltage. Even

48

if VGS(th) is positive, and the value is very small, there could be a turn-on either by the noise signal of the gate terminal, or by the increasing gate voltage during high speed switching. The VGS(th) can be controlled by the gate oxide thickness. Normally the gate oxide is kept thick in a high voltage device so that the VGS(th) is set at 2-4[V], and the gate oxide is kept thin in a low voltage device so that VGS(th) is 1 - 2 [V]. Additionally, VGS(th) can be controlled by back ground doping (the density of P body for the N channel MOSFET). It increases in proportion to the square root of the background doping.

Importance of Threshold Voltage

Threshold voltage VGS(th) is the minimum gate voltage that initiates drain

current flow. VGS(th) can be easily measured on a Tektronix 576 curve tracer by connecting the gate to the drain and recording the required drain voltage for a specified drain current, typically 250 mA or 1 mA. (VGS(th) in Figure 9 is 3.5V. While a high value of VGS(th), can apparently lengthen turn-on delay time a low value for power MOSFET is undesirable for the following reasons (a) VGS(th)

has a negative temperature coefficient b7 mV/C.

(b) The high gate impedance of a MOSFET makes it susceptible to spurious turn-on due to gate noise. (c)

One of the more common modes of failure is gate-oxide voltage punch through. Low VGS(th) requires thinner oxides,which lowers the gate oxide voltage rating.

Switching characteristics 44

The MOSFET have good switching characteristics as there is no storage delay caused by the minority carrier, and no variation caused by the temperature.They are explained in two states such as mentioned below.

(a)Turn On state

49

Drain current (ID) changes due to the increase in drain-to-source voltage (VDD) (VGS is constant). ID starts to flow when the channel has formed and VDD is supplied. When the VGS is a constant value, and the VDD is increased, the ID also increases linearly, But as shown in the MOSFET output characteristics graph, when the real VDD goes over a certain level, the rate of increase ID decreases slowly. And eventually, it becomes a constant value independent of VDD, and becomes dependent on VGS. To understand the characteristics, shown in Figure 11, note the voltage drop at VCS(x) due to ohmic resistance when ID is flowing at the inverse layer. VCS(x) is the channel to source voltage from the source at a distance of x. This voltage is equal to the VGS–Vox(x) at all x points. Vox(x) is the gate to body voltage crossing the gate oxide from the source at a distance of x, and it has the maximum value at VDS at x=L (the drain end of the channel). As shown in Figure 11(a), when low voltage VDD=VDD1 is supplied, low ID(=ID1) which has almost no voltage drop of VCS(x) flows. As Vox(0)~Vox(L) is constant, the thickness of the inversion layer remains uniform. And as higher VDD is supplied, ID increases,the voltage drop of VCS(x) occurs, and the value of Vox(x) decreases. These reduce the thickness of the inversion layer starting from x=L. Because of this, the resistance increases, and the graph of ID starts to become flat, as opposed to increasing with the increment of VDD. When Vox(L)=VGS–VDS=VGS(th), as ID increases, the inversion layer at x=L doesn’t disappear due to the high electric field (J=σE) formed by the reduction in thickness, and maintains the minimum thickness. The high electric field not only maintains the minimum thickness of the inversion layer, it also saturates

50

the velocity of the charge carrier at Vox(L)=VGS–VDS=VGS(th). The velocity of the charge carrier increases with the increase in the electric field initially, and at a certain point, it is saturated. Silicon starts saturating when the electric field reaches 1.5x104 [V/cm], and the drift velocity of the electron is 8x106 [cm/s]. At this point, the device goes into the active region. When a higher VDD is supplied, as shown in Figure 11(b), the electric field at x=L increases more, and the channel region which maintained the minimum thickness expands towards the source. VDS becomes VDS>VGS–VGS(th) due to the increase of VDD, and ID is kept constant.

Fig 11 Turn ON Characterstics

(b) Turn Off State

51

The description of the turn off procedure for the MOSFET transistor is basically back tracking the turn on steps from the previous section. Start with VGS being equal to VDRV and the current in the device is the full load current represented by IDC in Figure 12. The drain to source voltage is being defined by IDC and the RDS(on) of the MOSFET. The four turn off steps are shown in Figure 12 for completeness. The first time interval is the turn off delay which is required to discharge the CISS capacitance from its initial value to the Miller plateau level. During this time the gate current is supplied by the CISS capacitor itself and it is flowing through the CGS and CGD capacitors of the MOSFET. The drain voltage of the device is slightly increasing as the overdrive voltage is diminishing. The current in the drain is unchanged. In the second period, the drain-to-source voltage of the MOSFET rises from ID vs RDS(on) to the final VDS(off) level where it is clamped to the output voltage by the rectifier diode according to the simplified schematic of Figure 12. During this time period which corresponds to the Miller plateau in the gate voltage waveform the gate current is strictly the charging current of the CGD capacitor because the gate to source voltage is constant. This current is provided by the bypass capacitor of the power stage and it is subtracted from the drain current. The total drain current still equals the load current, i.e. the inductor current represented by the DC current source in Figure 12. The beginning of the third time interval is signified by the turn on of the diode, thus providing an alternative route to the load current. The gate voltage resumes falling from VGS Miller to VTH. The majority of the gate current is coming out of the CGS capacitor, because the CGD capacitor is

52

virtually fully charged from the previous time interval. The MOSFET is in linear operation and the declining gate to source voltage causes the drain current to decrease and reach near zero by the end of this interval. Meanwhile the drain voltage is steady at VDS(off) due to the forward biased rectifier diode. The last step of the turn off procedure is to fully discharge the input capacitors of the device. VGS is further reduced until it reaches 0V. The bigger portion of the gate current similarly to the third turn off time interval, supplied by the CGS capacitor. The drain current and the drain voltage in the device are unchanged. Summarizing the results, it can be concluded that the MOSFET transistor can be switched between its highest and lowest impedance states (either turn-on or turn-off) in four time intervals. The lengths of all four time intervals are a function of the parasitic capacitance values, the required voltage change across them and the available gate drive current. This emphasizes the importance of the proper component selection and optimumgate drive design for high speed, high frequency switching applications. Characteristic numbers for turn on, turn off delays, rise and fall times of the MOSFET switching waveforms are listed in the transistor data sheets. Unfortunately, these numbers correspond to the specific test conditions and to resistive

load,

making

the

comparison

of

different

manufacturers products difficult. Also, switching performance in practical applications with clamped inductive load is significantly different from the numbers.

Power Dissipation and Losses

53

45

The maximum allowable power dissipation that will raise the die temperature to the maximum allowable when the case temperature is held at 250C is important. It is give by Pd where

The switching action in the MOSFET transistor in power applications will result in some unavoidable losses, which can be divided into two categories. The simpler of the two loss mechanisms is the gate drive loss of the device. As described before, turning-on or off the MOSFET involves charging or discharging the CISS capacitor. When the voltage across a capacitor is changing, a certain amount of charge has to be transferred. The amount of charge required to change the gate voltage between 0V and the actual gate drive voltage VDRV, is characterized by the typical gate charge vs. Gate to source voltage curve in the MOSFET.

54

Fig 12. Turn OFF characterstics

This graph gives a relatively accurate worst case estimate of the gate charge as a function of the gate drive voltage. The parameter used to generate the individual curves is the drain-tosource off state voltage of the device. VDS(off) influences the Miller charge the area below the flat portion of the curves thus also, the total gate charge required in a switching cycle. Once the total gate charge is obtained from Figure 6, the gate charge losses can be calculated as

waveform and fDRV is the gate drive frequency which is in most cases equal to the switchingfrequency. It is interesting to notice that the QGfDRV term in the previous equation gives the average bias current required to drive the gate. The power lost to drive the gate of the MOSFET transistor is

55

dissipated in the gate drive circuitry. Referring back to Figures, the dissipating components can be identified as the combination of the series ohmic impedances in the gate drive path. In every switching cycle the required gate charge has to pass through the driver output impedances, the external gate resistor, and the internal gate mesh resistance. As it turns out, the power dissipation is independent of how quicklythe charge is delivered through the resistors.Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed as

Fig 13 Power Losses

46

In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct

56

answers. It is safe to assume that with low value gate resistors (<5Ω) most gate drive losses are dissipated in the driver. If RGATE is sufficiently large to limit IG below the output In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct answers. It is safe to assume that with low value gate resistors (<5Ω) most gate drive losses are dissipated in the driver. If RGATE is sufficiently large to limit IG below the output .

Assuming that IG2 charges the input capacitor of the device from VTH to VGS Miller and IG3 is the discharge current of the CRSS capacitor while the drain voltage changes from

VDS(off)

to 0V, the approximate switching times are

given as

During t2 the drain voltage is VDS(off) and the current is ramping from 0A to the load current, IL while in t3 time interval the drain voltage is falling from VDS(off) to near 0V. Again, using linear approximations of the waveforms he power loss components for the respective time intervals can be estimated.

57

where T is the switching period. The total switching loss is the sum of the two loss components, which yields the following simplifed expression

Even though the switching transitions are well understood, calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components which will significantly alter the current and voltage waveforms, as well as the switching times during the switching procedures. Taking into account the effect of the different source and drain inductances of a real circuit would result in second order differential equations to describe the actual waveforms of the circuit. Since the variables, including gate threshold voltage, MOSFET capacitor values, driver output impedances, etc. have a very wide tolerance, the above described linear approximation seems to be a reasonable enough compromise to estimate switching losses in the MOSFET.

MOS Charge Control Model 47

Well above threshold the charge density of the mobile carriers in the inversion layer can be calculated using the parallel plate charge control model. This model gives an adequate description for the strong inversion regime of the MOS capacitor, but fails for applied voltages near and below threshold (i.e., in the weak inversion and depletion regimes). Several expressions have been proposed for a unified charge control model (UCCM) that covers all the regimes of operation.

where ca = ci is approximately the insulator capacitance per unit area (with a small correction for the finite vertical extent of the inversion channel, see Lee et al. (1993) no = ns(V = VT) is the density of minority carriers per unit

58

area at threshold, and η is the so called subthreshold ideality factor, also known as the subthreshold swing parameter. The ideality factor accounts for the subthreshold division of the applied voltage between the gate insulator and the depletion layer, and 1/η represents the fraction of this voltage that contributes to the interface potential.

Temperature dependence and self heating 48

Since electronic devices and circuits have to operate in different environments, including a wide range of temperatures it is imperative to establish reliable models for such eventualities. Heat generated from power dissipation in an integrated circuit chip can be considerable, and the associated temperature rise must be accounted for both in device and circuit design. In conventional silicon substrates the thermal conductivity is relatively high such that a well-designed chip placed on a good heat sink may achieve a reasonably uniform and tolerable operating temperature. However, such design becomes increasingly difficult as the device dimensions are scaled down and power dissipation increases. The thermal behavior of MOSFETs has been extensively studied in the past, and the temperature dependencies of major model parameters. Circuits fabricated on substrates that are poor heat conductors, such as GaAs and silicon dioxide, are more susceptible to a significant self heating effect. In thin film SOI CMOS, the buried SiO2 layer inhibits an effective heat dissipation, and the self heating manifests itself as a reduced drain current and even as a negative differential conductance at high power inputs. Hence, for a reliable design of SOI circuits, accurate and selfconsistent device models that account for self heating effect are needed for use in circuit simulation.The influence of self heating effect on the electrical characteristics of SOI MOSFETs can be evaluated using a two dimensional device simulator incorporating heat flow or by combining a temperature rise model with an I–V expression through an iteration procedure. But the effect can also be

59

described in terms of a temperature dependent model for the device’s I–V characteristics combined with the following simplified relationship between temperature rise and power dissipation.

Here T is the actual temperature To is the ambient (substrate) temperature, and Rth is a thermal resistance that contains information on thermal conductivity and geometry. The equations can be solved self-consistently, either numerically or analytically. Once the temperature dependence of the device parameters are established, the same procedure can also be used for describing self heating in other types of devices, such as amorphous TFTs. 49

MOSFET Modeling

Analytical or semianalytical MOSFET models are usually based on the

so called gradual channel approximation (GCA). Contrary to the situation in the ideal two terminal MOS device, where the charge density profile is determined from a one-dimensional Poisson’s equation the MOSFET generally poses a two dimensional electrostatic problem. The reason is that the geometric effects and the application of a drain source bias create a lateral electric field component in the channel, perpendicular to the vertical field associated with the ideal gate structure. The GCA states that, under certain conditions, the electrostatic problem of the gate region can be expressed in terms of two coupled one dimensional equations a Poisson’s equation for determining the vertical charge density profile under the gate and a charge transport equation for the channel. This allows us to determine self-consistently both the channel potential and the charge profile at any position along the gate. A direct inspection of the two

dimensional

Poisson’s equation for the channel region shows that the GCA is valid if we can assume that the electric field gradient in the lateral direction of the

60

channel is much less than that in the vertical direction perpendicular to the channel. Typically we find that the GCA is valid for long-channel MOSFET where the ratio between the gate length and the vertical distance of the space charge region from the gate electrode the so called aspect ratio is large. However, if the MOSFET is biased in saturation the GCA always becomes invalid near drain as a result of the large lateral field gradient that develops in this region. In Figure, this is schematically illustrated for a MOSFET in saturation. Next we will discuss three relatively simple MOSFET models the simple charge control model the Meyer model and the velocity saturation model. These models with extensions can be identified with the models denoted as MOSFET Level 1, Level 2, and Level 3. We should note that the analysis that follows is based on idealized device structures. Especially in modern MOSFET/CMOS technology, optimized for high-speed and lowpower applications the devices are more complex. Additional oxide and doping regions are used for the purpose of controlling the threshold voltage and to avoid deleterious effects of high electric fields and so called short and narrow channel phenomena associated with the steady downscaling device dimensions. The GCA states that, under certain conditions, the electrostatic problem of the gate region can be expressed in terms of two coupled one dimensional equations a Poisson’s equation for determining the vertical charge density profile under the gate and a charge transport equation for the channel.

61

Thermal Stability of MOSFET 50

A MOSFET as a single power transistor but it is a collection of thousands of tiny power FET cells connected in parallel. In terms of sharing current, the same application of the positive temperature coefficient applies. In this case, the thermal path between the cells isbetter than that of separate packaged devices, because the cells are all on the same die. As the current density of a small group of cells increases, those cells heat up, increasing the resistivity of those cells and forcing current to flow in neighboring cells, which minimizes the thermal gradient and avoids hot spots. This process is an essential physical tenet that allows the parallel array of cells to function reliably. If the MOSFET exhibits a negative thermal coefficient, today.s parallel cell structure would cause serious reliability issues. In fact, in some modes of operation, the thermal coefficient goes negative. You can easily understand this phenomenon by looking at the transconductance curves for a FET device.A typical set of transconductance curves clearly demonstrates this effect as shown by Figure . Below are curves from three typical devices used in hot swap applications. All three devices shown have one thing in common a point of inflection at which the temperature coefficient is zero. At greater gate to source voltages, the coefficient is positive, and, at lower gate−to−source voltages it is negative. Figure illustrates the change from

62

negative to positive. At a gate to source voltage greater than that of the inflection point (VGS+) a positive temperature coefficient exists. At this gate voltage, the drain conducts more than 9.0 A of current. However, at 125ฐC the drain current reduces to less than 7.0 A. The arrow at the left of Figure which shows the current decreasing due to an increase in temperature indicates this drop. At a gate to source voltage below the inflection point (VGS−) a negative temperature coefficient exists. At −40ฐC the drain current is close to zero. However, at 125ฐC, the drain current is more than 1.0 A. A second arrow at the left of Figure indicates this relationship, and the current rises due to an increase in temperature. The implication is that when you are controlling the FET with a gate to source voltage below the inflection point thermal runaway can occur. When one cell or a small group of cells becomes hotter than the surrounding cells, they tend to conduct more current. This situation, in turn, creates more heat, which allows more current to flow. These cells can pull a large amount of current and, if not limited in time, can cause the device to fail. This situation is similar to the well known phenomenon of secondary breakdown that occurs in bipolar transistors except that a bipolar junction transistor is a single device and you can take steps to avoid its

destruction. A power MOSFET contains

thousands of parallel devices that are internal to the die, and you cannot individually protect them. If hot spots occur, the SOA characteristics of the heavily conducting cells differ greatly from those of the marginally conducting cells. The implication is that when you are controlling the FET with a gate to source voltage below the inflection point thermal runaway can occur. When one cell or a small group of cells becomes hotter than the surrounding cells, they tend to conduct more current.

63

Fig 13. Thermal Stablity of MOSFET

The thermal runaway situation occurs when you use large devices at low current limit settings. Even though it would appear to be desirable to use a very large MOSFET for an application such as a hot swap and limit it to a low current, it may be an inappropriate approach. Use of a very low on resistance device offers low losses for steady state operation but may cause the device to fail during a short circuit or an overload. One way to overcome this problem is to directly sense the die temperature of the MOSFET by integrating the MOSFET with the controller using a monolithic approach. ON Semiconductor takes this approach with its new line of hot swap ICs. In this case, the temperature can be sensed directly on the FET die. The location of the sense element on the die is critical for ensured protection of the device. If a hot spot occurs too far from the sense location, the device may be unable to protect itself. Discrete hot swap controllers employ a number of protection schemes. Thermal instability is an issue only if the controller can go into a constant current mode of operation. Some protection circuits simply shut off the MOSFET switch if a number of conditions indicate a dangerous area of operation. Controllers that use a constant current method of protection can use timers or other

64

schemes along with the current limit circuit to reduce the risk of failure. Because system efficiency is an important parameter it is tempting to use the largest MOSFET possible to reduce losses. It is important to keep in mind, however, that this approach may require you to make a trade off with the system reliability if you are not mindful of the possible thermal instablity. 51

MOSFET Totem Pole Driver

The MOSFET equivalent of the bipolar totempole driver is pictured in

Figure 14. All the benefits mentioned about the bipolar totem pole driver are equally applicable to this implementation. Unfortunately, this circuit has several drawbacks compared to the bipolar version which explain that it is very rarely implemented discretely. The circuit of Figure 11 is an inverting driver, therefore the PWM output signal must be inverted. In addition, the suitable MOSFET transistors are more expensive than the bipolar ones and they will have a large shoot through current when their common gate voltage is in transition. This problem can be circumvented by additional logic or timing components which technique is extensively used in IC implementations.

Fig 14. Totem Pole Driver Circuit.

Speed Enhancement circuits When speed enhancement circuits are mentioned designers exclusively consider circuits which speed-up the turn-off process of the MOSFET. The

65

reason is that the turn-on speed is usually limited by the turn-off, or reverse recovery speed of the rectifier component in the power supply. As discussed with respect to the inductive clamped model in Figure 3, the turn-on of the MOSFET coincides with the turn-off of the rectifier diode. Therefore, the fastest switching action is determined by the reverse recovery characteristic of the diode, not by the strength of the gate drive circuit. In an optimum design the gate drive speed at turn-on is matched to the diode switching characteristic. Considering also that the Miller region is closer to GND than to the final gate drive voltage VDRV, a higher voltage can be applied across the driver output impedance and the gate resistor. Usually the obtained turnon speed is sufficient to drive the MOSFET. The situation is vastly different at turn-off. In theory, the turn-off speed of the MOSFET depends only on the gate drive circuit. A higher current turn-off circuit can discharge the input

capacitors

quicker,

providing

shorter

switching

times

and

consequently lower switching losses. The higher discharge current can be achieved by a lower output impedance MOSFET driver and/or a negative turn-off voltage in case of the common N-channel device. While faster switching can potentially lower the switching losses, the turn-off speed-up circuits increase the ringing in the waveforms due to the higher turnoff di/dt and dv/dt of the MOSFET. This is something to consider in selecting the proper voltage rating and EMI containment for the power device.

MOSFET Amplify Electrical Signals 52

There is a minimum requirement for amplification of electrical signals is power gain, One finds that a device with both voltage and current gain is a highly desirable circuit element. The MOSFET provides current and voltage gain yielding an output current into an external load which exceeds the input current and an output voltage across that external load which exceeds the input voltage. The current gain capability of a Field Effect Transistor (FET) is that no gate current is required to maintain the inversion layer and

66

the resulting current between drain and source. The device has therefore an infinite current gain in DC. The current gain is inversely proportional to the signal frequency reaching unity current gain at the transit frequency.The voltage gain of the MOSFET is caused by the fact that the current saturates at higher drain source voltages. So that a small drain current variation can cause a large drain voltage variation.By this we can amplify electrical signals through MOSFET without using of Amplifying circuit.

Small signal Model 53

So far we have considered large signal MOSFET models which are suitable for digital electronics and for determining the operating point in small signal applications. The small signal regime is of course a very important mode of operation of MOSFET as well as for other active devices. Typically, the AC signal amplitudes are so small relative to the DC values of the operating point that a linear relationship can be assumed between an incoming signal and its response. Normally, if sufficiently accurate large signal models are available the AC designers will use such large signal models also for small signal applications, since this mode is readily available in circuit simulators.However in cases when suitable largesignal models are unavailable or when simple hand calculations are needed, it is convenient to use a dedicated small signal MOSFET model based on a linearized network. An intrinsic common source, small signal model for MOSFET. The model is generalized to include inputs at both the gate and the substrate terminal and the response is observed at the drain (Fonstad 1994). The network elements are obtained as first derivatives of current voltage and charge voltage characteristics resulting in fixed small signal conductances, transconductances, and capacitances for a given operating point. To build a more complete model, some of the extrinsic parasitics may be added including the gate overlap capacitances and the source and drain junction capacitances and the source and drain series resistances. At very

67

high frequencies in the radio frequency (RF) range, the junction capacitances become very important since they couple efficiently to the MOSFET substrate. Other important parasitics in this range are the gate resistance and the series inductances associated with the conducting paths. 54

Types of MOSFET

There are two types of MOSFET which are explained in this report.

(a) Depletion Type MOSFET The Depletion Type MOSFET and the physical construction of a depletion MOSFET is identical to the enhancement MOSFET, with one exception. The conduction channel is physically implanted (rather than induced). Thus for a depletion NMOS transistor, the channel conducts even if VGS=0. If the value of VGS is positive, the channel is further enhanced. That is more free electrons are attracted to the channel, and its conductivity increases. If the value of VGS is negative, free electrons are repelled from the channel! The conductivity of the channel is thus decreased. We call this phenomenon channel depletion. If the value of VGS becomes sufficiently negative all of the free electrons in the channel will be repelled the channel is said to be completely depleted. A channel that is completely depleted cannot conduct. In other words, the depletion MOSFET is in cutoff. Thus the negative value of vGS at which the channel is completely depleted is the threshold voltage Vt for a depletion NMOS device. In other words to have a conducting channel the gate to source voltage VGS must be greater than the threshold voltage. Just like the enhancement NMOS device. Moreover this means that to have a conducting channel the excess gate voltage must be positive. There are just two differences to remember such as

68

(a) The threshold voltage for a depletion NMOS device is negative (i.e., Vt <0). While the threshold voltage for a depletion PMOS device is positive (i.e., Vt > 0). (b) The depletion MOSFET has a slightly different circuit symbol.

(b) Enhancement Mode MOSFET Both the junction FET and the depletion mode MOSFET operate in a generally intuitive manner. In both device types, an electric field is used to deplete the channel of current carriers to one degree or another so that a control voltage will directly affect and control the amount of current flowing through the channel. But what happens if we have a device with no working channel, but with room to put a channel in place. The mechanical structure of this device is shown to the right. In an IC, we would place two n type regions side by side within a p-type area and then place the gate between the n type regions. However, the important region still consists of the two n type regions and the p type area between them. This is the portion we have depicted to the right.With no applied bias, we have what amounts to an npn transistor with no base connection. The two n type regions are isolated from each other and are electrically separate. Even with a voltage applied between the two n type regions, there is no channel present and no current flow. While we still apply the usual positive voltage to the drain with respect to the source, this time we will also apply a positive voltage to the gate region. This has the effect of attracting free electrons towards the gate. The larger the positive gate voltage, the wider its electric field and the more free electrons it will attract.You might not think this would have any effect on the p-type region, where the majority current

69

carriers are holes. However, there are some free electrons here as well. In addition, the source junction is forward biased, so the positive gate voltage can attract electrons across this junction towards the gate.The net result is that the electrons attracted towards the gate actually enhance a channel within the p type region, as shown to the left. This is a channel formed of free electrons, and actually bridges the gap between source and drain. Now we have a channel, which can conduct current from source to drain through the device. Because these devices operate by having a channel enhanced in the semiconductor material where no channel was constructed, they are known as enhancement mode MOSFET. It is just as easy to construct p channel versions of these devices as n channel versions. Indeed CMOS logic IC consist of nothing but these devices constructed and used in pairs such that one will be turned off while the other is turned on. This is the source of the designation CMOS Complementary MOS. Enhancement mode MOSFETs have the same advantages and disadvantages as their depletion-mode cousins. However, when they are constructed as part of an IC rather than as individual devices, they are not readily subject to random static charges. Such ICs are constructed with input protection circuitry for any MOSFET input that must be made accessible to external circuitry.

Advantages 55

They have following advantages such as (a) High input impedance, voltage controlled device easy to drive.To maintain the on state a base drive current which is 1/5th or 1/10th of collector current is required for the current controlled device (BJT) and also a larger reverse base drive current is needed for the high

70

speed turn off of the current controlled device (BJT). Due to these characteristics base drive circuit design becomes complicated and expensive. On the other hand a voltage controlled MOSFET is a switching device which is driven by a channel at the semiconductors surface due to the field effect produced by the voltage applied to the gate electrode which is isolated from the semiconductor surface. As the required gate current during switching transient as well as the on and off states is small, the drive circuit design is simple and less expensive. (b) Unipolar device, majority carrier device and fast switching speed. As there are no delays due to storage and recombination of the minority carrier, as in the BJT,the switching speed is faster than the BJT by orders of magnitude. Hence, it has an advantage in a high frequency operation circuit where switching power loss is prevalent. (c) Wide SOA (safe operating area). It has a wider SOA than the BJT because high voltage and current can be applied simultaneously for a short duration. This eliminates destructive device failure due to second breakdown. (d)

Forward voltage drop with positive temperature coefficient easy to use in parallel.When the temperature increases, the forward voltage drop also increases. This causes the current to flow equally through each device when they are in parallel. Hence, the MOSFET is easier to use in parallel than the BJT, which has a forward voltage drop with negative temperature coefficient.

Disadvantage

(a) In high breakdown voltage devices over 200V, the conduction loss of a MOSFET is larger than that of a BJT which has the same voltage and current rating due to the on-state voltage drop.

Safe Area of Operation

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The MOSFET is not subject to forward or reverse bias second breakdown, which can easily occur in bipolar junction transistors. Second breakdown is a potentially catastrophic condition in bi-polar transistors caused by thermal hot spots in the silicon as the transistor turns on or off. However in the MOSFET, the carriers travel through the device much as if it were a bulk semiconductor, which exhibits a positive temperature coefficient of 0.6%/§C. If current attempts to self-constrict to a localized area, the increasing temperature of the spot will raise the spot resistance due to the positive temperature coefficient of the bulk silicon. The ensuing higher voltage drop will tend to redistribute the current away from the hot spot.As we know that the safe area boundaries are only thermally limited and exhibit no derating for second breakdown. This shows that while the MOSFET transistor is very rugged, it may still be destroyed thermally by forcing it to dissipate too much power.

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Testing a MOSFET

This testing procedure is for use with a digital multimeter in the diode

test range with a minimum of 3.3 volt over d.u.t. (diode-under-test). If your multi-meter is less than that it will not do the test. Check your meter manual for the specs. (a) Hold

the MosFet by the case or the tab but don't touch the metal parts

of the test probes with any of the other MOSFET terminals until needed. Do NOT allow a MOSFET to come in contact with your clothes, plastic or plastic products, etc. because of the high static voltages it can generate. (b) First, (c)

touch the meter positive lead onto the MOSFET Gate.

Now move the positve probe to the Drain. You should get a low reading. The MOSFET internal capacitance on the gate has now been charged up by the meter and the device is turned on.

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the meter positive still connected to the drain touch a finger

between source and gate (and drainif you like, it does not matter at this stage). The gate will be discharged through your finger and the meter reading should go high, indicating a non conductive device. When MOSFET fail they often go short circuit drain to gate. This can put the drain voltage back onto the gate where ofcourse it feeds (via the gate resistors) into the drive circuitry, prossibly blowing that section. It will also get to any other paralleled MOSFET gates, blowing them also. So, if the MosFets are deceased, check the drivers as well! This fact is probably the best reason for adding a source-gate zener diode; zeners fail short circuit and a properly connected zener can limit the damage in a failure! You can also add subminiature gate resistors which tend to fail opencircuit (like a fuse) under this overload, disconnecting the dud MOSFET gate. Dying MOSFET often emit flames or blow-out, even more so in hobby built electronics projects. What that means is that a defective unit can usually be spotted visually. They show a burned hole or something black somewhere. I have seen them alot especially in ups's which can have as many as 8 or more mosfets in parallel. I always replace all of them if a couple are defective plus the drivers. Never use one of those hand held solder-suckers (you know, the ones with a plunger) to desolder. They create enough Electro Static Discharge to destroy a mosfet. Best method is using solder wick or a professional ESD safe desoldering station. A Proximity Switch. This design takes advantage of the ultra high input impedance and powerhandling capabilities of the IRF511 to make a simple, but sensitive, proximity sensor and alarm driver circuit. A 3x3-inch piece of circuit board (or similar size metal object), which functions as the pick-up sensor, is connected to the gate of Q1. A 100 MegaOhm resistor, R2, isolates Q1's gate from R1, allowing the input impedance to remain very high. If a 100 MegaOhm resistor cannot be located, just tie 5 22- MegaOhm resistors in

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series and use that combination for R2. In fact, R2 can be made even higher in value for added sensitivity. Potentiometer R1 is adjusted to a point where the piezo buzzer just begins to sound off and then carefully backed off to the point where the sound ceases. Experimenting with the setting of R1 will help in obtainin the best sensitivity adjustment for the circuit. Potentiometer R1 may be set to a point where the pick up must be contacted to set of the alarm sounder. A relay or other current hungry component can take the place of the piezo sounder to control almost any external circuit. 58

Conclusion

This trainer kit is mainly used in labs for practicals and get benefits for A.I.T. for perform the practical in easier or systematically manner. We have to draw the characterstics between drain current and drain voltage at that time when gate voltage are constant. This report demonstrated a systematic approach to design high performance gate drive circuits for high speed switching applications.This kit is really help to the students for finding out the solutions of FET characterstics. As we know that the Technology is developed day by day. So we are use N channel FET in this kit due to their fast switching applications. This project is minor but it really provide priceless knowledge to the students as practically. By this students also get aware from the terminals of finding out the FET and also measure the values of IDSS and pinch off voltage Vp. If proper drain load is chosen, the output power and efficiency goals for the amplifier stage can be reached. Proper functioning of the circuit in a commercial environment is very much dependent on the quality and selection of the passive parts in the circuit as well as the cooling and load protection systems necessary to support it. By making this project we are really get knowledge about the making of PCB’s because we make a PCB for FET characterstics and learning all objectives which are neccessary to making a PCB. So this plays an valuable thing for student.

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