Ppt Slide1

MULTIPROCESSOR REAL-TIME ANALYSIS A METHODOLOGY OF DSP APPLICATION

Contents  Introduction

to Real -Time Analysis  End to End Methodology –JTAG Scan based mechanism.  Moving from single processor to multiprocessor.  Issues supporting RTA.  Challenges in developing a Methodology.

INTRODUCTION  Analyzing

the execution of real time application is critical to their development and deployment.  Analysis includes timing and logical correctness.

Drawbacks of Traditional Emulator

 Traditional

emulator can’t monitor 32 bit address and data buses.  Traditional emulator needs replacement C.P.U.  High speed of newer D.S.P chips.  D.S.P ’ s have on chip caches, pipelines, memory etc..

Scan-based emulation - Advantages  Emulation

at Full device speed.  Non-intrusive Emulation  In-circuit Emulation  Complete access to system from CPU  Full access to internal memory, caches…..

JTAG Interface  JTAG

architecture includes  4 pins (TAP)  Boundary scan cell is attached to each device  JTAG defines a method called boundary-scan  Used for testing individual devices

Boundary Scan Mechanism  State

of each pin of each device is scanned.  Allows daisy chaining of devices-so entire PC can be scanned.  Input & Output transfers occurs parallely.

Real –Time Analysis  Logic

analysers used in olden days have limitations in the analysis of application behaviour. -Expensive -Tracing application -No data transfer from host to target  Alternative solution is RTA.  It is necessary during development as a means to debug.

Fig 4: Data flow in single processor RTA based upon JTAG emulation

• JTAG provides on chip emulation logic for data transfer from target to host & vice versa  The figure consists of -A Software library -Emulation software driver

 Data

flow in this architecture is bidirectional.  For host to target data transfer there are two distinct paths. 1.target application to RTA host sw lib. 2.RTA host sw lib to host application. • This architecture can be extended to multiprocessor as shown.

 An

RTA software lib must exist on each target.  Data from each processor is scanned upto the host via JTAG interface.  EM sw driver receives data from its corresponding target and delivers data to host sw lib.

End to End Methodology  An

important consideration is performance data identification hardware scalability Data selection ease of use support reliability

CHALLENGES  Emulation

Hardware is different for different families of D.S.P’s.  Some D.S.P’s use interrupt signal for data flow.  D.S.P’s have varying word sizes.

CONCLUSION  This

methodology is widely accepted.  The software that has been developed is able to differentiate between the various D.S.P’s.

QUERIES