Pin Diagram Of 8086

Pin Diagram of 8086 •

•

8086 operates in single processor (minimum mode) or multi processor (maximum mode) configurations to achieve high performance. The 8086 signals can be categorized in 3 groups.

I.

Signals having common functions in minimum as well as maximum mode.

II.

Signals which have special functions for minimum mode.

III.

Signals which have special functions for maximum mode.

I. Signals common for both minimum & maximum mode. 1. AD15-AD0: These are the time multiplexed memory I/O address & data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2,T3,TW,T4. These lines are active high, and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. 2. A19/S6, A18/S4, A17/S4, A16/S3 These are the time multiplexed address and status lines. During T1, these are the most significant address lines for memory operations. During I/O operations these lines are low. The status of the Interrupt Enable Flag (IF) bit (displayed on S5) is updated at the beginning of each clock cycle.

S4, S3 : together indicates which segment register is presently being used for memory access. S4

S3

Indications

0

0

Alternate data

0

1

Stack

1

0

Code or none

1

1

Data

These lines float at tristate off during the local bus hold acknowledge. S6: It is always low. 3. BHE/S7: Bus High Enable/Status The bus high enable signal is used to indicate the transfer of data over the higher order (D15-D8) data bus. If BHE is low then D15-D8 used to transfer data. BHE

A0 Indication

0

0

Whole word i.e AD15 – AD8

0

1

Upper byte from or to i.e AD15-AD8

1

0

Lower byte from or to even address i.e AD7AD0

1

1

None

4. RD: Read Read signal , when low, indicates the peripherals that the processor is performing a memory or I/O operation. RD is active low & shows the state for T2, T3, TW of any read cycle. The signal remains tristated during the ‘hold acknowledge’. 5. READY: This is the acknowledgement from the slow devices or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator. 6. INTR: Interrupt Request: This signal is sampled during the last clock cycle of each instruction to determine the availability of the request. If any interrupt request is pending the processor enters the interrupt acknowledge cycle. 7. TEST: This input is examined by a ‘WAIT’ instruction. If TEST=0, execution will continue, else processor remains in an idle state. Input is synchronized by clock cycle.

8. NMI: Non-Maskable Interrupt The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. 9. RESET: This input causes to processor to terminate the current activity and start execution from FFFF0H i.e reinitialize the system. 10. CLK: Clock Input The clock input provides the basic timing for processor operation and bus control activity. 11. Vcc: +5V power supply for the operation of the internal circuit. 12. GND: Ground for the internal circuit. 13. MN/MX: This pin decides whether the processor is to operate in either minimum or maximum mode.

II. Minimum mode operation of 8086 1.M/I/O: This line becomes active in the previous T4 and remains active till final T4 of the current cycle. 2. INTA: Interrupt Acknowledge This signal is low, the processor has accepted the interrupt. It is active low during T2, T3, Tw of each interrupt acknowledge cycle. 3. ALE: Address Latch Enable This output signal indicates the availability of the valid address on the address/data lines & it is connected to latch enable input of latches. This signal is active high and is never tristated. 4. DT/R: Data transmit/Receive This output is used to decide the direction of data flow through the transreceivers (i.e bidirectional buffers) DT/R = 1 Processor sends out data DT/R = 0 Processor receives data DT/R = S1 in maximum mode.

5. DEN: Data Enable This signal indicates the availability of valid data over the address/data lines. This used to separate data from multiplexed address/data signals. It is active from middle of T2 to middle of T4.

6. HOLD & HLDA: Hold/Hold Acknowledge Hold is high, indicates to the processor that another master is requesting the bus access. After receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle. HOLD is an asynchronous input, it should be externally synchronized .

III.Maximum mode operation of 8086 1.S2, S1, S0: Status lines These lines active during T4 of the previous cycle & remain active during T1 & T2 of the current bus cycle.

2. LOCK: This output pin indicates that other system bus masters will be prevented from gaining the system bus, while the LOCK=0. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. This floats to tri-state off during ‘hold acknowledge’.

3. QS1, QS0 : Queue status These lines give information about the status of the code-prefetch queue. These are active during the CLK cycle after which the queue operation is performed. The 8086 architecture has a 6-byte instruction pre-fetch queue.

4. RQ/GT0, RQ/GT1: Request/Grant These pins are used by other local bus masters, in maximum mode, to force the processor to release the local bus at the end of the processor’s current bus cycle. Each of the pins is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

Memory Interfacing to 8086 Static RAM Interfacing The general procedure of static memory interfacing with 8086 • Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is called ‘odd address memory bank’ and lower 8-bit bank is called ‘even address memory bank’. • Connect available memory address lines of memory chips with those of the microprocessor and also connect the memory RD and WR inputs to the corresponding processor control signals. Connect the 16-bit data bus of the memory bank with that of the microprocessor 8086. • The remaining address lines of the microprocessor, BHE and A0 are used for decoding the required chip select signals for the odd and even memory banks. The CS of memory is derived from the O/P of the decoding circuit.

Need for DMA • In the applications where the microprocessor/CPU is to transfer bulk data, it may be a waste of time to transfer the data from source to destination using program controlled data transfer or Interrupt driven data transfer. • The alternate way of transferring the bulk data is the Direct Memory Access (DMA) technique in which the data is transferred under the control of a DMA controller, after it is properly initialized by the microprocessor/CPU. • A DMA controller is designed to complete the bulk data transfer task much faster than the CPU. • A DMA controller may also be used to transfer data from the system memory to a video RAM of a CRT display. • Data transfer between CPU & FDC may be controlled using DMA controller.

8257 DMA Controller • The DMA mode of data transfer is the fastest amongst all the modes of data transfer. • In this mode, the device may transfer data directly to/from memory without any interference from the CPU/microprocessor. • The device requests the CPU through a DMA controller to hold its data, address & control bus, so that the device may transfer data directly to/from memory. • The DMA data transfer is initiated only after receiving HLDA signal from the CPU. • For facilitating DMA type of data transfer between several device, a DMA Controller may be used.

• Intel’s 8257 is a 4 channel DMA controller designed to be interfaced with their family of microprocessors. • The 8257, on behalf of the devices, requests the CPU for bus access using local bus request input i.e HOLD in minimum mode. In maximum mode RQ/GT pin is used as bus request input. • On receiving the HLDA signal from the CPU, the requesting device gets the access of the bus, and it completes the required no. of DMA cycles for the data transfer and then hands over the control of the bus back to the CPU. Internal Architecture of 8257 • Four I/O devices can independently request for DMA data transfer through four channels at a time. • Each of the four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and terminal count register. There are two common registers for all the channels, namely, mode set register and status register. Thus there are a total of 10 registers. The CPU selects one of these ten register using address lines A0-A3

•DMA Address Registers The function of this register is to store the address of the starting memory location, which will be accessed by the DMA channel. •Terminal Count Register (TC) This 16-bit register is used for ascertaining that the data transfer through a DMA channel ceases or stops after the required no. of DMA cycles. The low order 14-bits of the TC register are initialised with the binary equivalent of the number of required DMA cycles minus one. After each DMA cycle, the TC content will be decremented by one and finally it becomes zero after the required no. of DMA cycles are over. The bits 14 & 15 of this register indicate the type of the DMA operation. •Mode Set Register The function of the mode set register is to enable the DMA channels individually and also to set the various modes of operation (after initializing the DMA address and TC registers appropriately). Bit 15 Bit 14 Type of DMA operation 0 0 Verify DMA Cycle 0 1 Write DMA Cycle 1 0 Read DMA Cycle 1 1 (Illegal)

The bits D0-D3 enable one of the four DMA channels of 8257.