Pic Microcontroller Architecture

PIC Microcontroller

Architecture

Von Neumann Architecture „

„

Fetches instructions and data from same memory Limits operating bandwidth

CPU

8-Bits

Program and Data Memory

Harvard Architecture „

„ „

Two separate memory spaces for instruction and data Increases throughput Different program and data bus widths are possible

CPU

8-Bits 12/14/16-Bits

Program Memory

Data Memory

Instructions „

„

„

Long Word Instructions „ Wider instruction bus Movlw #imm<8> Single Word Instructions 1100XX k k k k k k k k „ Opcodes are 14 bits wide „ No multi byte instruction Single Cycle Instruction „ Entire instruction is fetched in a single cycle

Instructions „

Instruction Pipeline { { {

„

Two stage pipeline Overlaps Fetch & Execute Cycles Each takes one Tcy

Orthogonal Instructions {

Any operation on any register using any addressing mode

Architecture „

Register File Architecture {

{

„

Register File/ Data Memory can be accessed directly or indirectly All SFRs are mapped in data memory

Reduced Instruction Set { {

Instruction set is well designed Highly symmetric (orthogonal)

Instruction Cycle „

OSC1 is internally divided to four nonoverlapping quadrature clock {

Q1, Q2, Q3 and Q4

Clocking Scheme

Instruction Pipeline Flow

Instruction Cycle „

„

„ „

Q1 : Instruction Decode Cycle or Forced no operation Q2 : Instruction Read Data Cycle or No operation Q3 : Process the data Q4 : Instruction Write Data Cycle or No operation

General Instruction Format

Arithmetic Logic Unit „ „

8 bit ALU Capable of { {

„

Addition & Subtraction Logical & Shift operations

ALU

Result affects the status flag bits

Inputs to Arithmetic Logic Unit „

Two operand instructions Operand 1 Working Register

Operand 2

ALU

File Register Immediate constant

„

Single operand instruction { Working register { File Register

INDF TMR0 PCL STATUS FSR PORTA Other SFRs

00 01 02 03 04 05 06

General Purpose Registers (RAM)

20

W Register

ALU & W Register

STATUS register IRP

RP1

RP0

TO

PD

Z

DC

C CARRY DIGIT CARRY ZERO POWER DOWN TIMEOUT REGISTER PAIR 0 REGISTER PAIR 1 INDIRECT REGISTER PAIR

STATUS Register

Architecture Program Memory 8k x 14

Program Counter

File Registers 8 Level Stack

WREG Instruction Register

Instruction Decoder

RAM

Architecture – A subset

OPTION Register

PCON Register