Pic 1
This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA
Overview
Download & View Pic 1 as PDF for free.
More details
- Words: 194
- Pages: 9
PERIPHERAL INTERFACE CONTROLLER
Architectural Features • • • • • • • •
Harvard architecture Long word instructions Single word instructions Single cycle instructions Instruction pipelining Reduced instruction set Register File architecture Orthogonal instructions
Harvard Architecture
Program memory
Data memory
CPU 8
14
•Has program memory and data memory as separate memories. •Both are accessed from separate buses. •These separate buses allows instruction pipelining.
Data memory • Partitioned into multiple banks. • Each bank contains general purpose registers and special function registers. • Each bank extends upto 7Fh. (128 bytes). • Some frequently used SFRs in one bank may be mirrored in another bank for code reduction and easy access.
No. of banks (max)
Base-line
Midrange
High-end
2
4
14
Program memory Reset vector
Interrupt vector
0004h 0005h
On-chip memory
Baseline
Midrange
Highend
Address (max)
8K
8K
2MB
Program counter
13-bit
13-bit
21-bit
000h
Instruction flow/pipelining • Instruction cycle consists of 4 Q cycles. • Fetch takes one instruction cycle while decode and execute takes another instruction cycle. • Due to pipelining, each instruction effectively executes in one cycle.
TCY0
TCY1
Fetch 1
Execute 1 Fetch 2
TCY2
TCY3
Execute 2 Fetch3
Execute 3
Architectural Features • • • • • • • •
Harvard architecture Long word instructions Single word instructions Single cycle instructions Instruction pipelining Reduced instruction set Register File architecture Orthogonal instructions
Harvard Architecture
Program memory
Data memory
CPU 8
14
•Has program memory and data memory as separate memories. •Both are accessed from separate buses. •These separate buses allows instruction pipelining.
Data memory • Partitioned into multiple banks. • Each bank contains general purpose registers and special function registers. • Each bank extends upto 7Fh. (128 bytes). • Some frequently used SFRs in one bank may be mirrored in another bank for code reduction and easy access.
No. of banks (max)
Base-line
Midrange
High-end
2
4
14
Program memory Reset vector
Interrupt vector
0004h 0005h
On-chip memory
Baseline
Midrange
Highend
Address (max)
8K
8K
2MB
Program counter
13-bit
13-bit
21-bit
000h
Instruction flow/pipelining • Instruction cycle consists of 4 Q cycles. • Fetch takes one instruction cycle while decode and execute takes another instruction cycle. • Due to pipelining, each instruction effectively executes in one cycle.
TCY0
TCY1
Fetch 1
Execute 1 Fetch 2
TCY2
TCY3
Execute 2 Fetch3
Execute 3
