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sequential logic means having a clock input connected to receive said master clock pulse signal, having inputs connected to said out receive said clock phase signals, having a demand input connected to a signal source to receive a control signal, having an output c connection of said first means, and operative in the presence of one value of said control signal to apply a terminating signal to said terminate the corresponding ones of said clock pulses, operative in the presence of another value of said control signal to suspend s terminating signal to said control connection to widen selected ones of said clock pulses with respect to said terminated ones of said operative to apply said terminating signal to said control connection in a selected one of said master clock signal pulses following on said suspension of said application took place, thereby to limit the extent of said widening of the widened ones of said clock pulses t said master clock signal pulses to vary the symmetry of said clock phase signals. 14. Clock generator apparatus, comprising
first means having a clock input connection connected to receive a master clock pulse signal, having a control connection, and havin connections, said first means producing in each of said output connections a corresponding one of a group of clock phase signals, ea a series of clock pulses of widths related to the pulse width of said master clock signal, said first means terminating each of said clo appearance of a terminating signal at said control connection, and
sequential logic means having a clock input connected to receive said master clock pulse signal, having inputs connected to said out receive said clock phase signals, having a demand input connected to a signal source to receive a control signal, having an output c connection of said first means, and operative to apply a terminating signal to said control connection in the presence of specific one terminate the latter with a fixed width, operative to suspend said application of said terminating signal to said control connection in remainder of said clock pulses to widen the latter with respect to said specific ones of said clock pulses, operative in the presence of control signal to suspend said application of said terminating signal to said control connection to widen selected ones of said specific pulses with respect to the terminated ones of said clock pulses, and operative to apply said terminating signal to said control connec said master clock signal pulses following one of the latter in which said suspension of said application took place, thereby to limit th widening of the widened ones of said clock pulses to a selected number of said master clock signal pulses to impart a varying nonsy phase signals
sequential logic means having a clock input connected to receive said master clock pulse signal, having inputs connected to said out receive said clock phase signals, having a demand input connected to a signal source to receive a control signal, having an output c connection of said first means, and operative in the presence of one value of said control signal to apply a terminating signal to said terminate the corresponding ones of said clock pulses, operative in the presence of another value of said control signal to suspend s terminating signal to said control connection to widen selected ones of said clock pulses with respect to said terminated ones of said operative to apply said terminating signal to said control connection in a selected one of said master clock signal pulses following on said suspension of said application took place, thereby to limit the extent of said widening of the widened ones of said clock pulses t said master clock signal pulses to vary the symmetry of said clock phase signals. 14. Clock generator apparatus, comprising
first means having a clock input connection connected to receive a master clock pulse signal, having a control connection, and havin connections, said first means producing in each of said output connections a corresponding one of a group of clock phase signals, ea a series of clock pulses of widths related to the pulse width of said master clock signal, said first means terminating each of said clo appearance of a terminating signal at said control connection, and
sequential logic means having a clock input connected to receive said master clock pulse signal, having inputs connected to said out receive said clock phase signals, having a demand input connected to a signal source to receive a control signal, having an output c connection of said first means, and operative to apply a terminating signal to said control connection in the presence of specific one terminate the latter with a fixed width, operative to suspend said application of said terminating signal to said control connection in remainder of said clock pulses to widen the latter with respect to said specific ones of said clock pulses, operative in the presence of control signal to suspend said application of said terminating signal to said control connection to widen selected ones of said specific pulses with respect to the terminated ones of said clock pulses, and operative to apply said terminating signal to said control connec said master clock signal pulses following one of the latter in which said suspension of said application took place, thereby to limit th widening of the widened ones of said clock pulses to a selected number of said master clock signal pulses to impart a varying nonsy phase signals
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