Orkom Bus-bus Sistem_lanjutan
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Bus-Bus Sistem (Lanjutan) Maria Susan Anggreainy, M.Kom
09/03/2008
Maria Susan Anggreainy, M.Kom
1
Struktur Interkoneksi
09/03/2008
Kumpulan lintasan yang menghubungkan berbagai modul Komputer terdiri dari sekumpulan komponen-komponen atau modulmodul tiga jenis dasar (CPU, memori, dan I/O) yang salang berkomunikas satu sama lainnya
Maria Susan Anggreainy, M.Kom
2
Struktur Interkoneksi harus mendukung jenis perpindahan berikut: Memori ke CPU CPU ke Memori I/O ke CPU CPU ke I/O I/O ke Memori atau dari Memori
09/03/2008
Maria Susan Anggreainy, M.Kom
3
Computer Modules
09/03/2008
Maria Susan Anggreainy, M.Kom
4
Memory Connection
Receives and sends data Receives addresses (of locations) Receives control signals Read z Write z Timing z
09/03/2008
Maria Susan Anggreainy, M.Kom
5
Input/Output Connection(1)
Similar to memory from computer’s viewpoint Output Receive data from computer z Send data to peripheral z
Input Receive data from peripheral z Send data to computer z
09/03/2008
Maria Susan Anggreainy, M.Kom
6
Input/Output Connection(2)
Receive control signals from computer Send control signals to peripherals z
Receive addresses from computer z
09/03/2008
e.g. spin disk
e.g. port number to identify peripheral Maria Susan Anggreainy, M.Kom
Send interrupt signals (control)
7
CPU Connection
09/03/2008
Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts
Maria Susan Anggreainy, M.Kom
8
Buses
09/03/2008
There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP) Maria Susan Anggreainy, M.Kom
9
What is a Bus?
A communication pathway (lintasan komunikasi) connecting two or more devices Usually broadcast Often grouped A number of channels in one bus z e.g. 32 bit data bus is 32 separate single bit channels z
09/03/2008
Power lines may not be shown Maria Susan Anggreainy, M.Kom
10
System Bus
09/03/2008
Sebuah bus yang menghubungkan komponenkomponen utama komputer (CPU, Memori dan I/O) disebut bus sistem.
Maria Susan Anggreainy, M.Kom
11
Struktur Bus
09/03/2008
Biasanya terdiri dari 50 sampai 100 saluran yang terpisah. Masing-masing saluran umumnya hanya dapat membawa 1 bit. Masing-masing saluran ditandai dengan arti dan fungsi khusus Fungsi saluran bus dapat diklasifikasikan menjadi tiga kelompok : data, alamat dan kontrol Selain itu, mungkin ada saluran distribusi daya Maria Susan Anggreainy, M.Kom
12
Data Bus
Carries data z
Width is a key determinant of performance z
09/03/2008
Remember that there is no difference between “data” and “instruction” at this level
8, 16, 32, 64 bit
Bila bus data lebarnya 8 bit, dan setiap instruksi panjangnya 16 bit, maka CPU harus dua kali mengakses modul Memori untuk setiap siklus instruksinya. Maria Susan Anggreainy, M.Kom
13
Address bus
Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Lebar bus menentukan kapasitas memori maksimum. Bus width determines maximum memory capacity of system z
09/03/2008
e.g. 8080 has 16 bit address bus giving 64k address space
Umumnya juga dipakai juga untuk mengalamati port-port I/O. Misal : pada bus 8 bit, alamat 01111111 kebawah untuk mengalamati memori (128 alamat) dan 10000000 keatas untuk modul I/O Maria Susan Anggreainy, M.Kom
14
Control Bus Untuk mengontrol akses ke address bus dan penggunaan data bus serta address bus (karena keduanya dipakai bersama) Control and timing information
Memory read/write signal z Interrupt request z Clock signals z
09/03/2008
Maria Susan Anggreainy, M.Kom
15
Bus Interconnection Scheme
09/03/2008
Maria Susan Anggreainy, M.Kom
16
Operasi bus
Bila sebuah modul akan mengirimkan data ke modul lainnya : (1) Memperoleh penggunaan bus z (2) Memindahkan data melalui bus z
09/03/2008
Maria Susan Anggreainy, M.Kom
17
Big and Yellow?
What do buses look like? Parallel lines on circuit boards z Ribbon cables z Strip connectors on mother boards z
e.g.
z
09/03/2008
PCI
Sets of wires
Maria Susan Anggreainy, M.Kom
18
Single Bus Problems
Lots of devices on one bus leads to: z
Propagation delays (semakin besar waktu yang diperlukan perangkat untuk mengkoordinasi penggunaan bus)
09/03/2008
Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems Maria Susan Anggreainy, M.Kom
19
Traditional (ISA) (with cache)
09/03/2008
Maria Susan Anggreainy, M.Kom
20
High Performance Bus (arsitektur ini sering dikenal dengan nama arsitektur mezzanine)
09/03/2008
Maria Susan Anggreainy, M.Kom
21
Elemen-elemen rancangan bus
Jenis (tipe) z z
Metode Arbitrasi z z
z
z
Address Data
Jenis Transfer Data z z z z z
09/03/2008
Synchronous Asynchronous
Lebar Bus z
Tersentralisasi Terdistribusi
Timing z
Dedicated Multiplexed
Read Write Read-Modify-write Read-alter-write Block Maria Susan Anggreainy, M.Kom
22
Bus Types
Dedicated z
Separate data & address lines
Multiplexed Shared lines z Address valid or data valid control line z Advantage - fewer lines z Disadvantages z
More 09/03/2008
complex control Susan Anggreainy, M.Kom Maria Ultimate performance
23
Bus Arbitration
09/03/2008
More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed Maria Susan Anggreainy, M.Kom
24
Centralised Arbitration
Single hardware device controlling bus access Bus Controller z Arbiter z
09/03/2008
May be part of CPU or separate
Maria Susan Anggreainy, M.Kom
25
Distributed Arbitration
09/03/2008
Each module may claim the bus Control logic on all modules
Maria Susan Anggreainy, M.Kom
26
Timing
Co-ordination of events on bus Synchronous Events determined by clock signals z Control Bus includes clock line z A single 1-0 is a bus cycle z All devices can read clock line z Usually sync on leading edge z Usually a single cycle for an event z
09/03/2008
Maria Susan Anggreainy, M.Kom
27
Synchronous Timing Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
28
Asynchronous Timing – Read Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
29
Asynchronous Timing – Write Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
30
Lebar Bus
09/03/2008
Data Bus Address Bus
Maria Susan Anggreainy, M.Kom
31
Jenis Transfer Data
09/03/2008
Maria Susan Anggreainy, M.Kom
32
PCI Bus
09/03/2008
Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines
Maria Susan Anggreainy, M.Kom
33
PCI Bus Lines (required)
Systems lines z
Including clock and reset
Address & Data 32 time mux lines for address/data z Interrupt & validate lines z
Interface Control Arbitration Not shared z Direct connection to PCI bus arbiter z
09/03/2008
Maria Susan Anggreainy, M.Kom
34
PCI Bus Lines (Optional)
Interrupt lines z
Not shared
Cache support 64-bit Bus Extension Additional 32 lines z Time multiplexed z 2 lines to enable devices to agree to use 64-bit transfer z
09/03/2008
JTAG/Boundary Scan Maria Susan Anggreainy, M.Kom
z
For testing procedures
35
PCI Commands
Transaction between initiator (master) and target Master claims bus Determine type of transaction z
09/03/2008
e.g. I/O read/write
Address phase One or more data phases Maria Susan Anggreainy, M.Kom
36
PCI Read Timing Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
37
PCI Bus Arbitration
09/03/2008
Maria Susan Anggreainy, M.Kom
38
Foreground Reading
09/03/2008
Stallings, chapter 3 (all of it) www.pcguide.com/ref/mbsys/bu ses/ In fact, read the whole site! www.pcguide.com/
Maria Susan Anggreainy, M.Kom
39
09/03/2008
Maria Susan Anggreainy, M.Kom
1
Struktur Interkoneksi
09/03/2008
Kumpulan lintasan yang menghubungkan berbagai modul Komputer terdiri dari sekumpulan komponen-komponen atau modulmodul tiga jenis dasar (CPU, memori, dan I/O) yang salang berkomunikas satu sama lainnya
Maria Susan Anggreainy, M.Kom
2
Struktur Interkoneksi harus mendukung jenis perpindahan berikut: Memori ke CPU CPU ke Memori I/O ke CPU CPU ke I/O I/O ke Memori atau dari Memori
09/03/2008
Maria Susan Anggreainy, M.Kom
3
Computer Modules
09/03/2008
Maria Susan Anggreainy, M.Kom
4
Memory Connection
Receives and sends data Receives addresses (of locations) Receives control signals Read z Write z Timing z
09/03/2008
Maria Susan Anggreainy, M.Kom
5
Input/Output Connection(1)
Similar to memory from computer’s viewpoint Output Receive data from computer z Send data to peripheral z
Input Receive data from peripheral z Send data to computer z
09/03/2008
Maria Susan Anggreainy, M.Kom
6
Input/Output Connection(2)
Receive control signals from computer Send control signals to peripherals z
Receive addresses from computer z
09/03/2008
e.g. spin disk
e.g. port number to identify peripheral Maria Susan Anggreainy, M.Kom
Send interrupt signals (control)
7
CPU Connection
09/03/2008
Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts
Maria Susan Anggreainy, M.Kom
8
Buses
09/03/2008
There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP) Maria Susan Anggreainy, M.Kom
9
What is a Bus?
A communication pathway (lintasan komunikasi) connecting two or more devices Usually broadcast Often grouped A number of channels in one bus z e.g. 32 bit data bus is 32 separate single bit channels z
09/03/2008
Power lines may not be shown Maria Susan Anggreainy, M.Kom
10
System Bus
09/03/2008
Sebuah bus yang menghubungkan komponenkomponen utama komputer (CPU, Memori dan I/O) disebut bus sistem.
Maria Susan Anggreainy, M.Kom
11
Struktur Bus
09/03/2008
Biasanya terdiri dari 50 sampai 100 saluran yang terpisah. Masing-masing saluran umumnya hanya dapat membawa 1 bit. Masing-masing saluran ditandai dengan arti dan fungsi khusus Fungsi saluran bus dapat diklasifikasikan menjadi tiga kelompok : data, alamat dan kontrol Selain itu, mungkin ada saluran distribusi daya Maria Susan Anggreainy, M.Kom
12
Data Bus
Carries data z
Width is a key determinant of performance z
09/03/2008
Remember that there is no difference between “data” and “instruction” at this level
8, 16, 32, 64 bit
Bila bus data lebarnya 8 bit, dan setiap instruksi panjangnya 16 bit, maka CPU harus dua kali mengakses modul Memori untuk setiap siklus instruksinya. Maria Susan Anggreainy, M.Kom
13
Address bus
Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Lebar bus menentukan kapasitas memori maksimum. Bus width determines maximum memory capacity of system z
09/03/2008
e.g. 8080 has 16 bit address bus giving 64k address space
Umumnya juga dipakai juga untuk mengalamati port-port I/O. Misal : pada bus 8 bit, alamat 01111111 kebawah untuk mengalamati memori (128 alamat) dan 10000000 keatas untuk modul I/O Maria Susan Anggreainy, M.Kom
14
Control Bus Untuk mengontrol akses ke address bus dan penggunaan data bus serta address bus (karena keduanya dipakai bersama) Control and timing information
Memory read/write signal z Interrupt request z Clock signals z
09/03/2008
Maria Susan Anggreainy, M.Kom
15
Bus Interconnection Scheme
09/03/2008
Maria Susan Anggreainy, M.Kom
16
Operasi bus
Bila sebuah modul akan mengirimkan data ke modul lainnya : (1) Memperoleh penggunaan bus z (2) Memindahkan data melalui bus z
09/03/2008
Maria Susan Anggreainy, M.Kom
17
Big and Yellow?
What do buses look like? Parallel lines on circuit boards z Ribbon cables z Strip connectors on mother boards z
e.g.
z
09/03/2008
PCI
Sets of wires
Maria Susan Anggreainy, M.Kom
18
Single Bus Problems
Lots of devices on one bus leads to: z
Propagation delays (semakin besar waktu yang diperlukan perangkat untuk mengkoordinasi penggunaan bus)
09/03/2008
Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity
Most systems use multiple buses to overcome these problems Maria Susan Anggreainy, M.Kom
19
Traditional (ISA) (with cache)
09/03/2008
Maria Susan Anggreainy, M.Kom
20
High Performance Bus (arsitektur ini sering dikenal dengan nama arsitektur mezzanine)
09/03/2008
Maria Susan Anggreainy, M.Kom
21
Elemen-elemen rancangan bus
Jenis (tipe) z z
Metode Arbitrasi z z
z
z
Address Data
Jenis Transfer Data z z z z z
09/03/2008
Synchronous Asynchronous
Lebar Bus z
Tersentralisasi Terdistribusi
Timing z
Dedicated Multiplexed
Read Write Read-Modify-write Read-alter-write Block Maria Susan Anggreainy, M.Kom
22
Bus Types
Dedicated z
Separate data & address lines
Multiplexed Shared lines z Address valid or data valid control line z Advantage - fewer lines z Disadvantages z
More 09/03/2008
complex control Susan Anggreainy, M.Kom Maria Ultimate performance
23
Bus Arbitration
09/03/2008
More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed Maria Susan Anggreainy, M.Kom
24
Centralised Arbitration
Single hardware device controlling bus access Bus Controller z Arbiter z
09/03/2008
May be part of CPU or separate
Maria Susan Anggreainy, M.Kom
25
Distributed Arbitration
09/03/2008
Each module may claim the bus Control logic on all modules
Maria Susan Anggreainy, M.Kom
26
Timing
Co-ordination of events on bus Synchronous Events determined by clock signals z Control Bus includes clock line z A single 1-0 is a bus cycle z All devices can read clock line z Usually sync on leading edge z Usually a single cycle for an event z
09/03/2008
Maria Susan Anggreainy, M.Kom
27
Synchronous Timing Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
28
Asynchronous Timing – Read Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
29
Asynchronous Timing – Write Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
30
Lebar Bus
09/03/2008
Data Bus Address Bus
Maria Susan Anggreainy, M.Kom
31
Jenis Transfer Data
09/03/2008
Maria Susan Anggreainy, M.Kom
32
PCI Bus
09/03/2008
Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines
Maria Susan Anggreainy, M.Kom
33
PCI Bus Lines (required)
Systems lines z
Including clock and reset
Address & Data 32 time mux lines for address/data z Interrupt & validate lines z
Interface Control Arbitration Not shared z Direct connection to PCI bus arbiter z
09/03/2008
Maria Susan Anggreainy, M.Kom
34
PCI Bus Lines (Optional)
Interrupt lines z
Not shared
Cache support 64-bit Bus Extension Additional 32 lines z Time multiplexed z 2 lines to enable devices to agree to use 64-bit transfer z
09/03/2008
JTAG/Boundary Scan Maria Susan Anggreainy, M.Kom
z
For testing procedures
35
PCI Commands
Transaction between initiator (master) and target Master claims bus Determine type of transaction z
09/03/2008
e.g. I/O read/write
Address phase One or more data phases Maria Susan Anggreainy, M.Kom
36
PCI Read Timing Diagram
09/03/2008
Maria Susan Anggreainy, M.Kom
37
PCI Bus Arbitration
09/03/2008
Maria Susan Anggreainy, M.Kom
38
Foreground Reading
09/03/2008
Stallings, chapter 3 (all of it) www.pcguide.com/ref/mbsys/bu ses/ In fact, read the whole site! www.pcguide.com/
Maria Susan Anggreainy, M.Kom
39
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