Ocw1-3(8259)

Lecture-63 OCW2 (Operation Control Word 3): As discussed earlier, OCW3 is also issued to even address, i.e., address with A0 = 0 and it is differentiated with OCW2 by bit D3 which is „0‟ in OCW2 and „1‟ in OCW3. The format of OCW3 is shown below: D7 0

D6

D5

ESMM SMM

D4

D3

D2

D1

D0

0

1

P

RR RIS

The combination of different bits decides the mode in which Intel 8259A will operate. This control word is used to sent/reset Special Mask mode, Polling command and to decide the source of read register. ESMM 0 0 1 1 RR 0 0 1 1

RIS 0 1 0 1

SMM 0 1 0 1

Operation No Action No-Action Reset Special Mask Mode Set Special Mask Mode

Operation No Action No-Action Read Interrupt Request Register on next RD pulse Read In-service Register on next RD pulse P 0 1

Operation No Poll Command Poll Command

Special Mask Mode: Some application may require interrupt service routine to dynamically after the system interrupts priority structure during its execution under software control. For example, it may be required to inhibit lower priority requests for a portion of its interrupt subroutine execution but enable some of them for another portion. The difficulty in normal operation of 8259A is that if an interrupt request is acknowledged and an End of Interrupt command has not been issued to reset its ISR bit (i.e.,while executing a service routine), the 8259A would have inhibited all lower priority requests. There is no easy way for the Interrupt service subroutine to enable them. Under such condition, 8259A can be commanded to operate in special mask mode. If the chip is programmed to operate in special mask mode using OCW3 and an interrupt is acknowledged, it inhibits further interrupt at that level and enables all interrupts at other levels (lower as well as higher) that are not masked. Thus, any interrupts may be selectively enabled by loading the mask register. In other words, the lower priority interrupts to be allowed to interrupt the processor during the execution are unmasked. It is to be noted, that operation of higher priority interrupts are not affected. In any case, same priority interrupt will not be acknowledged aslongas the corresponding ISR bit is set. The special mask mode is set by OCW3 where ESMM=1, SMM=1, and cleared where ESMM=1, SMM=0.

Poll Command: As stated earlier, eight 8259As can be used in master-slave configuration mode to handle 64 interrupts at the most. No further cascading is possible. If more than 64 interrupts are to be used in a system or the interrupt structure of the processor is not to be used, 8259A can be used in polling mode. In this mode, 8259A is interfaced with the processor without using interrupt, i.e, INT output of 8259A is not connected to the microprocessor interrupt and INTA of the chip is left open (NC). The microprocessor internal interrupt enable flip-flop is reset; disabling its interrupt input, service to device is achieved by software using a poll command. The poll command is issued by setting P = 1 in OCW3. After issuing OCW3, the status of interrupts is read from even address. The RD=0 and CS=0 issued acts as an interrupt acknowledge signal, sets the appropriate ISR bit if there is an interrupt request, and reads the 8-bit data indicating the highest priority interrupt active. The data put onto the data bus during RD is D7

D6

D5

D4

D3

D2

D1

D0

I

-

-

-

-

W2

W1

W0

W2–W0 bits indicate the binary code of the highest priority level requesting service. I is equal to „1‟ if there is one or more interrupt(s) requesting service. If there is no interrupt active, I is equal to zero. In this case, W2–W0 bits are redundant.

Interrupt is frozen from WR signal issued to send Poll command to RD signal issued to read the 8-bit data. This mode is useful if there is a routine common to its several levels so that the INTA sequence is not needed to save memory space. Another application is to use the poll mode to expand the number of priority levels to more than 64 as stated earlier.

Reading the 8259A status: The input status of several internal registers can be read to update the user information on the system. The following internal registers can be read as and when required to know the status of interrupts: Interrupt Request Register (IRR): It is an 8-bit register which contains the interrupt levels, requesting service, to be acknowledged. The bits set in interrupt request register gives the status of pending interrupts. The highest interrupt request level is reset from the IRR when an interrupt is acknowledged. This register is not affected by IMR. In- Service Register (ISR): It is an 8-bit register which contains the interrupt levels that are being serviced by the processor. Remember, 8259A allows a higher priority interrupt to be acknowledged even if lower priority interrupt is being serviced provided the processor does not block the new interrupt. The ISR bit is reset when an End of Interrupt command is issued. Interrupt Mask Register (IMR): It is also an 8-bit register which contains the interrupt requests masked.

These three registers can be read from the two address assigned to 8259A – even address (A0 = 0) and odd address (A0 = 1). The interrupt mask register IMR, no OCW3 is needed. Since this register is set by issuing OCW1 to odd address, therefore, whenever, information is read from odd address, the PIC releases the content of IMR giving the status of interrupts masked/unmasked. The interrupt request register (IRR) and in-service register (ISR) can be read from even address. By default, just after initialization the 8259A is set to IRR. It means, if no OCW3 is issued and information is read from even address, the 8259A releases the status of pending interrupts from IRR. The ISR can be read when, prior to the RD pulse issued to 8259A, a read register command is issued with OCW3 making RR=1 and RIS=1. Later on, if again IRR is to be read, a read register command is required to be issued with OCW3 making RR=1 and RIS=0. There is no need to write an OCW3 before every status read operation, as long as the status read corresponds with the previous one, i.e., the IRR or ISR has been previously selected by the OCW3. It is to be noted that if the chip is being used in polling mode, the status of interrupts need to be read from even address. Polling over side status read when P=1, RR=1 in OCW3. Therefore, whenever, polling command has been issued, the next read operation from even address gets the status of highest priority interrupt active and not the status of IRR or ISR. But subsequent read operation from even address gives the status of either pending interrupts (IRR) or inservice interrupts (ISR) as set earlier. To get the status of highest

interrupt active in polling mode, OCW3 need to be issued every time before reading the status.

Edge & Level Triggered Modes: This mode is programmed using bit D3 (LTIM) in ICW1. If LTIM=0, the 8259A is programmed in edge triggered mode and an interrupt request will be recognized by a low to high transition on an IR input. The IR input can remain high without generatively another interrupt. If LTIM=1, the chip is programmed in level triggered mode and an interrupt request will be recognized by a high level on IR input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued or the CPU interrupt is enabled to prevent a second interrupt from occurring. In both the edge & level triggered modes, the IR input must remain high until after the falling edge of the first INTA as discussed earlier. In fact, the interrupt being acknowledged is rechecked when first INTA signal is received by 8259A. If the IR input goes low before this time, it is considered an interrupt due to noise and a DEFAULT INT will occur when the CPU acknowledges the interrupt. In this case, the 8259A reset the corresponding IRR bit but does not set the corresponding ISR bit. Further, the chip releases the address of IR7 irrespective of noise occurring at any interrupt input. This can be a useful safe guard for detecting interrupts caused by spurious noise glitches on the IR inputs.

To implement this feature, i.e., detection of noise, the IR7 routine is used for “clean up”, thus ignoring the interrupts. There are three possibilities in case of default interrupt as below: Case 1: IR7 is not being used in the application. In this case, there is no issue EOI command as ISR7 bit will not be set due to default interrupt. Only the interrupt structure of processor is to be enabled before returning from the subroutine. ISS7 Enter

Enable Interrupt

Return

Fig.11.6(a) Default ISS- IR7 interrupt Not Used

Case 2: IR7 is needed for the other purpose in the application but IR7 is not current being serviced. In this case, a default IR7 can still be detected by reading the ISR. ISS7 Enter

Is ISR7 =1 ? No Enable Interrupt

Return

Yes

Normal IR7 Subroutine

Issue EOI Enable Interrupt

Return

Fig.11.6(b) Default ISS- IR7 used but not active

A normal IR7 interrupt will set the corresponding ISR bit, a default IR7 won‟t. Therefore, whenever the control is transferred to subroutine for IR7, the ISR is read and ISR7 bit is checked to determine whether it is due to normal IR7 or due to default interrupt. Case 3: A default IR7 routine occurs during the execution of normal IR7 routine. In this the control will again be transferred to IR7 subroutine but the ISR7 bit will remain set. In this case it is necessary to keep track of whether or not the IR7 routine was previously entered. If another IR7 occurs it is a default. It can be done by using an index, say INDEX, which is made „0‟ in the beginning and whenever, a normal IR7 interrupt is acknowledged, it is set to „1‟ and after serving the routine it is reset to „0‟. Thus, during the execution of normal IR7 routine, if default interrupt comes, this index is checked and if found set, it means the new interrupt is default interrupt and should be ignored.

ISS7 Enter

Is ISR7 =1 ?

Yes No

No Enable Interrupt

Is Index =1 ?

Yes Set Index =1 Return Normal IR7 Subroutine

Issue EOI Enable Interrupt

Return

Fig.11.6(c) Default ISS - Interrupt IR7 is in Service