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Non-return-to-zero From Wikipedia, the free encyclopedia (Redirected from NRZI) Jump to: navigation, search

The binary signal is encoded using rectangular pulse amplitude modulation with polar non-return-to-zero code In telecommunication, a non-return-to-zero (NRZ) line code is a binary code in which "1s" are represented by one significant condition and "0s" are represented by some other significant condition, with no other neutral or rest condition. The pulses have more energy than a RZ code. Unlike RZ, NRZ does not have a rest state. NRZ is not inherently a self-synchronizing code, so some additional synchronization technique (perhaps a run length limited constraint, or a parallel synchronization signal) must be used to avoid bit slip. For a given data signaling rate, i.e., bit rate, the NRZ code requires only half the bandwidth required by the Manchester code. When used to represent data in an asynchronous communication scheme, the absence of a neutral state requires other mechanisms for data recovery, to replace methods used for error detection when using synchronization information when a separate clock signal is available. NRZ-Level itself is not a synchronous system but rather an encoding that can be used in either a synchronous or asynchronous transmission environment, that is, with or without an explicit clock signal involved. Because of this, it is not strictly necessary to discuss how the NRZ-Level encoding acts "on a clock edge" or "during a clock cycle" since all transitions happen in the given amount of time representing the actual or implied integral clock cycle. The real question is that of sampling--the high or low state will be received correctly provided the transmission line has stabilized for that bit when the physical line level is sampled at the receiving end. However, it is handy to see NRZ transitions as happening on the trailing (falling) clock edge in order to compare NRZ-Level to other encoding methods, such as the mentioned Manchester code, which requires clock edge information (is the XOR of the clock and NRZ, actually) and to see the difference between NRZ-Mark and NRZ-Inverted.

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[edit] Unipolar Non-Return-to-Zero Level

Main article: On-off keying "One" is represented by one physical level (such as a DC bias on the transmission line). "Zero" is represented by another level (usually a positive voltage).

In clock language, "one" transitions or remains high on the trailing clock edge of the previous bit and "zero" transitions or remains low on the trailing clock edge of the previous bit, or just the opposite. This allows for long series without change, which makes synchronization difficult. One solution is to only send bytes with lots of transitions, see RLL. The diagram shows a line representing the physical zero below the biased logical zero-showing the less usual case of "one" being a high voltage.

[edit] Bipolar Non-Return-to-Zero Level "One" is represented by one physical level (usually a negative voltage). "Zero is represented by another level (usually a positive voltage). In clock language, in bipolar NRZ-Level the voltage "swings" from positive to negative on the trailing edge of the previous bit clock cycle. An example of this is RS-232, where "one" is -5V to -12V and "zero" is +5 to +12V.

[edit] Non-Return-to-Zero Mark Non-Return-to-Zero Mark "One" is represented by a change in physical level. "Zero" is represented by no change in physical level. In clock language, the physical level transitions on the trailing clock edge of the previous bit to represent a "one." No transition occurs for a "zero." When looking at the diagrams for transition-based encoding, it is important to realize that they might be inverted or partially inverted if the physical state were assumed to be the opposite just before the first bit in the diagram.

This encoding is commonly referred to as just "NRZ" in other contexts[1]; FIPS 1037 also lists "non-return-to-zero change-on-ones" and "non-return-to-zero one" as encoding names that seem to mean the same thing.

[edit] Non-Return-to-Zero Space "One" is represented by no change in physical level. "Zero" is represented by a change in physical level. In clock language, the level transitions on the trailing clock edge of the previous bit to represent a "zero." This "change-on-zero" is used by High-Level Data Link Control and USB. They both avoid long periods of no transitions (even when the data contains long sequences of 1 bits) by using zero-bit insertion. HDLC transmitters insert a 0 bit after five contiguous 1 bits (except when transmitting the frame delimiter '01111110'). USB transmitters insert a 0 bit after six consecutive 1 bits. The receiver at the far end uses every transition -- both from 0 bits in the data and these extra non-data 0 bits -- to maintain clock synchronization. The receiver otherwise ignores these non-data 0 bits.

[edit] Non-Return-to-Zero Inverted (NRZI) Example NRZI encoding NRZI-transition occurs for a zero Non return to zero, inverted (NRZI) is a method of mapping a binary signal to a physical signal for transmission over some transmission media. The two level NRZI signal has a transition at a clock boundary if the bit being transmitted is a logical one, and does not have a transition if the bit being transmitted is a logical zero. "One" is represented by a transition of the physical level. "Zero" has no transition. Also, NRZI might take the opposite convention, as in USB signalling, when in Mode 1 (transition when signalling zero and steady level when signalling one). The transition occurs on the leading edge of the clock for the given bit. This distinguishes NRZI from NRZ-Mark. However, even NRZI can have long series of zeros (or ones if transitioning on "zero"), so clock recovery can be difficult unless some other encoding is used on top of it (such as RLL). Manchester encoding always reflects a clock edge, but it is less efficient than NRZI.

NRZI encoding is used for recording on magnetic tape and for data transmission in the standard USB. Note that USB injects a transition if 6 bits were the same.

El acrónimo SDLC (del inglés Syncronous Data Link Controller, controlador de enlace de datos síncrono) se utiliza para nombrar el protocolo diseñado por IBM para enlaces síncronos a través de una línea para la capa 2 del modelo OSI de comunicaciones. Como su nombre implica, es un protocolo síncrono, lo que supone la transmisión de la señal de reloj con los datos.

Synchronous Data Link Control From Wikipedia, the free encyclopedia Jump to: navigation, search Synchronous Data Link Control (SDLC) is a computer communications protocol. It is the layer 2 protocol for IBM's Systems Network Architecture (SNA). SDLC supports multipoint links as well as error correction. It also runs under the assumption that an SNA header is present after the SDLC header.[1]. SDLC was mainly used by IBM mainframe and midrange systems; however implementations exist on many platforms from many vendors. The use of SDLC (and SNA) is becoming more and more rare, mostly replaced by IP-based protocols or being tunneled through IP (using AnyNet or other technologies). In 1975, IBM developed the first bit-oriented protocol, SDLC. This de facto standard has been adopted by ISO as High-Level Data Link Control (HDLC) and by ANSI as Advanced Data Communication Control Procedures (ADCCP). The latter standards added features such as the Asynchronous Balanced Mode. SDLC operates independently on each communications link, and can operate on multipoint or point-to-point links, on switched or dedicated circuits, and with full and half-duplex operation.

Bipolar encoding From Wikipedia, the free encyclopedia Jump to: navigation, search An example of Bipolar encoding, or AMI. In telecommunication, bipolar encoding is a type of line code (a method of encoding digital information to make it resistant to certain forms of signal loss during transmission). A duobinary signal is such an encoding.

[edit] Definition [edit] Common line codesContents [edit] Transmitting and receiving serial data Bits have to be moved from one place to another using wires or some other medium. Over many miles, the expense of the wires becomes large. To reduce the expense of long communication links carrying several bits in parallel, data bits are sent sequentially, one after another, using a UART to convert the transmitted bits between sequential and parallel form at each end of the link. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. The UART usually does not directly generate or receive the external signals used between different items of equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels. External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS485 from the EIA. Historically, the presence or absence of current (in current loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are optical fiber, infrared, and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC-LIN for

power line communication. Communication may be "full duplex" (both send and receive at the same time) or "half duplex" (devices take turns transmitting and receiving). As of 2006, UARTs are commonly used with RS-232 for embedded systems communications. It is useful to communicate between microcontrollers and also with PCs. Many chips provide UART functionality in silicon, and lowcost chips exist to convert logic level signals (such as TTL voltages) to RS-232 level signals (for example, Maxim's MAX232).

[edit] Asynchronous receive and transmit In asynchronous transmitting, teletype-style UARTs send a "start" bit, five to eight data bits, least-significant-bit first, an optional "parity" bit, and then one, one and a half, or two "stop" bits. The start bit is the opposite polarity of the dataline's idle state. The stop bit is the data-line's idle state, and provides a delay before the next character can start. (This is called asynchronous start-stop transmission). In mechanical teletypes, the "stop" bit was often stretched to two bit times to give the mechanism more time to finish printing a character. A stretched "stop" bit also helps resynchronization. The parity bit can either make the number of "one" bits between any start/stop pair odd, or even, or it can be omitted. Odd parity is more reliable because it assures that there will always be at least one data transition, and this permits many UARTs to resynchronize. In synchronous transmission, the clock data is recovered separately from the data stream and no start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. An asynchronous transmission sends nothing over the interconnection when the transmitting device has nothing to send; but a synchronous interface must send "pad" characters to maintain synchronism between the receiver and transmitter. The usual filler is the ASCII "SYN" character. This may be done automatically by the transmitting device. USART chips have both synchronous and asynchronous modes.

[edit] Serial to Parallel Algorithm A data communication pulse can only be in one of two states but there are many names for the two states. When on, circuit closed, low voltage, current flowing, or a logical zero, the pulse is said to be in the "space" condition. When off, circuit open, high voltage, current stopped, or a logical one, the pulse is said to be in the "mark" condition. A character code begins with the data communication circuit in the space condition. If the mark condition appears, a logical one is recorded otherwise a logical zero. Figure 1 shows this format. start|<- five to eight data ->| stop bit(s) 0 ---- - - - - - - - - Space (logic low) | | | | | | | | | | | | | S | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | S | S | | | | | | | | | | | | | 1 - - - - - - - - - - -------Mark (logic high) bits

Figure 1. Asynchronous Code Format. The right-most bit is always transmitted first. If parity is present, the parity bit comes after the data bits but before the stop bit(s).

The start bit is always a 0 (logic low), which is also called a space. The start bit signals the receiving DTE that a character code is coming. The next five to eight bits, depending on the code set employed, represent the character. In the ASCII code set the eighth data bit may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They provide a "rest" interval for the receiving DTE so that it may prepare for the next character which may be after the stop bit(s). The rest interval was required by mechanical Teletypes which used a motor driven camshaft to decode each character. At the end of each character the motor needed time to strike the character bail (print the character) and reset the camshaft. All operations of the UART hardware are controlled by a clock signal which runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking

for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register is made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. In some common types of UART, a small first-in, first-out (FIFO) buffer memory is inserted between the receiver shift register and the host system interface. This allows the host processor more time to handle an interrupt from the UART and prevents loss of received data at high rates. Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register, the UART hardware generates a start bit, shifts the required number of data bits out to the line,generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since fullduplex operation requires characters to be sent and received at the same time, practical UARTs use two different shift registers for transmitted characters and received characters. Transmitting and receiving UARTS must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system. Typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ASCII characters per second is equal to the bit rate divided by 10.

[edit] History Some early telegraph schemes used variable-length pulses and rotating clockwork mechanisms to transmit alphabetic characters. The first UART-like devices (with fixed-length

pulses) were rotating mechanical switches (commutators). These sent 5-bit Baudot codes for mechanical teletypewriters, and replaced morse code. Later, ASCII required a seven bit code. When IBM built computers in the early 1960s with 8-bit characters, it became customary to store the ASCII code in 8 bits. Gordon Bell designed the UART for the PDP series of computers. Western Digital made the first single-chip UART WD1402A around 1971; this was an early example of a medium scale integrated circuit. An example of an early 1980s UART was the National Semiconductor 8250. In the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher transmission speed without data loss and without requiring such frequent attention from the computer. For example, the popular National Semiconductor 16550 has a 16 byte FIFO, and spawned many variants, including the 16C550, 16C650, 16C750, and 16C850. Depending on the manufacturer, different terms are used to identify devices that perform the UART functions. Intel called their 8251 device a "Programmable Communication Interface". MOS Technology 6551 was known under the name "Asynchronous Communications Interface Adapter" (ACIA). The term "Serial Communications Interface" (SCI) was first used at Motorola around 1975 to refer to their start-stop asynchronous serial interface device, which others were calling a UART. Some very low-cost home computers or embedded systems dispensed with a UART and used the CPU to sample the state of an input port or directly manipulate an output port for data transmission. While very CPU-intensive, since the CPU timing was critical, these schemes avoided the purchase of a costly UART chip. The technique was known as a bit-banging serial port.

[edit] Structure A UART usually contains the following components: • • •

a clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period. input and output shift registers transmit/receive control

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read/write control logic transmit/receive buffers (optional) parallel data bus buffer (optional) First-in, first-out (FIFO) buffer memory (optional)

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[edit] Special Receiver Conditions

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[edit] Overrun Error

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[edit] Underrun Error

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[edit] Framing Error

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[edit] Parity Error

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[edit] Break Condition

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An "overrun error" occurs when the UART receiver cannot process the character that just came in before the next one arrives. Various UART devices have differing amounts of buffer space to hold received characters. The CPU must service the UART in order to remove characters from the input buffer. If the CPU does not service the UART quickly enough and the buffer becomes full, an Overrun Error will occur. An "underrun error" occurs when the UART transmitter has completed sending a character and the transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since additional stop bits can be appended. This error indication is commonly found in USARTs, since an underrun is more serious in synchronous systems. A "framing error" occurs when the designated "start" and "stop" bits are not valid. As the "start" bit is used to identify the beginning of an incoming character, it acts as a reference for the remaining bits. If the data line is not in the expected idle state when the "stop" bit is expected, a Framing Error will occur. A "parity error" occurs when the number of "active" bits does not agree with the specified parity configuration of the UART, producing a Parity Error. Because the "parity" bit is optional, this error will not occur if parity has been disabled. Parity error is set when the parity of an incoming data character does not match the expected value. A "break condition" occurs when the receiver input is in at the "space" level for longer than some duration of time, typically, for more than a character time. This is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error. Some equipment will deliberately transmit the "break" level for longer than a character as an out-of-band signal. When signaling rates are mismatched, no meaningful characters can be sent, but a long "break" signal can be a useful way to get the attention of a

mismatched receiver to do something (such as resetting itself. UNIX systems and UNIX-like systems such as Linux can use the long "break" level as a request to change the signaling rate. •

[edit] See also

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Asynchronous serial communication Baud bit rate Modem Morse code Serial communication Serial port USB

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Manchester code

From Wikipedia, the free encyclopedia Jump to: navigation, search In telecommunication, Manchester code (also known as Phase Encoding, or PE) is a line code in which the encoding of each data bit has at least one transition and occupies the same time. It is, therefore, self-clocking, which means that a clock signal can be recovered from the encoded data. Manchester code is widely-used (e.g. in Ethernet). There are more complex codes e.g. 8B/10B encoding which use less bandwidth to achieve the same data rate (but which may be less tolerant of frequency errors and jitter in the transmitter and receiver reference clocks).

Contents [hide]

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1 Features 2 Description o 2.1 Manchester encoding as phase-shift keying o 2.2 Conventions for representation of data 3 Shortcomings 4 References

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5 Further reading

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AMI 2B1Q

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4B5B 4B3T 6b/8b encoding 8b/10b encoding 64b/66b encoding B3ZS B8ZS CMI Conditioned Diphase Eight-to-Fourteen Modulation (EFM) used in Compact Disc EFMPlus used in DVD HDB3 NRZ - Non-return-to-zero NRZI - Non-return-to-zero, inverted Manchester code (also variants Differential Manchester & Biphase mark code) Miller encoding (also known as Delay encoding, and has variant Modified Miller encoding) MLT-3 Encoding Modified AMI RZ - Return-to-zero Hybrid Ternary Codes Surround by complement (SBC) TC-PAM

Universal asynchronous receiver/transmitter From Wikipedia, the free encyclopedia (Redirected from Universal asynchronous receiver transmitter) Jump to: navigation, search "DUART" redirects here. For the castle on the Island of Mull, see Duart Castle. A universal asynchronous receiver/transmitter (usually abbreviated UART and pronounced /ˈjuːɑrt/) is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with other communication standards such as EIA RS-232. A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART or DUART combines two UARTs into a single

chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are called USARTs. •

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[hide] 1 Definition o 1.1 Transmitting and receiving serial data o 1.2 Asynchronous receive and transmit o 1.3 Serial to Parallel Algorithm 2 History 3 Structure 4 Special Receiver Conditions o 4.1 Overrun Error o 4.2 Underrun Error o 4.3 Framing Error o 4.4 Parity Error o 4.5 Break Condition 5 See also

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6 External links

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1 Advantages 2 Alternate Mark Inversion 3 Error detection 4 Other T1 encoding schemes 5 References

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6 See also

[edit] Advantages [edit] Features Manchester code provides simple encoding with no long period without a level transition. This helps clock recovery. The DC component of the encoded signal is not dependent on the data and therefore carries no information, allowing the signal to be conveyed conveniently by media (e.g. Ethernet) which usually do not convey a DC component.

[edit] Description An example of Manchester encoding showing both conventions Extracting the original data from the received encoded bit (from Manchester as per 802.3):

original data = clock 0 0 0 1 1 0 1 1

XOR

Manchester value 0 1 1 0

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Each bit is transmitted in a fixed time (the "period"). A 0 is expressed by a low-to-high transition, a 1 by high-to-low transition (according to G.E. Thomas' convention -- in the IEEE 802.3 convention, the reverse is true). The transitions which signify 0 or 1 occur at the midpoint of a period. Transitions at the start of a period are overhead and don't signify data.

Manchester code always has a transition at the middle of each bit period and may (depending on the information to be transmitted) have a transition at the start of the period also. The direction of the mid-bit transition indicates the data. Transitions at the period boundaries do not carry information. They exist only to place the signal in the correct state to allow the mid-bit transition. Although this allows the signal to be selfclocking, it doubles the bandwidth requirement compared to NRZ coding schemes (or see also NRZI). In the Thomas convention, the result is that the first half of a bit period matches the information bit and the second half is its complement.

[edit] Manchester encoding as phase-shift keying Manchester encoding is a special case of binary phase-shift keying (BPSK), where the data controls the phase of a square wave carrier whose frequency is the data rate. Such a signal is easy to generate. To control the bandwidth used, a filter can reduce the bandwidth to as low as 1Hz per bit/second without loss of information in transmission. In radio transmission, the encoded signal may also be modulated with a carrier wave; however, the property of 1Hz per bit/second is preserved.

[edit] Conventions for representation of data Encoding of 11011000100 in Manchester code (as per G. E. Thomas) There are two opposing conventions for the representations of data. The first of these was first published by G. E. Thomas in 1949 and is followed by numerous authors (e.g., Tanenbaum). It specifies that for a 0 bit the signal levels will be Low-High (assuming an amplitude physical encoding of the data) - with a low level in the first half of the bit period, and a high level in the second half. For a 1 bit the signal levels will be High-Low.

The second convention is also followed by numerous authors (e.g., Stallings) as well as by IEEE 802.4 (token bus) and lower speed versions of IEEE 802.3 (Ethernet) standards. It states that a logic 0 is represented by a High-Low signal sequence and a logic 1 is represented by a Low-High signal sequence. If a Manchester encoded signal is inverted in communication, it is transformed from one convention to the other. This ambiguity can be overcome by using differential Manchester encoding.

[edit] Shortcomings Manchester code needs twice the bandwidth of asynchronous communications, and the signal spectrum is much wider. Most high-speed communication now uses encoding schemes with better coding performance. One consideration is synchronization of the receiver to the transmitter. It might appear that a half bit period error would give an inverted output at the receiver, but for typical data this leads to code violations. The receiver can detect these violations and use this information to synchronise accurately.

A binary 0 is encoded as zero volts as in unipolar encoding. A binary 1 is encoded alternately as a positive voltage and a negative voltage. This prevents a significant build-up of DC, as the positive and negative pulses average to zero volts. Little or no DC-component is considered an advantage because the cable may then be used for longer distances and to carry power for intermediate equipment such as line repeaters.[1] The DC-component can be easily and cheaply removed before the signal reaches the decoding circuitry. Bipolar encoding is preferable to non-return-to-zero where signal transitions are required to maintain synchronization between the transmitter and receiver. Other systems must synchronize using some form of out-of-band communication, or add frame synchronization sequences that don't carry data to the signal. These alternative approaches require either an additional transmission medium for the clock signal or a loss of performance due to overhead, respectively. A bipolar encoding is an often good compromise: runs of ones will not cause a lack of transitions, however long sequences of zeroes are still an issue. Long sequences of zero bits result in no transitions and a loss of synchronization. Where frequent transitions are a requirement, a self-clocking encoding such as return-to-zero or some other more complicated line code may be more appropriate, though they introduce significant overhead.

[edit] Alternate Mark Inversion When used on a T-carrier, the code is known as Alternate Mark Inversion because, in this context, a binary 1 is referred to as a "mark", while a binary 0 is called a "space".[2] The coding was used extensively in first-generation PCM networks, and is still commonly seen on older multiplexing equipment today, but successful transmission relies on no long runs of zeroes being present.[3] No more than 15 consecutive zeros

should ever be sent to ensure synchronization. The modification of bit 7 causes a change to voice that is undetectable by the human ear, but it is an unacceptable corruption of a data stream. Data channels are required to use some other form of pulse-stuffing,[1] such as always setting bit 8 to 1, in order to maintain one's density. Of course, this lowers the effective data throughput to 56 kbit/s per channel.[4]

[edit] Error detection Another benefit of bipolar encoding compared to unipolar is error detection. In the Tcarrier example, the bipolar signals are regenerated at regular intervals so that signals diminished by distance are not just amplified, but detected and recreated anew. Weakened signals corrupted by noise could cause errors, a mark interpreted as zero, or zero as positive or negative mark. Every single-bit error results in a violation of the bipolar rule. Each such bipolar violation (BPV) is an indication of a transmission error. (The location of BPV is not necessarily the location of the original error).

[edit] Other T1 encoding schemes For data channels, in order to avoid the need of always setting bit 8 to 1, as described above, other T1 encoding schemes (Modified AMI codes) ensure regular transitions regardless of the data being carried. In this way, data throughput of 64 kbit/s per channel is achieved. B8ZS is a newer format for North America, where HDB3 is the original line coding type used in Europe and Japan. A very similar encoding scheme, with the logical positions reversed, is also used and is often referred to as pseudoternary encoding. This encoding is otherwise identical.

Line code From Wikipedia, the free encyclopedia Jump to: navigation, search An example of coding a binary signal using rectangular pulse amplitude modulation with polar non-return-to-zero code An example of Bipolar encoding, or AMI. Encoding of 11011000100 in Manchester encoding An example of Differential Manchester encoding An example of Biphase mark code

An example of MLT-3 encoding. In telecommunication, a line code (also called digital baseband modulation) is a code chosen for use within a communications system for transmission purposes. For digital data transport line coding is often used. Line coding consists of representing the digital signal to be transported, by an amplitude- and time-discrete signal, that is optimally tuned for the specific properties of the physical channel (and of the receiving equipment). The waveform pattern of voltage or current used to represent the 1s and 0s of a digital signal on a transmission link is called line encoding. The common types of line encoding are unipolar, polar, bipolar and Manchester encoding. For reliable clock recovery at the receiver, one usually imposes a maximum runlength constraint on the generated channel sequence, i.e. the maximum number of consecutive ones or zeros is bounded to a reasonable number. A clock period is recovered by observing transitions in the received sequence, so that a maximum runlength guarantees such clock recovery, while sequences without such a constraint could seriously hamper the detection quality. After line coding, the signal is put through a "physical channel", either a "transmission medium" or "data storage medium". Sometimes the characteristics of 2 very differentseeming channels are similar enough that the same line code is used for them. The most common physical channels are: • • • • • • •

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the line-coded signal can directly be put on a transmission line, in the form of variations of the voltage or current (often using differential signaling). the line-coded signal (the "baseband signal") is further modulated to create the "RF signal" that can be sent through free space. the line-coded signal can be used to turn on and off a light in Free Space Optics, most commonly infrared remote control. the line-coded signal can be printed on paper to create a barcode. the line-coded signal can be converted to a magnetized spots on a hard drive or tape drive. the line-coded signal can be converted to a pits on optical disc. Unfortunately, most long-distance communication channels cannot transport a DC component. The DC component is also called the disparity, the bias, the DC coefficient. The simplest possible line code, unipolar, because it has unbounded DC component, gives too many errors on such systems. Most line codes eliminate the DC component -- such codes are called "DC balanced", zero-DC, zero-bias, "DC equalized", etc. There are 2 ways of eliminating the DC component: Use a constant-weight code. In other words, design each transmitted code word such that every code word that contains some positive or negative levels also contains enough of the opposite levels, such that the average level over each code word is zero. For example, Manchester code and Interleaved 2 of 5. Use a paired disparity code. In other words, design the receiver such that every code word that averages to a negative level is paired with another code word that averages to a positive level. Design the receiver so that either code word of the

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pair decodes to the same data bits. Design the transmitter to keep track of the running DC buildup, and always pick the code word that pushes the DC level back towards zero. For example, AMI, 8B10B, 4B3T, etc. Line coding should make it possible for the receiver to synchronize itself to the phase of the received signal. If the synchronization is not ideal, then the signal to be decoded will not have optimal differences (in amplitude) between the various digits or symbols used in the line code. This will increase the error probability in the received data. It is also preferred for the line code to have a structure that will enable error detection. Note that the line-coded signal and a signal produced at a terminal may differ, thus requiring translation. A line code will typically reflect technical requirements of the transmission medium, such as optical fiber or shielded twisted pair. These requirements are unique for each medium, because each one has different behavior related to interference, distortion, capacitance and loss of amplitude.

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Contents

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[hide] 1 Common line codes 2 See also 3 References

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4 External links

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1 Unipolar Non-Return-to-Zero Level 2 Bipolar Non-Return-to-Zero Level 3 Non-Return-to-Zero Mark 4 Non-Return-to-Zero Space 5 Non-Return-to-Zero Inverted (NRZI) 6 Notes 7 See also

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8 References