Noise Considerations For Mixed-signal Rf Ic Transceivers

Wireless Networks 4 (1998) 41–53

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Noise considerations for mixed-signal RF IC transceivers Sayfe Kiaei a , David Allstot b , Ken Hansen c and Nishath K. Verghese d b Electrical

a Broadband Products, Motorola Inc., Austin, TX 78721, USA and Computer Engineering Department, Oregon State University, Corvallis, OR 97331, USA c Wireless Technology Center, Motorola Inc., Austin, TX 78759, USA d Cadense Design Systems, San Jose, CA 95134, USA

This paper discusses design trade-offs for mixed-signal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multi-path fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit non-linearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design trade-offs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixed-signal noise coupling and to model substrate noise effects are presented.

1. Introduction There has been rapid growth in wireless communication systems such as cellular and cordless telephones, multi-media, paging, and Personal Communication Systems (PCS) [6,10,19,23,26,27], and the recent FCC allocation of new PCS channels in the 1.8–2 GHz band will simulate further growth in the next generation of wireless systems [27]. The recent increase in wireless applications brings a new set of aggressive design goals: low-power for portability, lower-cost, and higher integration of RF components. For a typical receiver, the RF signal’s magnitude modulated at 900 MHz–2 GHz, can range from 20 dBm to −120 dBm; i.e., with a 50 Ω termination, the incoming signal can be as low as 0.22 µV [10]. During signal propagation and reception, there exists many sources of noise such as interferers, channel noise and device non-linearity (mixers and front and RF circuitry) that affect the integrity of the demodulated signal. Figure 1(a) shows the possible sources of noise during signal transmission and reception. This can be categorized as follows: • Channel noise sources and signal losses: background white gaussian noise, atmospheric noise, radio propagation losses, Doppler effect, fast fading, multi-path signal losses, and adjacent channel interferers [10,23]. • Front-end RF receiver non-idealities: RF circuit sensitivity, circuit non-linearity (mixers, amplifiers, RF filters), intermodulation, spurious responses [4,9,18,21,22, 25,30], fundamental device noise, and synthesizer phase noise [28]. • Mixed-signal noise coupling: digital circuit switching noise coupling to RF and sensitive analog sections via the substrate, input/output pins, and supply lines [1,2,7, 12,15,29,31–34]. Fundamental device noise contributions to the frequency synthesizer spectral response (phase noise) can couple to  J.C. Baltzer AG, Science Publishers

(a)

(b) Figure 1.

Wireless system noise model. (a) Cellular system model. (b) Transceiver model.

the signal path in the RF mixer as illustrated in figure 1(b). Moreover, on-chip integration of sensitive analog RF circuits with the noisy local oscillator (LO), frequency synthesizer, and other high-speed digital circuits can be detrimental to the weak incoming RF signal. The synthesizer consists of a high-speed divider/counter circuit which can produce significant switching noise [8]. Any digital switching noise is of significant importance since cumulatively it can reach several hundred mVolts and propagate to the RF section via the substrate and I/O pins. This noise can also couple to the signal path during the mixing operation of LO with the incoming signal. Methods to model such

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noise and to prevent its propagation to the analog section are discussed in sections 4 and 5. The organization of this paper is as follows: a tutorial on the basics of radio frequency signal propagation and interference is given followed by an overview of a typical RF transceiver and its design trade-offs. Later sections examine on-chip noise coupling for mixed-signal RF ICs and methods to model such effects.

Figure 2. Reflective signal losses.

2. RF signal losses and channel noise The properties of a wire-lined communications channel such as a cable telephone system which can be modeled as a stationary channel are well understood. However, a wireless channel is constantly changing over time due to the uncertainty in the channel terrain, signal propagation path, and the mobility of the transceiver unit. The RF signal received at the antenna is a function of the distance from the base station, signal path geography, obstacles between the transmitter and the receiver, and multi-path propagation of reflective signals. The channel noise illustrated in figure 1(a) consists of large scale propagation losses, lognormal shadowing, and exponential multi-path power losses (Rayleigh fading) [3,10,14,21–23,30] as described bellow. 2.1. Power-law losses

Figure 3. Mobile received signal fading representation.

The power law effect is due to the power loss of an electromagnetic wave traveling through free space in a line of sight path from transmitter to receiver. Under the assumption that the transmitting antenna is in the far field of the receiving antenna [10], Pr (d) =

Pt Gt Gr λ2 , (4π)2 d2 L

(1)

where Pr and Pt are the received and transmitted signal powers, Gr and Gt are the receiver and transmitter antenna gains, d is the receiver distance is from the transmitter, L is the system loss related to the channel, and λ is the RF signal wavelength. A more general expression can be derived to include reflections from the earth as shown in figure 2:  Pr (d) ≈ (Pt Gt Gr )

 hb hm , d2

(2)

where hb and hm are the heights of the base station and the mobile antenna. Since the received signal power is inversely proportional to the fourth power of distance, there is a 12 dB loss in power for each doubling of distance from the transmitter. This model accurately predicts what is measured empirically in the field [21]. For base station antennas less than 20 m in height over a range of 1 to 15 km, the measured power law exponent is d3.6 compared to d4 .

2.2. Multi-path losses The power law expression of (2) describes large-scale losses in the channel as a function of distance. There is also substantial variation in the receive power for small changes in distance because radio waves arrive at the receiver with different time delays (phase) and from different directions. As the mobile unit moves, the phase relationships among various incoming signals to the receiver via direct paths or reflected paths change. More specifically, if there is a substantial change in phase and magnitude of the incoming signals, then the received signal is subjected to fading. In addition to reflections, the mobile may also be moving which imposes a Doppler shift on the received signal. For UHF and higher RF frequencies, the scattered signals resulting from other moving objects can cause fading even if the mobile receiver is stationary. Figure 3 shows the received signal losses in a mobile environment. The long-term fading in the mean level is due to slow fading or log-normal fading, while fast fading occurs over distances of about half the signal wavelength. For a mobile travelling at 30 m.p.h., the fast fades occur about every second (60 Hz) for VHF and UHF frequencies. The rapid changes are due to local multipath phase cancellation known as fast fading or Rayleigh fading. The received signal xr (t) is a function of long term fading m(t) and short term fading r(t): xr (t) = m(t)r(t).

(3)

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2.2.1. Fast-fading (Rayleigh-fading) If distances over only a few wavelengths about a fixed distance are observed experimentally, the received signal has an exponential or Rayleigh distribution of power. Rayleigh fading is caused by multi-path signals arriving at the antenna with different time delays (phase shift) and amplitudes. The vector sum of the incident waves produces the resultant power. By moving only a fraction of a wavelength, it is possible for the phases of the incident waves to cancel the incoming signal resulting in a significant attenuation (up to 30 dB) of the received signal [3,14,21,22]. Consider the modulated received signal
xr (t) = A(t) cos 2πfc t + θ(t) ,

Figure 4. Multi-path received signal arriving at an angle α.

where A(t) is the amplitude variation and θ(t) encompasses the phase changes. In many cases, line of sight communication is not possible and the received signal is reflected from several paths arriving at different times as the mobile is moving with a velocity ν. Figure 4 shows the mobile moving along the x-coordinate at speed ν. The received signal arrives at an angle α and there exist N multipath components. If the transmitted signal is vertically polarized (i.e., the electric field vector is aligned along the z-axis), the electric field intensity of the RF signal Ez can be written as Ez = E0

N X

ej(ωc t+θn ) ,

θn = ωd t + φn ,

(4)

n=1

where E0 is the amplitude of the nth incoming reflective wave, φn is its random phase uniformly distributed between 0 and 2π, ωc is the carrier frequency, ωd is the Doppler radian frequency of nth incoming wave, and θn is the signal phase. The Doppler shift due to nth incoming signal at an angle αn is ωd = βν cos(αn ),

(5)

where β = 2π/λ. For a vehicle travelling at 60 m.p.h. receiving a modulated signal at 800 MHz, the fade occurs every 7 msec or at the frequency of fd = 143 Hz. The short term fading envelope has a Rayleigh probability distribution function given by [10] p(r) =

r (−r2 )/(2P0 ) e , P0

(6)

where 2P0 = 2σ2 is the mean square power of the component subject to short-term fading and r2 is the instantaneous power. The Rayleigh density function describes the firstorder statistical properties of the signal envelope over short distances where the signal mean level is constant. In order to combat short-fading, the system must be designed with sufficient transmit power to cover the desired area and prevent loss of communication during a fade. Hence, the radio circuit designer must design circuits whose performance is insensitive to rapid changes of RF signal power.

2.2.2. Long-term fading Field measurements have shown that the distribution of the received power measured at a constant distance from the base around a circular route (where the signal path from the base-station is constant) is log-normal with a typical standard deviation of 8–10 dB [10]. Since the probability density function for long-term fading m(t) is log-normal, the term log-normal shadowing is also used to describe this fading condition: p(m) =

2 2 1 √ e[(−(log m−η) )/(2σm )] , mσm 2π

(7)

where σm is the standard deviation and η is the mean of log(m). The long-term and short term fading along with other channel noise cause phase and amplitude distortions in the signal. In addition to the channel noise sources, the receiver adds noise and distortion to the incoming signal as described in the next sections.

3. RF receiver design considerations The goal of receiver design is to optimize performance in the presence of interferers. The primary interferers are undesired transmitters at the same frequency (co-channel interferers) or at a frequency one channel away (adjacent channel interferers). There are other interference sources such as automotive ignition systems, power distribution or transmission lines, industrial equipment (motors, welders), and consumer products (fluorescent lights, TV local oscillators, garage door openers). Co-channel interference is at the receiver’s desired frequency and can only be minimized by geographic separation and by reducing the number of potential interferers. From the power law model of (1), a first order estimate of carrier and interferer powers can be made. For US Cellular AMPS systems, a minimum carrier to interferer (C/I) level of 17–18 dB is required for acceptable voice quality. A typical super heterodyne receiver block diagram is shown in figure 5. Wherein an adjacent channel interferer is attenuated by crystal and ceramic filtering. Crystal filtering typically provides 15–20 dB of protection with the

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S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers

Figure 5. Superheterodyne receiver architecture.

remainder (determined by system specification) provided by ceramic filtering. 3.1. Receiver block The receiver block diagram shown in figure 5 consists of an RF front end, a 1st IF (Intermediate Frequency), a second IF, and an audio processing block. The RF selectivity band-width (image rejection) is typically 3–8 MHz depending on the application; the crystal selectivity filters usually consist of 2 poles per stage with an insertion loss of 2–3 dB per stage. The main objectives of the selectivity filter are to filter out the image signal and to band-limit the number of possible interferers that could cause intermodulation distortion before mixing, as shown in figure 6. The image signal is an unwanted interferer at a frequency 2fIF away from the desired RF signal that mixes to the same frequency as the IF signal. The first mixer frequency translates the RF carrier to an IF frequency (the RF signal frequency can vary depending on the channel frequency allocation). All further signal processing can be done at single tuned frequencies. Each crystal filter typically consists of a 2 pole bandpass stage with 3 dB of insertion loss. The 2nd IF circuitry is referred to as the receiver back-end and the final band-pass selectivity filter is a high Q filter such as ceramic filters. These ceramic filters typically consist of 8 poles with 12 dB of insertion loss. The audio processing circuitry conditions the audio signals as per system specifications and is typically integrated. Although the block diagram is for an AMPS system, the RF/IF blocks are nearly identical for all digital modulation formats. Many of the digital modulation schemes carry amplitude (not necessary in FM) as well as phase information which requires a different solution for the demodulation function as compared to FM. This is typically handled using a DSP section whose input is from the 2nd mixer. The purpose of the low-noise amplifiers is to provide isolation between stages and gain to improve the receiver sensitivity. The placement and design of selectivity filters and amplifiers balance the requirements of receiver sensitivity and intermodulation performance which will be discussed next. The new generation of mobile telecommunications devices are becoming more complex, yet rapidly decreasing in size. An example of a single chip Transceiver developed by Na-

Figure 6. Image rejection. The image signal is 2fIF away from the desired signal.

tional Semiconductor Corp. [11] for Digital European Cordless Telephone (DECT) and PCS applications is shown in figure 7. The main transceiver integrated circuit consists primarily of the mixers, and PLL, however, many of the components in the system such as the front-end RF SAW and LC filters, Transmit Power Amplifier (Tx PA), Voltage Control Oscillator (VCO), PLL loop filter, and others are external. There are several major obstacles in providing a single Transceiver IC including the front-end filters due to their high-Q and high operating frequency, the VCO due to its sensitivity to voltage variation and on-chip noise, and the synthesizer and oscillator components due to the coupling of their digital switch noise to the incoming RF signal. 3.2. Receiver sensitivity The receiver’s ability to receive a signal is defined in terms of SINAD which is measured at the input to the speaker and is defined to be SINAD =

S+N +D , S+N

(8)

where S = signal, N = noise, and D = distortion power. The accepted standard measure of receiver sensitivity is the RF signal level required to produce 12 dB SINAD. The distortion is caused in part by the FM process of receiving only limited sidebands. This degradation is primarily fixed by the system specifications for channel spacing and frequency deviation. Noise degradations are caused by the noise of

S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers

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Figure 7. Single chip transceiver with several off-chip components [11].

electronic circuits. For RF circuits, noise performance is characterized by noise figure which is defined as F =

1 NO (S/N )I = , (S/N )O G NI

(9) Figure 8. Noise figure for cascade of devices.

where F = noise figure, (S/N )I = Input signal-to-noise ratio, (S/N )O = Output signal-to-noise ratio, and G = circuit gain. If several blocks are cascaded as shown in figure 8 with noise figure Fi and power gain Gi , the overall noise figure is given by [30] F = F1 +

(F2 − 1) (F3 − 1) + + ···. G1 G1 G2

(10)

The overall noise figure is the first stage which it should have a low noise figure and a high gain. Noise figure can be related to receiver sensitivity through a receiver rise sensitivity (R) defined as R=

S+N . N

(11)

The rise sensitivity is typically measured at the lowest IF frequency. It has been found experimentally that a 6 dB rise sensitivity corresponds to 12 dB SINAD. For a signal generator driving a matched load it can be shown that the RMS voltage level required to achieve a given rise sensitivity is [4] p υ = F kT BRg (R − 1), (12) where k = Boltzman’s constant, T = temperature in ◦ K, B = bandwidth, and Rg = matched load impedance.

3.3. Intermodulation Intermodulation distortion is a measure of circuit nonlinearity; it occurs when two or more sinusoidal signals are applied to a non-linear circuit. Under these conditions, the output consists of the fundamentals, harmonics, and other spurious frequencies. A classical way of analyzing the problem is to represent a non-linear transfer function as a power series [18]: υ0 = a0 + a1 υi + a2 υi 2 + a3 υi 3 + · · · + an υi n,

(13)

where υ0 = output voltage, υi = input voltage, and ai = power series coefficient. If the input consists of two sinusoids of equal amplitude (replicates standard test conditions),
υi = υi cos(ω1 t) + cos(ω2 t) , (14) then from (13) υ0 = a0 + a1 υ1 (cos ω1 t + cos ω2 t)  + a2 υ12 1 + 12 cos 2ω1 t + 12 cos 2ω2 t  + cos(ω1 + ω2 )t + cos(ω1 − ω2 )t  + a3 υ13 94 cos ω1 t + 94 cos ω2 t + 14 cos 3ω1 t + 14 cos 3ω2 t + 34 cos(2ω1 + ω2 )t + 34 cos(2ω2 + ω1 )t  + 34 cos(2ω1 − ω2 )t + 34 cos(2ω2 − ω1 )t + · · · . (15)

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Figure 9. Intermodulation and harmonic distortion due to two sine tones at ω1 and ω2 .

For this analysis to be valid, it is assumed that the circuit is weakly non-linear so that the higher order terms are small compared to the fundamental amplitude a1 υ1 . A frequency domain plot of (15) is shown in figure 9. Second-order terms in the frequency domain consist of a DC component, the second harmonics of each input, and the sum and difference frequencies of the two inputs. Thirdorder terms are the fundamental frequencies, the third harmonics of the inputs, and the sum and differences of twice one input frequency minus the other input. The intermodulation ratio (IM) is defined as the ratio of the desired amplitude to the undesired amplitude. The particular frequency components of interest are those created by the sum and difference frequencies of the two input sources. Thus, IM2 =

a1 1 a2 v1

and IM3 =

4 a1 1 . 3 a3 v12

In wireless communications applications, third-order IM distortion is a primary concern. Consider the typical measurement for IM, which is to place two interfering signals at one and two channels away from the desired signal such that ωd = 150 Mhz, ω1 = 150 Mhz + 25 kHz, and ω2 = 150 Mhz + 50 kHz, where ωd = the desired frequency and ω1 and ω2 are interferers. From (15), there is an IM3 product at 2ω1 − ω2 = 150 Mhz which is the desired frequency. There is little protection from this IM3 product. The RF passband will pass the interferer unattenuated. However, the crystal filter can provide some protection. It has been shown that the IM3 ratio is improved 2 dB for every dB of attenuation one channel away from the desired and is improved dB for dB two channels away from the desired [9]. The remainder of the IM performance can only be achieved by designing circuits that are highly linear. For dual conversion receivers, second-order IM is not important because the distortion products fall well outside the RF passband. However, for direct conversion receivers (homodyne) where the RF signal is directly down converted to base-band signal, the second order IM product (ω2 − ω1 ) will fall at the desired frequency. In order to specify the IM characteristics of a circuit, two of the following must be specified: (1) IM ratio, (2) level

Figure 10. Inter-modulation intercept plot.

of the input interferer (v1 ), and (3) the level of IM generated (vc ). A convenient way to describe these relationships is by using the intercept point. Figure 10 shows the intercept point concept wherein each line is a plot of output versus input power. The slope of the fundamental is one and the slope of the mth order IM product is m. The intersection of the 2 lines defines the intercept point. Both an mth order input intercept point (IPmi ) and an mth order output intercept point (IPmo ) can be defined as shown in figure 10. In practice, the signal will is limited by the supply voltage and the circuit will gain compress prior to reaching the intercept point levels. Using figure 10 and simple geometric techniques, the relationship between IM and intercept point can be determines as follows (units in dB): IP2i = IM2 + v1 ,

(16)

IP2o = 2IM2 + vc ,

(17)

IP3i = 12 IM3 + v1 ,

(18)

3 2 IM3

(19)

IP3o =

+ vc ,

where IP2i(o) = second order input (output) intercept point, IP3i(o) = third order input (output) intercept point, IM2 = second-order IM ratio, and IM3 = third-order IM ratio. Using figure 10, the total intercept point IPt for cascaded stages can be calculated as [15]  q  q 1 1 G1 = + IPt IP1i IP2i  q 1/q G1 G2 + + ··· , (20) IP3i where q = (m − 1)/2, m = order of the intercept, and IPni = input intercept of nth stage. Therefore, from (20), it is undesirable to add gain in the receiver path after the first stage. Since this is in direct conflict with the requirement

S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers

Figure 11. Mixer symbol.

for high receiver sensitivity discussed in section 3.2, tradeoffs in the gain and selectivity of each stage must be made to optimize system performance. 3.4. Spurious responses Receiver spurious responses are defined as an apparent on-channel response to an undesired signal or group of signals. Spurious responses are caused by non-linearity in the receiver circuits. Intermodulation is a type of spurious response. Other common spurious responses are image, half-IF spur, and Able–Baker spurs generated by the mixer. A mixer function provides a frequency translation from the input frequency to an IF frequency. For the mixer shown in figure 11, for low-side injection fLO < fRF , where fIF = fRF − fLO ,

(21)

and for high-side injection fLO > fRF fIF = fLO − fRF ,

(22)

where fRF = RF frequency, fLO = Local Oscillator (LO) frequency and fIF = IF frequency. • Image spur. The image spur (fI ) occurs one IF frequency away from the LO frequency in the opposite direction from the RF frequency and is applied at the RF input of the mixer as an undesired signal (figure 11). Protection from the image can be provided by selectivity ahead of the mixer. For example, for low IF at 455 kHz, the image is at 910 kHz from the desired input signal. For this reason 4 poles of crystal selectivity are typically required ahead of the second mixer. • Half-IF. The half-IF spur (fHIF ) occurs at a frequency of 1/2 the IF frequency from the RF frequency towards the injection frequency. For low side injection fHIF = fLO + fIF /2.

(23)

Spurs are characterized by their order typically written as order (m, n) where m is the harmonic of the incoming spurious signal and n is the harmonic of the local oscillator required to produce a signal at the IF frequency. In the case of the half-IF spur of order (2, 2), 2fHIF − 2xfLO = fIF , fHIF = fLO + fIF /2.

(24) (25)

The half-IF spur is even more difficult to protect against than the image spur because it is located only half an IF from the desired RF frequency. In order to minimize

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its impact the second-order non-linearity of the circuit must to be minimized. • Able–Baker spur. These spurs are defined to occur at frequencies where n and m are separated by one. Spurs of this type are likely to fall within the RF passband but tend to be higher order. It has been shown that the distance the Able–Baker spur is from the desired frequency is [8] mfs − nfLO = fIF , fd − fLO = fIF ,

(26) (27)

where fs = spurious frequency, and fd = desired frequency. As f = fs − fd approaches 0, the spurious interferer falls inside the RF and IF passbands. With f = 0, it can be seen that the lower the IF frequency, the higher the order of the spur which is desirable since the magnitude of higher-order harmonics will be reduced substantially. The choice of an IF frequency requires several trade-offs. The first criterion is to choose an IF frequency that is not identical to a powerful transmitter (such as a commercial FM station) due to direct pickup. To minimize the impact of the image and half-IF spurs, the IF frequency should be as high as possible. However, to minimize the impact of Able–Baker spurs, the IF should be chosen as low as possible. Therefore, designer must balance these conflicting requirements. 3.5. Electronic device noise An important consideration in the design of receiver RF circuitry is the noise introduced by electronic (active and passive) components. Device noise is particularly important in the design of voltage-controlled oscillators where it contributes to noise in the oscillator phase response which sensitizes the receiver to interferers as will be seen in section 3.6. Moreover, in amplifiers and mixers, device noise must be considered in designing for acceptable noise figure. The level of noise generated by device noise mechanisms such as thermal noise, 1/f noise, and shot noise represents a minimum level of noise in a system and its control is accomplished through optimal circuit design, topology selection, bandwidth limiting of signals, and semiconductor process control. The most significant contributor to device noise is thermal noise (also called Johnson noise) due to the Brownian motion of charges in resistors. This random thermal motion can be represented as lattice vibrations within the material which result in a random disruption of current flow. The mean-square thermal noise voltage generated by a resistor is e2n = 4kT R∆f ,

(28)

where en represents the rms noise voltage developed across the resistor of value R over the (brickwall) bandwidth ∆f at absolute temperature T , a 1 MOhm resistor generates

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1.26 mV of rms thermal noise over a 100 MHz bandwidth at 25◦ C. Although pure reactances contribute no thermal noise, all practical implementations of reactive elements contain some resistive losses which lead to thermal noise contributions. For instance, a grounded capacitor with a series lossy resistance can be easily shown to have a brickwall bandwidth of 1/4RC. Consequently, such a capacitor would contribute “capacitor” noise with a meansquare voltage value of kT /C. The thermal noise contribution of a MOSFET can be determined by applying (28) to the channel resistance of the device to yield a channel thermal noise voltage, ed given by e2d = 4γkT ∆f /gd0,

(29)

where gd0 is the drain-source conductance at zero Vds and the parameter γ is ideally unity in the triode region and approximately 2/3 in saturation. Unfortunately, modern day shortchannel devices exhibit noise in excess of that predicted by (29) due to the influence of hot-electron effects, channel induced gate noise at RF frequencies [17] and other phenomena. Other sources of device noise include flicker (1/f ) noise which is generally associated with surface charge trapping by defects, impurities in semiconductor material, and shot noise due to the discreteness of charge carriers as they cross a potential barrier. As its name implies, 1/f noise is inversely proportional to its frequency, i2n = KI∆f /f n ,

(30)

where K is an empirically determined parameter, f is the frequency of the noise component and I is the dc bias current. For example, an NMOS device with W/L = (100 µm/10 µm) exhibits roughly 100 nV/sqrt(Hz) of rms flicker noise at 1 kHz. Flicker noise in MOS devices is usually insignificant beyond a few tens of kHz, whereas in bipolar devices it is insignificant beyond a few hundreds of Hz. Although 1/f noise contributions are negligible at RF frequencies, low frequency 1/f noise can be modulated by the RF carrier signal and appear in the RF band of mixers and oscillators [24]. Shot noise can be modeled as a current controlled current source whose rms-noise current value, is given by i2n = 2qI∆f ,

(31)

where I is the dc current flowing through the potential barrier and q is the electronic charge. For instance, a 1 µA current flowing through a P–N junction produces a rms shot noise current of 5.7 nA over a 100 MHz bandwidth. Shot noise is prevalent in bipolar devices but is insignificant in MOSFETS since the only current that flows through a semiconductor junction in MOS devices is the negligible gate current.

Figure 12. Frequency synthesizer phase noise.

3.6. Synthesizer phase noise Specifications of modern communication systems dictate that very small signals in the frequency band of interest be detected in the presence of strong interferers in adjacent channels. The high desensitization requirement for such interferers in adjacent channels cannot possibly be met by the RF filter alone. Consequently, the LO signal applied to the RF mixer in the receive path must be as close to a pure sinusoid as possible. If the spectrum of the LO signal consists of excessive contributions from frequencies close to the LO frequency, the undesired interferers in the RF band are also mixed down, thereby corrupting the IF signal. The non-ideal spectral response of the LO signal is caused by device noise and digital switching noise mechanisms (outlined in following sections) in the frequency synthesizer and are referred to as its phase noise. The phase noise requirement of a frequency synthesizer expressed in dBc/Hz from the carrier (LO) frequency is illustrated in figure 12. A typical cellular standard requires the phase noise to be between −115 to −130 dBc/Hz, at 60–250 kHz from the carrier frequency. In commonly-used phase-locked loop based frequency synthesizers as shown in figure 13, spectral components of the LO signal around the carrier frequency are determined primarily by phase noise in the voltage-controlled oscillator. Phase noise introduced by the crystal reference is low-pass filtered by the loop, whereas phase noise introduced by the VCO is high pass filtered. Consequently, for frequencies above the loop bandwidth which is typically governed by the channel spacing, the VCO effectively runs open loop and its phase noise is injected directly into the synthesizer output. Synthesizer phase noise is optimized through proper VCO design. Implementation of VCOs using active devices is not common since a large amount of power must be dissipated to minimize device noise contributions to the overall phase noise. Tuned LC oscillators using purely pas-

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Figure 13. PLL-based frequency synthesizer.

sive components are more commonly employed. With increasing demands for integrated transceivers, it has become necessary to implement passive inductors on the silicon substrate or as bondwires. Since, such implementations are lossy in nature, careful attention must be paid to physical design to realize integrated inductors at minimum cost [28].

4. Mixed-signal noise coupling The received RF signal can range from 20 dBm to −120 dBm; i.e., the incoming signal can be as low as 0.22 µV at 1.8–2 GHz. Any internal on-chip noise can corrupt the desired signal. The main source of on-chip noise in mixed-signal ICs is digital switching noise. In purely digital applications, CMOS static logic offers several attractive features including zero static power dissipation, high packing densities, wide noise margins, high operating frequencies, etc. For high-frequency wireless applications, however, its major drawback is the generation of a large amount of digital switching noise [1,2,7,12,15,29,31–34]. When many static gates change states, a large cumulative current spike flows through parasitic resistances and inductances creating power supply noise voltage spikes known as ‘Vdd bounce’ or ‘Gnd bounce’. Some fraction of this noise inevitably propagates, as shown in figure 14, to the sensitive analog circuitry through the substrate, power supply lines, bonding wires, package pins, etc., where it often limits the achievable accuracy. The switching noise current can range from 0.1 mA to several mA per CMOS gate depending on the device sizes. 4.1. Substrate coupling One of the key problem areas in integrating a receiver (or transceiver) onto a single chip is the common silicon substrate. Transistors fabricated on the same die interact with each other through the common conductive substrate leading to a phenomenon referred to as “substrate coupling”. This parasitic crosstalk can cause otherwise normal designs to malfunction. With increasing demands on both the frequency of operation and the analog resolution of integrated circuits, substrate coupling is becoming an increasingly important determinant of mixed analog/digital (mixed-signal) RF IC performance and behavior.

Figure 14. Noise coupling from the noisy digital portion of the IC to the sensitive RF/analog portion via substrate and supply lines.

Substrate coupling is a key problem both in purely analog circuits and in mixed-signal circuits. Although the mechanism of coupling in the substrate is identical in both cases, the effect of the parasitic crosstalk tends to be slightly different in these two classes of circuits. In purely analog circuits, the substrate acts as a signal feedback path which can lead to changes in small signal performance functions like amplifier gain and bandwidth. Additionally, impact ionization can cause currents to be injected into the substrate even under DC operating conditions, causing substrate biases to vary, which in turn cause variations in MOS threshold voltages, depletion capacitances and other circuit bias and performance quantities. In mixed-signal circuits, in addition to impact ionization-generated substrate currents, significant substrate currents are generated as a result of digital switching nodes capacitively connected to the substrate through both interconnect and device junction (depletion) capacitances. The switching noise injected into the substrate is picked up by sensitive analog devices on the same substrate, through both their junction capacitances to substrate and through the MOS device body effect. This results in induced spikes of noise in both device currents and node voltages [33]. 4.2. Mixed-signal design considerations Designers frequently rely on heuristic guidelines to immunize their designs from substrate crosstalk. These include noise prevention techniques to minimize generation of switching noise and noise reduction techniques using layout isolation and noise tolerant circuit design techniques for sensitive analog circuitry [33]. Less noisy alternatives to static CMOS logic families such as current steering logic (CSL) and folded source coupled logic (FSCL) that reduce switching currents in the

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power supply [1,2] are used wherever possible, especially at higher frequencies. In many transceiver systems, the synthesizer is designed using Bi-CMOS technology where the highspeed dividers and scalers are implemented with ECL (emitter coupled logic) topologies and at lower frequencies standard CMOS or CSL/FSCL components are used. Clocks and buffered outputs are ramped or have their rise times reduced to prevent excessive switching currents into the supplies and the substrate. Buffered outputs are skewed to prevent them from switching simultaneously and instants of analog sampling are timed away from primary switching events [32]. Power buses are routed to minimize impedance using multi-level gridded buses with regular on-chip (and on-board) capacitive decoupling to defuse current spikes. Power buses are also tied to multiple power pads/package pins to minimize lead inductance. (Package/bondwire inductance is the subject of a following section.) Layout isolation techniques help reduce the severity of crosstalk on some substrates. Physical separation between noisy and quiet circuits, separate analog and digital power/substrate supplies and diffused guard rings around a sensitive circuit are commonly employed layout strategies. Noise tolerant analog circuits can also be employed to minimize the impact of coupled noise. By using fully differential analog circuitry as in doubly balanced mixers and fully differential low noise amplifiers (LNA) with high common-mode rejection ratio (CMRR) and power-supply rejection ratio (PSRR), advantage can be taken of the fact that the switching noise appears as common-mode and is easily rejected by the circuit. In employing differential analog circuitry, care must be taken to ensure symmetric layout so that the coupled noise appears as common-mode between the differential device pairs. The unfortunate byproduct of using differential circuits is that the device noise √ contribution of the circuit now increases by a factor of 2 on a rms basis. Typically however, additional device noise is easier to live with. Sophisticated processing techniques utilizing triple-wells and trench structures or bondedwafer Silicon on Insulator (SOI) processes may also be used to DC isolate devices from one another. Such processes help isolate sensitive RF subsections from low frequency noise coupling from the digital sections. The aforementioned methods provide a partial solution to minimizing on-chip noise coupling.

impact ionization, device/interconnect capacitance, package/bondwire inductance and substrate resistance (and capacitance). 5.1. Impact ionization With increasing speeds of operation and decreasing technology feature sizes, impact ionization is becoming a primary cause of substrate current injection in integrated circuits. When the electric field in the depleted drain end of a MOS transistor becomes large enough to cause impact ionization, electron-hole pairs are created causing a current flow to the substrate. The hot-electron induced substrate current can be expressed in semi-analytical form as [13]  1/3 1/2  C2 tox · xj Isub = C1 (Vds − Vdsat )Id exp − , (32) Vds − Vdsat where C1 and C2 are process-related, empirically determined parameters, tox is the oxide thickness and xj is the junction depth. Using results from device simulations or measurements, it is possible to determine the empirical coefficients, C1 and C2 and to incorporate impact ionization induced substrate currents into existing device models for circuit simulation. 5.2. Device and interconnect capacitance Every transistor on an IC die is coupled capacitively to the substrate through its p–n junction depletion capacitances. Moreover, every interconnect routed on an IC has some capacitance to substrate. This capacitively coupled substrate current is of significant consequence in mixedsignal circuits, due to the presence both of a large number of switching digital nodes that inject current into the substrate and of high impedance analog nodes that are affected by this injected current. Since the amount of injected current is directly proportional to the slew rate of the switching voltage, at higher rates of circuit operation the substrate coupling problem is greatly aggravated. Moreover, with decreasing technology feature sizes, the interconnect capacitances to substrate are becoming increasingly important contributors of injected current. In order to account for capacitively coupled substrate currents, it is necessary to perform a parasitic capacitance extraction on the design to determine all significant capacitances to substrate in the circuit.

5. Modeling substrate coupling 5.3. Package/bondwire inductance Without suitable analysis to predict substrate crosstalk during the design process, the effectiveness of design guidelines cannot be determined until a circuit is fabricated and tested. Consequently, a basic understanding of the substrate coupling problem and techniques to model it [1,7,29,31–33] are assets to every RF integrated circuit designer. Several mechanisms must be understood and suitably modeled in an electrical circuit in order to analyze it for substrate coupling problems. These include the effects of

The effect of non-ideal (inductive) power supplies has a tremendous impact on the amount of substrate coupled switching noise in an IC design. Since the bondwires and package pins associated with the substrate supplies have finite and often large inductances, any substrate current picked up by these supplies can cause large glitches in the value of the substrate supply bias. This phenomenon is referred to as inductive or Ldi/dt noise. The presence of

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Figure 16. Substrate admittance versus frequency.

Figure 15. Methods for minimizing the coupling between the digital portion of Transceiver and the sensitive Analog portion.

parasitic inductances in the substrate supplies (note: there are typically several separate digital and analog supplies connected to substrate) can severely aggravate the noise coupling problem and much of current mixed-signal IC design methodology focuses on techniques to minimize their effect. For simulation purposes, it is necessary to use suitable package inductance models in the supply leads to accurately analyze substrate-coupled switching noise [29,33].

the substrate. The substrate admittance between the two points, y12 (s) can be determined as

5.4. Substrate resistance and capacitance Outside of the active areas formed by devices and substrate contacts, the substrate can be treated as consisting of layers of uniformly doped semiconductor material. Neglecting the effects of magnetic-fields on-chip, a simplified form of Maxwell’s equations can be applied to the substrate yielding
1 2 ∂ ∇ V (r, t) + ε ∇2 V (r, t) = I(r, t), ρ ∂t

(33)

where ρ is the resistivity and ε the permittivity of the uniformly-doped semiconductor. V (r, t) and I(r, t) are the transient voltage and current vectors at location r = (x, y, z) on the substrate. Assuming a 3-D semi-infinite substrate that goes to infinity in all but one of the six spatial directions, the solution to (33) in the Laplace domain for the voltage at any point on the substrate due to a unit current injected into the substrate a distance r away, is given by υ2 (s) =

ρ i1 (s) · . 2πr s(ρε) + 1

Figure 17. A typical substrate profile consisting of multiple uniformlydoped semiconductor layers with a backplane.

(34)

Consequently, the substrate impedance z21 (s) = v2 (s)/i1 (s) has a single pole response with a 3 dB frequency given by the reciprocal of the relaxation time constant, τ = ρε of

y12 (s) =

i1 1 = . 2(υ1 (s) − υ2 (s)) 2(z11 (s) − z12 (s))

(35)

Figure 16 plots the substrate admittance between two points on a substrate as a function of frequency for different substrate sheet resistivity (with ε0 = 11.7). Note that the admittance has a zero in its response with a 3 dB frequency as given above. Moreover, the 3 dB frequency scales with doping and is nearly 150 GHz for a 1 Ω-cm substrate. Consequently, for most frequencies of interest, the substrate can be assumed to behave as a purely resistive medium. The analysis conducted above assumed a simplistic homogeneous substrate. When the substrate profile consists of several layers of different doping density as shown in figure 17, the analysis becomes more complicated. To accommodate arbitrary doping profiles and the finite box boundary condition, techniques like the numerical finite difference method [33] or the semi-analytical boundary element method [7,32] can be applied. These techniques are used to determine reduced-order R(C) models between the devices in the circuit to capture the behavior of the substrate. Combining models for impact ionization, interconnect/device capacitance, package/bondwire inductance and substrate resistance/capacitance with a given electrical cir-

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cuit, one can simulate the effects of substrate coupling in the circuit. Such an analysis is very helpful to an IC designer in making circuit and physical design choices and in exploring the advantages of one process or packaging technology over another. 6. Conclusion Due to the rapid growth of wireless communications, the semiconductor industry has begun to generate silicon solutions for these applications. Most of these solutions have been focused on baseband processing. As semiconductor manufactures begin to increase the level of integration, the factors discussed in this paper will become increasingly important. Gain distribution and the impact it has on receiver sensitivity and intermodulation have been described. The origin of spurious responses and the impact of the IF frequency selection on these spurs has been presented, and the need for highly linear and robust circuits that can follow RF fades has been identified. Issues in high performance receiver circuit design such as device noise and phase noise were analyzed. Mixed-signal coupling problems due to the substrate and package were identified as significant physical design considerations, and guidelines for effective mixedsignal design to circumvent the coupling problems were outlined. Modeling strategies for the analysis of mixedsignal crosstalk were discussed to help study the effectiveness of the suggested design practices. It will be necessary to follow these guidelines to develop highly integrated wireless communications products. References [1] D.J. Allstot, S. Kiaei and R.H. Zele, Analog logic techniques steer around the noise, IEEE Circuits and Dev. Mag. 9 (September 1993) 18–21. [2] S.H. Chee, S. Kiaei and D.J. Allstot, CMOS folded source-coupled logic for mixed-mode VLSI circuits, IEEE J. Solid State Circuits 27 (January 1992). [3] M.J. Clarke, A statistical theory of mobile-radio reception, Bell System Technical Journal (August 1968). [4] J. Cramer, Analytical basis for rise and takeover measurements, Motorola Internal Technical Report (April 1969). [5] J.F. DeRose, The Wireless Data Handbook (Quantum Publishing, Inc., 1994). [6] T. Freeburg, A new technology high-speed WLAN, in: Proc. IEEE Workshop on Wireless LANs (Worcester, MA, 1991). [7] R. Gharpurey and R.G. Meyer, Modeling and analysis of substrate coupling in integrated circuits, IEEE J. Solid State Circuits 31(3) (March 1996) 344–353. [8] J. Glasser, Receiver spurious responses and other considerations in the selection of an intermediate frequency, Motorola Internal Technical Report (1968). [9] J. Heck, Intermodulation distortion analysis, Motorola Internal Technical Report (1993). [10] G.C. Hess, Land Mobile Radio System Engineering (Artech House, Boston, 1993). [11] K.M.D. Hess and D.E. Fague, Performance evaluation of a single chip radio transceiver, in: Proc. IEEE VTS 46th Vehicular Technology Conference, pp. 1048–1051.

[12] B.J. Hosticka and W. Brockherde, The art of analog circuit design in a digital VLSI world, in: Proc. of the IEEE International Symposium on Circuits and Systems (1990) pp. 1347–1350. [13] C. Hu, VLSI Electronics: Microstructure Science, Vol. 18 (Academic Press, New York, 1981) Chapter 3. [14] W.C. Jakes, Microwave mobile communications, in: Multi-Path Interference (Wiley, 1974) Chapter 1, pp. 11–78. [15] S. Kiaei, S.H. Chee and D.J. Allstot, CMOS source-coupled logic for mixed-mode VLSI, in: Proc. of the IEEE International Symposium on Circuits and Systems (1990) pp. 1608–1611. [16] M.C. Lawton and J.D. Waters, The design of flexible receivers for communicating appliances, in: Proc. IEEE VTS 46th Vehicular Technology Conference, pp. 1060–1064. [17] T. Lee, CMOS LNA design, in: IEEE Int. Solid State Circuits Conf. Short Course (February 1997). [18] C. Lynk and J. Ganzel, Receiver intermodulation analysis and calculations, Motorola Internal Technical Report (1962). [19] M.J. Marcus, Regulatory policy considerations for Radio Local Area Networks, IEEE Communication Mag. (July 1987) 95–99. [20] R.J. Murota and K. Hirade, GMSK modulation for digital mobile radio telephony, IEEE Transactions on Communications (July 1981) 1044–1050. [21] Y. Okumura et al., Field strength and variability in VHF and UHF land-mobile radio service, Rev. Elec. Communication Lab. 16(9–10) (September–October 1968) 841. [22] R. Price and P.E. Green, A communication technique for multipath channel, Proceedings of the IRF (March 1958) 555–570. [23] T.S. Rappaport, Wireless Communications, Principle and Practice (IEEE Press, Prentice-Hall PTR, 1996). [24] B. Razavi, Analysis modeling and simulation of phase noise in monolithic voltage-controlled oscillators, in: Proc. of the IEEE Custom Integrated Circuits Conference (May 1995) pp. 323–326. [25] R.C. Sagers, Intercept point and undesired responses, Correlations: An Engineering Bulletin from Motorola Inc. 5(1) (1985) 35–55. [26] M.K. Simon, J.K. Omura, R.A. Scholtz and B.K. Levitt, Spread Spectrum Communications Handbook (McGraw-Hill Inc., revised ed., 1994). [27] D.G. Steer, Coexistence and access etiquette in the US unlicensed PCS bands, IEEE Personal Comm. (1994). [28] M. Steyaert, Integrated CMOS voltage-controlled-oscillators and synthesizers, in: IEEE Int. Solid State Circuits Conf. Short Course (February 1997). [29] D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, Modeling techniques and experimental results for substrate noise in mixed-signal integrated circuits, IEEE J. Solid State Circuits 28(4) (April 1993) 420–430. [30] H. Taub and D.L. Schilling, Principles of Communications Systems (McGraw-Hill, New York, 1971). [31] N.K. Verghese and D.J. Allstot, Verification of RF and mixed-signal ICs for substrate coupling effects, in: Proc. Custom IC Conf. (May 1997). [32] N.K. Verghese, D.J. Allstot and M.A. Wolfe, Verification techniques for substrate coupling and their application to mixed-signal IC design, IEEE J. Solid State Circuits 31(3) (March 1996) 354–365. [33] N.K. Verghese, T.J. Schmerbeck and D.J. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits (Kluwer, Boston, 1995). [34] G.H. Warren and C. Jungo, Noise, crosstalk and distortion in mixed analog/digital integrated circuits, in: Proc. of the IEEE Custom Integrated Circuits Conference (1988) pp. 12.1.1–12.1.4.

Sayfe Kiaei, Ph.D., Washington State University, 1987. He was with Boeing Research and Technology Center at Renton, WA, during 1985– 1986 and with Motorola Inc. Wireless Technology Center from 1993 to 1997. Dr. Kiaei has been with the Department of Electrical Engineering at Oregon State University from 1987–1993 and 1996–present where he is an Associate Professor. His current research activities includes design of high

S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers performance IC’s for mixed-mode applications, wireless communication systems, VLSI system design for digital signal processing, and design of ASIC’s. He has authored several book chapters and over 30 papers in the fields of wireless communications, DSP, and Mixed-signal CMOS IC’s. Dr. Kiaei is a senior member of the IEEE, and was a member of the editorial board of IEEE Transactions on Circuits and Systems II. He is the Technical Co-Chair of the International Symposium on LowPower Electronics and the member of the technical program committee of a number of conferences. Dr. Kiaei is the recipient of the IEEE circuits and systems society Darling best paper award in 1994, and was the recipient of the Loyd-Carter award for the best teacher in the college of engineering at Oregon State University. Dr. Kiaei is the associate director of the NSF Center for the Design of Analog–Digital IC’s (CDADIC). David J. Allstot received the B.S. degree in engineering science from the University of Portland, the M.S. degree in electrical and computer engineering from Oregon State University, and the Ph.D. degree in electrical engineering and computer Science from the University of California (Berkeley) in 1979. His Ph.D. dealt with the analysis, design, and implementation of switched-capacitor filters. He has held industrial positions with Tektronix, Texas Instruments, and MOSTEK, and academic positions with UC Berkeley, Southern Methodist University, and Carnegie Mellon University. He is currently the Hewlett-Packard Professor of Electrical and Computer Engineering at Oregon State University. He has advised about 50 M.S. and Ph.D. students and has published several papers and one book with colleagues. Dr. Allstot’s professional service has included: Associate Editor and Editor of the IEEE Transactions on Circuits and Systems, Guest Editor of the IEEE Journal of Solid-State Circuits, member of the IEEE Circuits and Systems Society Board of Governors, and Technical Program Committee member of the IEEE Custom IC Conference, the IEEE International Symposium on Circuits and Systems, the International

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Symposium on Low-Power Electronics and Design, and the IEEE International Solid-State Circuits Conference. He is currently on the executive committee of the IEEE International Solid-State Circuits Conference. He was a co-recipient of the 1980 IEEE W.R.G. Baker Award and the 1995 IEEE Circuits and Systems Society Darlington Award, and has received excellence in teaching awards from SMU, OSU, and CMU. He is a member of Eta Kappa Nu and Sigma Xi and a fellow of IEEE.

Ken Hansen. MS, University of Illinois, 1976. Principal Member of the Technical Staff and Director of the Wireless Integration Technology Center for Radio Products Group of Motorola in Austin, TX. He has over 20 years of experience in RF circuits, bipolar, CMOS, and BiCMOS analog and digital circuit design in the field of wireless communications. He holds 7 patents in this area and is a member of IEEE.

Nishath K. Verghese received the B.E. (Hons.) degree from Birla Institute of Technology and Science, Pilani, India, in 1990, and the M.S. and Ph.D. degrees from Carnegie Mellon University, Pittsburgh, PA, in 1993 and 1995, respectively. From 1990 to 1991 he was with the VLSI Design Laboratory at McGill University, Montreal, Canada, where he worked on new circuit implementations of sigma–delta A/D converters and on estimation techniques for power bus current in CMOS logic circuits. At CMU, his research focussed on extraction and simulation techniques for substrate-coupled noise in mixed-signal ICs. In 1994, he worked for five months at the Mixed-Signal Design Department, Texas Instruments, Dallas, applying these techniques to the design of a video A/D converter. He is currently a Member of Consulting Staff at Cadence Design Systems, San Jose, CA. His research interests include design and verification of analog and mixed-signal circuits.