Microprocessor/microcontroller Program

INDEX 1. BLOCK TRANSFER AND BLOCK EXCHANGE OF DATA BYTES 2. ARRANGING ELEMENTS OF A BLOCK OF DATA IN ASCENDING AND DESCENDING ORDER. 3. MULTIPLICATION OF TWO 8-BIT NUMBERS USING THE

METHOD OF SUCCESSIVE ADDITION AND SHIFT AND ADD. 4. CONVERTING TWO DIGIT NUMBER TO THEIR EQUIVALENTS 5. GENERATION OF FIBONACCI SERIES 6. INTERFACING DAC 0808 7. INTERFACING OF THUMBWHEEL SWITCH. 8. ARRANGING BLOCK IN DESCENDING AND ASCENDING

9. 8051 TIMER BASED EXPERIMENT. 10. INTERFACING OF DOT MATRIX DISPLAY USING 8051

EXPERIMENT NO – 1 BLOCK TRANSFER AND BLOCK EXCHANGE OF DATA BYTES

BLOCK TRANSFER AND BLOCK EXCHANGE OF DATA BYTES Program Statement: Write a program to transfer block of bytes from location 2040 to 2050. Then exchange block of data at 2040 and 2050. Block length is stored at 203F.

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC-8501), Scratch Pad RAM used from 2000h to 2770h.

Learning Objective: 1. How transfer byte from one location to other? 2. Use of indirect addressing mode. 3. Exchange of data between two memory locations.

Logic: BLOCK TRANSFER: Block length is copied from location 203F and is used as counter. Data from memory location 2040 is copied to accumulator and from accumulator to 2050.After data is copied pointers for source and destination block is incremented by one and counter is decremented. Procedure is repeated till counter is not zero. BLOCK EXCHANGE: Content of memory location pointed by HL pair is copied to register B and from location pointed by DE pair to accumulator. Then data from accumulator is copied to location pointed by HL pair and from Reg. B to location pointed by DE pair and thus exchange is carried out. HL and DE pair is incremented counter is decremented . Exchange is carried out till counter is not zero.

ALGORITHM: BLOCK TRANSFER: 1. Start 2. Copy length of block 3. Initialize memory pointer of source block 4. Initialize memory pointer of destination block 5. Copy content of memory location from source block to accumulator 6. Copy content of memory location from accumulator to destination block 7. Increment both pointers 8. Decrement counter 9. If counter is not zero go to step 5 10. Stop

Stop

Copy length of block Initialize source block pointer Initialize destination block pointer Copy content from source memory location

Copy content to destination memory location Increment both pointers

Decrement counter

No

Is counter =0?

Yes

Stop

BLOCK EXCHANGE Stop

Copy length of block

Initialize source block pointer

Initialize destination block pointer

Exchange content of source and destination memory location

Increment both pointers

Decrement counter

No

Is counter =0?

Yes

Stop

BLOCK TRANSFER OF DATA BYTES Memory Address 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A

OP CODE 21 3F 20 4E 23 11 50 20 7E 12 23

200B

13

INX D

200C 200D 200E 200F 2010

0D C2 08 20 EF

DCR C JNZ BACK

Label

Mnemonic

Comment

LXI H, 203F

Point where length Is stored

MOV C, M INX H LXI D,2050

Copy length

BACK: MOV A,M STAX D INX H

RST 5

Initialize destination pointer

Increment source pointer Increment destination pointer

Check counter is zero or not?

BLOCK EXCHANGE OF DATA BYTES Memory Address 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013

OP CODE 21 3F 20 4E 23 11 50 20 46 1A 77 78 12 23 13 0D C2 08 20 EF

Label

Mnemonic

Comment

LXI H, 203F

Point where length Is stored

MOV C,M INX H LXI D,2050

Copy count value

BACK: MOV B,M LDAX D MOV M,A MOV A,B STAX D INX H INX D DCR C JNZ BACK RST 5

Initialize pointer

Increment pointer

Result: Block transfer: Memory Data Address 2040 11 2041 22 2042 55 2043 78 2044 63 2045 48 2046 54 Exchange Data 2047 87 Bytes: 2048 23 2049 65 Memory Data Address 2040 11 2041 22 2042 55 2043 78 2044 63 Memory Data 2045 48 Address 2046 54 2040 87 2047 87 2041 78 2048 23 2042 65 2049 65 2043 63 2044 55 2045 54 2046 48 2047 23 2048 22 2049 11

Memory Data Address 2050 11 2051 22 2052 55 2053 78 2054 63 2055 48 2056 54 2057 87 2058 23 2059 65 Memory Data Address 2050 87 2051 78 2052 65 2053 63 2054 55 Memory Data 2055 54 Address 2056 48 2050 11 2057 23 2051 22 2058 22 2052 55 2059 11 2053 78 2054 63 2055 48 2056 54 2057 87 2058 23 2059 65

EXPERIMENT NO – 2 ARRANGING ELEMENTS OF BLOCK IN ASCENDING AND DESCENDING ORDER

ARRANGING BLOCK OF DATA IN ASCENDING AND DESCENDING ORDER Program Statement: Write a program to arrange given block of data starting from 2051h in ascending order and descending order. Store result from 2070 for ascending order and from 2080 for descending order. Length of data is stored in memory location 2050h.

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC-8501), Scratch Pad RAM used from 2000h to 2770h.

Learning Objective: 1. How to arrange block in ascending and descending order? 2. Why to use two counters? 3. Use of compare instruction.

4. Effect of compare instruction on flag.

Logic: Ascending Order: Technique to arrange data bytes in ascending order is to compare two bytes at a time and arrange them at same time. Two counters are used for arranging data in ascending order. Two Numbers at successive memory locations are compared. Smaller number is stored at first memory location and larger number stored at next memory location. First counter is decremented by one and when first counter is zero then second counter is decremented by one and first counter is loaded again. So when second counter is also zero block is arranged in ascending order.

Descending Order: Technique to arrange data bytes in descending order is to compare two bytes at a time and arrange them at same time. Two counters are used for arranging data in descending order. Two Numbers at successive memory locations are compared. Larger number is stored at first memory location and smaller number at next memory location. First counter is decremented by one and when first counter is zero then second counter is decremented by one and first counter is loaded again. So when second counter is also zero block is arranged in descending order.

Algorithm: Ascending Order: 1. Start 2. Copy length of block 3. Initialize outer counter 4. Initialize inner counter 5. Initialize memory pointer 6. Compare two numbers

7. If carry flag is set go to step 9 8. If carry flag is not set exchange numbers 9. Decrement inner counter 10. If counter is not zero increment memory pointer go to step 6 11. If counter is zero decrement outer counter 12. If counter is not zero go to step 4 13. Stop

Descending Order: 1. Start 2. Copy length of block 3. Initialize outer counter 4. Initialize inner counter 5.

Initialize memory pointer

6. Compare two numbers 7. If carry flag is reset go to step 9 8. If carry flag is set exchange numbers 9. Decrement inner counter 10. If counter is not zero increment memory pointer go to step 6 11. If counter is zero decrement outer counter 12. If counter is not zero go to step 4 13. Stop

SORTING IN ASCENDING ORDER Start

Copy length of block Initialize outer counter

Initialize inner counter Initialize memory pointers

Compare two numbers Increment memory pointers

Is carry flag set?

No

Yes Exchange two numbers

Decrement inner counter

No

Is counter Yes =0? Yes Decrement outer counter

No

Is counter = 0 Yes ? Yes

Stop

SORTING IN DESCENDING ORDER Start

Copy length of block Initialize outer counter

Initialize inner counter Initialize memory pointers

Compare two numbers Increment memory pointers

Is carry flag reset?

No

Yes Exchange two numbers

Decrement inner counter

No

Is counter Yes =0? Yes Decrement outer counter

No

Is counter = 0 Yes ? Yes

Stop

SORTING IN ASCENDING ORDER Memory Address 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B

OP CODE 21 4F 20 46 35 5E 4B 21 51 20 BE DA 13 20 56 77 2B 72 23 0D C2 08 20 05 C2 06 20 EF

Label

Mnemonic LXI H, 204F

MOV B, M DCR M MOV E, M LOOP2: MOV C, E LXI H, 2051 LOOP1: MOV A, M INX H CMP M JC NEXT MOV D, M MOV M, A DCX H MOV M, D INX H NEXT: DCR C JNZ LOOP1 DCR B JNZ LOOP2 RST 5

Comment Point where length Is stored Copy length Initialize inner counter

Compare two numbers

Exchange if carry is Not created

Decrement inner counter

Decrement outer counter

SORTING IN DESCENDING ORDER Memory Address 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B

OP CODE 21 50 20 46 35 5E 4B 21 50 20 BE DA 13 20 56 77 2B 72 23 0D C2 08 20 05 C2 06 20 EF

Label

Mnemonic LXI H, 2050

MOV B, M DCR M MOV E, M LOOP2: MOV C, E LXI H, 2050 LOOP1: MOV A, M INX H CMP M JNC NEXT MOV D, M MOV M, A DCX H MOV M, D INX H NEXT: DCR C JNZ LOOP1 DCR B JNZ LOOP2 RST 5

Comment Point where length Is stored Copy length Initialize inner counter

Compare two numbers

Exchange if carry is created

Decrement inner counter

Decrement outer counter

Result: Ascending order: Before sorting Memory Data Address 2051 11 2052 22 2053 55 2054 78 2055 63 2056 48 2057 54 2058 87 2059 23 Memory Data 205A 65 Address 2051 11 2052 22 2053 55 2054 78 2055 63 2056 48 2057 54 2058 87 2059 23 205A 65

After sorting

Descending order: Before sorting After sorting

Memory Data Address 0500 11 0501 22 0502 23 0503 48 0504 54 0505 55 0506 63 0507 65 0508 78 Memory Data 0509 87 Address 0500 87 0501 78 0502 65 0503 63 0504 55 0505 54 0506 48 0507 23 0508 22 0509 11

Question Bank 1. Compare instructions SUB B and CMP B. 2. How compare instruction will affect on flags? 3. Where result of comparison is stored?

EXPERIMENT NO – 3 MULTIPLICATION OF TWO 8 BIT NUMBERS

MULTIPLICATION BY SHIFT AND ADD METHOD Program Statement: Write a program to multiply two 8-bit numbers by shift and add method. Numbers are present at memory location 2100(multiplier) and 2101(multiplicand). The result is 16 bit and is to be stored in memory location2102 and 2103.

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC8501), Scratch Pad RAM used from 2000h to 2770h.

Learning Objective: a)

Methods of multiplication.

b)

Shift and add method for multiplication.

c)

Use of DAD h in shift and add method.

Logic: The technique used to multiply two 8 bit numbers is same as used to multiply two binary numbers. In this method each bit of the multiplier bit is multiplied with multiplicand. Each partial product is to be shifted left so as to double the number. If the multiplier bit is 0 the multiplicand is doubled placed as the partial product. Therefore if multiplier ‘ n’ bit number of partial product will be ‘n’ if multiplicand is ‘m’ bits the product length will be 2 * m. 1101 (multiplicand) *0011(multiplier) --------------------------------1101

(partial products)

1011x 0000 x x 0000 x x x ---------------------------------------------00100011 (result)

MULTIPLICATION BY SHIFT AND ADD METHOD Algorithm: 1. Start. 2. Set partial product register pair to 0. 3. Set up register pair as multiplicand, get multiplier is register C as counter. 4. Double the partial product for next summand. 5. If multiplier is zero go to step 7. 6. If multiplier is not zero add multiplicand to the previous partial product. 7. Decrement counter by 1. 8. If counter is not zero go to step 4. 9. If counter is zero save result in register pair in memory. 10. Stop.

MULTIPLICATION BY SHIFT AND ADD METHOD Start Set partial product register pair to 0

Set up register pair as multiplicand; get multiplier in register C as counter

Double the partial product for next summand

Is multiplier zero?

Yes

No Add multiplicand to the previous partial product

Decrement counter by 1

No

Is counter zero? Yes Save result in register pair in memory

Stop

MULTIPLICATION BY SHIFT AND ADD METHOD Memory Address

OP CODE

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B

2A 50 20 5D 16 00 43 21 00 00 0E 08 29 78 07 47 D2 14 20 19 0D C2 0C 20 22 52 20 EF

Label

Mnemonic

Comment

LHLD 2050 Initialize memory pointer MOV E,L MVI D,00H MOV B,H LXI H,0000H MVI C,08H

Number of times to be rotated

UP: DAD H MOV A,B RLC MOV B,A JNC NEXT DAD D NEXT: DCR C JNZ UP SHLD 2052 RST 5

Result: INPUT Address 2100 2101

OUTPUT Data 3Fh 70h

Address 2102 2103

Data 1Bh 90h

MULTIPLICATION BY SUCCESSIVE ADDITION Algorithm: 1. Start 2. Copy contents of memory location to HL pair(First number) 3. Copy content of memory location to register C(Second number) 4. Add first number in itself 5. Decrement reg C 6. If not zero go to step 4 7. Store result 8. Stop.

MULTIPLICATION BY SUCCESSIVE ADDITION

Start Copy 1st number from memory location to register pair

Copy second number from memory location to register C Copy first number in DE pair

Add first number in itself HL+DE Decrement reg C

No

Is reg C zero?

Yes Store result in memory location

Stop

MULTIPLICATION BY SUCCESSIVE ADDITION Memory Address

OP CODE

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B

01 00 22 0A 6F 26 00 03 0A 3D 4F 5D 16 00 19 0D C2 0E 20 01 02 20 7D 02 03 7C 02 EF

Label

Mnemonic

LXI B,2200 LDAX B MOV L,A MVI H,00 INX B LDAX B DCR A MOV C,A MOV E,L MVI D,00

Comment

Load BC pair with content Of memory location 2200 Copy first number

Copy second number

LOOP: DAD D DCR C JNZ LOOP LXI B, 2002 MOV A,L STAX B INX B MOV A,H STAX B RST 5

Store result Store result

Result: INPUT Address 2200 2201

OUTPUT Data AA H AA H

Address 2202 2203

Data E4 H 70 H

Question Bank

1.

Compare RAR and RRC.

2. Explain following instructions a)

SHLD 2100

b)

DAD D

c)

XCHG

d)

LHLD 2100

3. What is difference between hardware and software interrupts? 4. What are vectored interrupts? 5. What are maskable and non maskable interrupts?

 

CONVERTING TWO DIGIT NUMBERS TO THEIR EQUIVALENTS Program Statement: Write a program to convert two digit number from BCD to HEX. Number is at location 2040 store result at location 2041.

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC8501), Scratch Pad RAM used from 2000h to 2770h.

EXPERIMENT NO – 4 CONVERTING TWO DIGIT NUMBER TO THEIR EQUIVALENTS Learning Objective: 1.

Unpacking of BCD number.

2.

Division of number.

Logic: BCD TO HEX CONVERSION: BCD number is unpacked and LSB and MSB is unpacked. MSB is multiplied by 10 and LSB is added in resulting value of multiplication. HEX TO BCD CODE CONVERSION:

HEX number is divided by 100 which is MSB. Remaining value is divided by 10 and remainder will be LSB.

Algorithm: BCD TO HEX CONVERSION: 1. Start 2. Copy number from memory location 3. Unpack both digits 4. Multiply MSB by 10 5. Add LSB into previous multiplication result 6. Store result 7. Stop HEX TO BCD CODE CONVERSION: 1. Start 2. Copy number from memory location 3. Divide number by 100 it will give MSB 4. Divide number by 10 5. Remainder is LSB 6. Store result 7. Stop

BCD TO HEX CONVERSION

Start Copy number from memory location

Unpack number and separate LSB and MSB

Multiply MSB by 10 add LSB into it

Store result in memory location

Stop

HEX TO BCD CONVERSION

Start Copy number from memory location

Divide number by 100(MSB)

Divide number by 10, Remainder is LSB

Store result in memory locations

Stop

BCD TO HEX CODE CONVERSION: Memory Address

OP CODE

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B 201C 201D 201E

21 40 20 46 7E E6 0F 4F 78 E6 F0 CA 1B 20 0F 0F 0F 0F 57 AF 1E 0A 83 15 C2 16 20 81 23 77 EF

Label

Mnemonic

LXI H,2040 MOV B,M MOV A,M ANI 0FH MOV C,A MOV A,B ANI F0H

Load HL pair with address of memory location Unpack LSB

Unpack MSB

JZ NEXT RRC RRC RRC RRC MOV D,A XRA A MVI E,0AH ADD: ADD E DCR D JNZ ADD ADD C INX H MOV M,A RST 5

Result: Input:

Comment

Output:

Address Data 2040 12 Address Data 2041 0C

Multiply MSB by 10 Add both

Store result

HEX TO BCD CODE CONVERSION Memory Address

OP CODE

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B 201C

21 40 20 7E 06 64 23 36 FF 90 34 D2 09 20 80 23 36 FF 06 0A 90 34 D2 14 20 80 23 77 EF

Label

Mnemonic

LXI H,2040

Address Data 2040 FF

Load HL pair with address of memory location

MOV A,M MVI B,64H INX H MVI M,FFH NEXT: SUB B INR M JNC NEXT

Divide number by 100

ADD B INX H MVI M,FFH MVI B,0AH NEXT1: SUB B INR M JNC NEXT1 ADD B INX H MOV M,A RST 5

Result: Input:

Comment

Output: Address 2041 2042 2043

Data 02 05 05

Divide number by 10

GENERATION OF FIBONACCI SERIES Program Statement: Write a program to generate Fibonacci series starting from location 2040.

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC8501), Scratch Pad RAM used from 2000h to 2770h.

EXPERIMENT NO – 5 GENERATION OF FIBONACCI SERIES Learning Objective: a. Generation of series

Logic: Copy first two numbers to locations. For generating next number add previous two numbers and store result. Go on repeating same procedure till counter is not zero.

Algorithm: 1. Start 2. Initialize pointer

3. Initialize counter 4. Copy first two numbers 5. Generate next number by adding previous two 6. Store result 7. Increment Pointer 8. Decrement counter 9. If counter is not zero go to step 5 10. Stop

GENERATION OF FIBONACCI SERIES Start

Initialize pointer and counter Copy first two numbers

Generate next number by addition of previous numbers Store result Increment pointer

Decrement counter

No

Is counter =0?

Yes

Stop

GENERATION OF FIBONACCI SERIES Memory Address

OP CODE

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014

21 40 20 0E 09 36 00 23 36 01 7E 2B 86 23 23 77 0D C2 0A 20 EF

Result: Address 2040 2041 2042 2043 2044 2045 2046 2047 2048

Data 00 01 01 02 03 05 08 0D 15

Label

Mnemonic

Comment

LXI H,2040H Initialize memory pointer MVI C,09H

Initialize counter

MVI M,00H

Copy first number

INX H MVI M,01H

Copy second number

BACK: MOV A,M DCX H ADD M INX H INX H MOV M,A DCR C JNZ BACK RST 5

Generate next number Store result

EXPERIMENT NO – 6 INTERFACING OF DAC 0808

INTERFACING OF DAC 0808 Program Statement: Write program to generate triangular waveform using DAC 0808

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC8501),Scratch Pad RAM used from 2000h to 2770h, Cathode Ray Oscilloscope.

Learning Objective: a) DAC 0808 b) OUT instruction c) How to generate triangular wave?

Logic: R-2R Ladder DAC:

2R

R

R R

R

2R

2R

2R

2R

+5V Only two values of resistors are used but result is same, input current is proportional to bit inputs. Features of DAC 0808 are: a) It has 8 data inputs. b) Fast setting time 150ns. c) Low power consumption 33mW. d) +5V power supply. e) TTL and CMOS compatible.

TRIANGULAR WAVE GENERATION USING DAC 0808 Algorithm: 1.

Initialize accumulator to 00H.

2.

Output register A to DAC buffer A0H.

3.

Increment accumulator.

4.

Compare accumulator content with FFH.

5.

If not zero go to step 2 or go to step 6.

6.

Decrement accumulator.

7.

Output register A to DAC buffer A0H.

8.

Compare accumulator content with 00H.

9.

If not zero go to step 6 or go to step 10.

10.

Go to step 1.

TRIANGULAR WAVE GENERATION USING DAC 0808

Start Load accumulator with 00H

Out accumulator content on A0H

Increment accumulator

Compare A with FFH

No

Is ZF=1 ?

Yes Decrement accumulator

Out accumulator content on A0H

Compare A with 00H

No

Is ZF=1 ?

Yes

TRIANGULAR WAVE GENERATION USING DAC 0808 Memory Address 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014

OP CODE 3E 00 D3 A0 3C FE FF C2 02 20 3D D3 A0 FE 00 C2 0A 20 C2 00 20

Label

Mnemonic

NEXT: MVI A, 00H NEXTINR: OUT A0H INR A CPI FFH

Comment Load A with 00H Output A to DAC Increment A

JNZ NEXTINR NEXTDCR: DCR A OUT A0H

Decrement A

CPI 00H JNZ NEXTDCR JMP NEXT

Jump to start again

Question Bank 1. Draw complete interfacing diagram and discuss a scheme for generation of ramp waveform using DAC IC 8255 PPI and 8085 2.

Draw timing diagram of OUT 20H instruction and explain it in detail.

 

EXPERIMENT NO – 4 INTERFACING THUMBWHEEL SWITCH

THUMBWHEEL SWITCH INTERFACE USING PPI 8255 Program Statement: To interface thumbwheel switch to 8085 through PPI 8255.

Apparatus: 8085 based single chip Microprocessor kit (VINYTICS VMC8501), Scratch Pad RAM used from 2000h to 2770h, Thumbwheel Switch Kit. Memory Address

Subroutine

0347h

Clear Display

05D0h

Character display

03BCh

Delay

16h is the character code used to keep display blank; stored at memory locations 2050 to 2054.

Learning Objective: a) IN instruction. b) Effect of XRA A instruction. c) PPI 8255.

Logic: Thumbwheel switch is interfaced to 8085 using PPI 8255. Each time thumbwheel switch is rotated by one step corresponding BCD number is read through PORT A by 8085 and that digit is displayed by using display subroutine.

THUMBWHEEL SWITCH INTERFACE USING PPI 8255 Algorithm: 1. Initialize stack 2. Call clear subroutine stored at 0347H 3. Load accumulator with control word and out it on control word register. 4. Clear accumulator and register B to enable address field of display. 5. Load HL pair with starting address of data for address field display. 6. Call output subroutine at 05D0H. 7. Copy contents of port A into accumulator. 8. Mask upper four bits. 9. Load HL pair with starting address of data for data field display. 10. Copy contents of accumulator in 2055H. 11. Load accumulator with 01H and register B with 00H to enable data field display. 12. Call display subroutine. 13. Load DE pair with 0000H as counter required by delay routine. 14. Call delay at 03BCH. 15. Go to step 7.

THUMBWHEEL SWITCH INTERFACE USING PPI 8255 Start

Initialize stack Call clear subroutine

Initialize 8255 ports Clear register A and B Initialize HL pair with 2050 Call output display subroutine

Copy data from Port A

Mask upper four bits Call output display subroutine

Load DE pair with count Call Delay Subroutine

THUMBWHEEL SWITCH INTERFACE USING PPI 8255 Memory Address 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A 200B 200C 200D 200E 200F 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 201A 201B 201C 201D 201E 201F 2020 2021 2022 2023 2024 2025

OP CODE 31 00 21 CD 47 03 3E 90 D3 03 AF 47 21 50 20 CD D0 05 DB 00 E6 0F 21 54 20 32 55 20 3E 01 06 00 CD D0 05 11 00 00

Label

Mnemonic LXI SP,2100H

Comment Initialize stack

CALL CLEAR MVI A,90H OUT 03H UP: XRA A MOV B,A LXI H,2050H CALL OUTPUT

Memory pointer for Character code Output subroutine

IN 00H ANI OFH LXI H,2054H STA 2055H MVI A,01H MVI B,00H CALL OUTPUT LXI D,0000H

Enable data field of display Disable dot of display Output subroutine

THUMBWHEEL SWITCH INTERFACE USING PPI 8255

Memory Address 2026 2027 2028 2029 202A 202B

OP CODE CD BC 03 C3 0A 20

Label

Mnemonic

Comment

CALL DELAY

Delay subroutine

JMP UP

Repeat again

2050 2051 2052 2053 2054 2055

16H 16H 16H 16H 16H 00H

Question Bank 1. Compare the execution of following instructions a) MVI A, 00H b) XRA A c) SUB A d) ANI 00H 2. Draw timing diagram of handshaking signals of 8255 in mode 1, input, along with INTR, RD. 3. Give BSR control word and explain bi-directional mode of operation of 8255



EXPERIMENT NO – 8 ARRANGING BLOCK IN DESCENDING AND ASCENDING USING 8051

ARRANGING BLOCK OF DATA IN DESCENDING AND ASCENDING ORDER Program Statement: Arrange given block of ten bytes in descending and ascending order. Block is stored from location 30H.

Apparatus: 8031 based single chip Microcontroller kit (ANSHUMAN – 8031/V51), Scratch Pad RAM used from 6000h to 7FFFh, Power Supply.

Learning Objective: 1. How to use memory pointer? 2. Comparison between two numbers 3. Use of one of the sorting technique as Bubble sort 4. Using two counters nesting is done.

Logic: For arranging block in descending order two memory pointers are used. Both are pointing successive memory locations. First pointers are pointing 30h and 31h both numbers are compared and larger number is stored at location 30h and smaller at 31h.Both pointers are incremented and counter is decremented. After comparing all numbers same procedure is repeated for ten times for that second counter is used. When second counter is decremented both pointers are pointing again 30h and 31h and first counter is loaded with 09. Above steps are repeated till second counter is zero. When second counter is zero block is arranged in descending order. Two counters are used as first counter is for comparison between two successive numbers and second for repeating the comparison 9 times to arrange them in descending order.

ARRANGING BLOCK OF DATA IN DESCENDING ORDER Start Counter1=0Ah Counter2=09h Pointer1=30h Pointer2=31h

No Is number pointed by pointer1 > pointer2 ?

Yes Increment Pointers decrement counter2

No

Is counter2 zero? Yes Decrement counter1

No Is counter1 zero? Yes Stop

Copy larger no. pointed by pointer1 smaller at pointed by pointer2

ARRANGING BLOCK OF DATA IN ASCENDING ORDER Start Counter1=0Ah Counter2=09h Pointer1=30h Pointer2=31h

No Is number pointed by pointer1 < pointer2 ?

Yes Increment Pointers decrement counter2

No

Is counter2 zero? Yes Decrement counter1

No Is counter1 zero? Yes Stop

Copy larger no. pointed by pointer1 smaller at pointed by pointer2

ARRANGING BLOCK IN DESCENDING ORDER Memory Address 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 600A 600B 600C 600D 600E 600F 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 601A 601B

OP CODE 7A 0A 7B 09 78 30 79 31 E6 87 40 B5 40 02 80 04 50 02 C7 F6 08 09 DB F0 BA E8 80 FE

Lable

Mnemonic And Operand MOV R2, #0AH

PASS2: MOV R3, #09H

Comment ;Load counter1 ;Load counter2

MOV R0, #30H

;Initialize Pointer1

MOV R1, #31H

;Initialize Pointer2

PASS: MOV A, @R0 MOV 40H, @R1 CJNE A, 40H,NEXT SJMP LOOP NEXT: JNC LOOP XCH A, @R1 MOV @R0, A LOOP: INC R0 INC R1 DJNZ R3, PASS DJNZ R2, PASS2 HERE: SJMP HERE

;Compare values Pointed by pointers

ARRANGING BLOCK IN ASCENDING ORDER Memory Address 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 600A 600B 600C 600D 600E 600F 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 601A 601B

OP CODE 7A 0A 7B 09 78 30 79 31 E6 87 40 B5 40 02 80 04 50 02 C7 F6 08 09 DB F0 BA E8 80 FE

Lable

Mnemonic And Operand MOV R2, #0AH

PASS2: MOV R3, #09H

Comment ;Load counter1 ;Load counter2

MOV R0, #30H

;Initialize Pointer1

MOV R1, #31H

;Initialize Pointer2

PASS: MOV A, @R0 MOV 40H, @R1 CJNE A, 40H,NEXT SJMP LOOP NEXT: JC LOOP XCH A, @R1 MOV @R0, A LOOP: INC R0 INC R1 DJNZ R3, PASS DJNZ R2, PASS2 HERE: SJMP HERE

;Compare values Pointed by pointers

Result: Ascending and Descending Input Block:

Output Block:

Memory Data Address 30 0A 31 05 32 0F 33 06 34 01 35 0B 36 0D 37 08 38 03 39 07

Memory Data Address 30 01 31 03 32 05 33 06 34 07 35 08 36 0A 37 0B 38 0D 39 0F

Input Block:

Output Block:

Memory Data Address 30 0A 31 05 32 0F 33 06 34 01 35 0B 36 0D 37 08 38 03 39 07

Memory Data Address 30 0F 31 0D 32 0B 33 0A 34 08 35 07 36 06 37 05 38 03 39 01

Question Bank 1. Why two pointers are required in this program? 2. How numbers are arranged in descending order? 3. Explain following instructions: a) CJNE A, #data, relative address b) DJNZ R1, relative address c) XCH A, @R1 4. Which registers are allowed to be used for register indirect addressing mode when accessing data in RAM?

EXPERIMENT NO – 8 SQUARE WAVE GENERATION USING TIMER OF 8051

SQUARE WAVE GENERATION USING TIMER OF 8051 Program Statement: Generation of square wave using timer of 8051.

Apparatus: 8031 based single chip Microcontroller kit (ANSHUMAN –8031/ V51), Scratch Pad RAM used from 6000h to 7FFFh, Cathode Ray Oscilloscope, Power Supply.

Learning Objective: 1. Timers of 8051 2. Working of timer of 8051 3. Generation of square using timer of 8051 4. Calculating count to be loaded in timer register 5. Role of overflow flag in timer 6. Generating delay using timer

Logic: For generating square wave port pin P1.1 is used. P1.1 is high for delay period generated by timer and low for the same delay period. TIMER0 in MODE1 is used. Count value is loaded in TH0 and TL0. Count value is calculated according to the frequency of square wave to be generated. P1.1 is made high. Timer is started and overflow flag is checked. When timer will roll over from FFFFH to 0000H overflow flag will be set. When overflow flag is set; P1.1 is complemented. Then stop the timer and procedure is repeated for continuous generation of square wave. As delay is same for high and low period square wave is having 50% duty cycle.

Algorithm: 1. Initialize timer and mode of timer. 2. Make P1.1 high 3. Load count value in THx and TLx 4. Start timer 5. Check overflow flag 6. When overflow flag is set complement P1.1 7. Clear overflow flag 8. Stop timer 9. For continuous display of square wave go to step 3

SQUARE WAVE GENERATION USING TIMER OF 8051

Start Initialize timer and mode Make P1.1 high

Load count value

Start timer

No

Is overflow flag set? Yes Complement P1.1

Clear overflow flag Stop Timer

SQUARE WAVE GENERATION USING TIMER OF 8051

Memory Address 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 600A 600B 600C 600D 600E 600F 6010 6011 6012 6013 6014 6015 6016 6017

OP CODE 75 89 01 D2 91 75 8A FD 75 8C FF D2 8C 30 8D FD B2 91 C2 8D C2 8C 80 ED

Lable

Mnemonic And Operand MOV TMOD, #01H

Comment ;Initialize mode and timer

SETB P1.1 UP: MOV TL0, #0FDH

;TL0 count

MOV TH0, #0FFH

;TH0 count

SETB TR0

;Start timer

LOOP: JNB TF0, LOOP

;Check overflow flag

CPL P1.1 CLR TF0 CLR TR0

;Stop timer

SJMP UP

;For continuous wave

Question Bank

1. How many timers do 8051 have? 2. How timer is initialized? 3. How count value, which is to be loaded in timer is calculated? 4. What is the use of overflow flag? 5. What is role of timer in serial communication? 6. Explain TMOD register. 7. Write assembly language program to generate square wave of 1KHz at P1.0 (bit 0 at port 1). 8. What bit addresses are assigned to TCON register?

EXPERIMENT NO – 6 INTERFACING OF DOT MATRIX DISPLAY USING 8051

INTERFACING OF DOT MATRIX DISPLAY USING 8051 Program Statement: Interfacing of 5 x 7 dot matrix display.

Apparatus: 8031 based single chip Microcontroller kit (ANSHUMAN – 8031/ V51), Scratch Pad RAM used from 6000h to 7FFFh, Dot Matrix Kit, Power Supply.

Learning Objective: 1. How to display number on matrix display? 2. How to use single bit of port? 3. Calling subroutine from different memory page.

Logic: For interfacing of 5x7 dot matrix display port 1 and port 3 are used. Seven rows as R1 to R7 are interfaced with port 1 from P1.0 to P1.6. Pin P1.7 is used for column 5. Four columns are interfaced using port 3 as C1 using P3.1, C2 using P3.3, C3 using P3.4 and C4 using P3.5. For displaying character rows and columns are enabled accordingly. By making port pins low of port 1 rows are enabled. And by making port pins of port 3 high columns are enabled. According to data to be displayed on matrix display, rows and columns are enabled and delay is called.

Algorithm: 1. Make display blank by disabling all rows and columns. 2. Enable all rows and C3 3. Call delay 4. Disable all rows and C3 5. Enable all columns and R7. 6. Call delay 7. Disable all columns and R7 8. Enable R3 and C1 9. Call delay 10. Disable R3 and C1 11. Enable R2 and C2 12. Call delay 13. Disable R2 and C2 14. For continuous display go to step2.

INTERFACING OF DOT MATRIX DISPLAY USING 8051 Start

Make display blank

Enable all rows and C3

Call delay Disable all rows and C3

Enable all columns and R7 Call delay Disable all columns and R7 Enable R3 and C1

Call display

Disable R3 and C1

Enable R2 and C2

Call delay

Disable R2 and C2

INTERFACING OF DOT MATRIX DISPLAY USING 8051 Memory OP Address CODE 6000 75 6001 81 6002 50 6003 75 6004 90 6005 7F 6006 75 6007 B0 6008 00 6009 75 600A 90 600B 00 600C D2 600D B4 600E 12 600F 60 6010 40 6011 C2 6012 B4 6013 75 6014 90 6015 7F 6016 75 6017 B0 6018 FF 6019 D2 601A 97 601B C2 601C 96 601D 12 601E 60 601F 40 6020 C2 6021 97 6022 D2 6023 96 6024 75 6025 B0 6026 50 6027 C2 6028 92

Lable

Mnemonic And Operand MOV SP, #50H

;Initialize stack

MOV P1, #7FH

;Blank Display

MOV P3, #00H

;Blank Display

UP: MOV P1, #00H SETB P3.4

Comment

;Enable all rows ;Enable column C3

LCALL DELAY CLR P3.4

;Disable column C3

MOV P1, #7FH

;Disable all rows

MOV P3, #0FFH

;Enable all columns

SETB P1.7

;Enable C5

CLR P1.6

;Enable R7

LCALL DELAY CLR P1.7

;Disable C5

SETB P1.6

;Disable R7

MOV P3, #00H

;Disable all columns

CLR P1.2

;Enable R3

Continued……….

INTERFACING OF DOT MATRIX DISPLAY USING 8051 Memory Address 6029 602A 602B 602C 602D 602E 602F 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 603A 603B 603C 603D 603E 603F

OP CODE D2 B1 12 60 40 D2 92 C2 B1 C2 91 D2 B3 12 60 40 D2 91 C2 B3 02 60 09

6040 6041 6042 6043 6044

76 FF D8 FE 22

Lable

Mnemonic And Operand SETB P3.1

Comment ;Enable C1

LCALL DELAY SETB P1.2

;Disable R2

CLR P3.1

;Disable C1

CLR P1.1

;Enable R2

SETB P3.3

;Enable C2

LCALL DELAY SETB P1.1

;Disable R2

CLR P3.3

;Disable C2

LJMP UP

DELAY:

MOV R0, #0FFH

;Initialize counter

HERE:

DJNZ R0, HERE

;Decrement counter if not zero go to HERE

RET

Question Bank 1.

How a port can be made input port?

2.

Give memory organization of 8051 family.

3.

How an element on matrix display can be made on?

4.

Explain the difference between LJMP and SJMP.

5.How to calculate the relative address for forward and backward jump? 6. What bit addresses are assigned to P3?