Microprocessor

Microprocessor • • •

• • •

Heart of a Microprocessor based computer It controls memory and IO through a series of connections called busses. Three main tasks 1. Data transfer b/w itself, memory or IO 2. Simple arithmetic and logic operations 3. Program flow via simple decision Power of a microprocessor means the capacity to execute millions of instructions per second Data are operated upon from the memory or internal registers Data width of a microprocessor can be 8, 16,32,64

• Buses – common group of wires, transfer address, data and control information b/w the microprocessor and its memory and IO systems • Arithmetic and logic operations Addition , Subtraction, Multiplication, division, AND, OR NOT NEG, Shift, Rotate • Decisions Zero Sign Carry Parity Overflow

Intel 8086/8088 Microprocessors • • • •

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8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus Intel 8086 is a 16b microprocessor with 16b data registers, 16b ALU. Width of external data bus: 8086: 16b 8088: 8b Width of external address bus: 16b+4b=20b Maximum addressable memory is IM

Segment: Offset memory model Little-Endian Data Format

Internal organization EU

B IU A d d re s s B u s 2 0 b its

AH

AL

BH

BL

CH

CL

DH

DL

S U M M A T IO N

D a ta B u s

CS DS SP SS BP ES DI IO BI

Bus C o n tr o l

In te rn a l C o m m u n ic a tio n s R e g is te rs

8088 Bus

T e m p o r a ry R e g is te rs In s tru c tio n Q u e u e ALU

F la g s

EU C o n tr o l

1

2

3

4

• 8086/8088 consists of two internal units – The execution unit (EU) - executes the instructions – The bus interface unit (BIU) - fetches instructions, reads operands and writes results • The 8086 has a 6B prefetch queue • The 8088 has a 4B prefetch queue

BIU Elements • Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction – The memory interface is slower than the processor execution time so this speeds up overall performance • Segment Registers: – CS, DS, SS and ES are 16b registers – Used with the 16b Base registers to generate the 20b address – Allow the 8086/8088 to address 1MB of memory – Changed under program control to point to different segments as a program executes • Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register

EU Elements •

Internal Registers AX – Accumulator BX – Base Index CX – Count DX – Data

SP – Stack Pointer BP – Base Pointer DI – Destination Index SI – Source Index

IP – Instruction Pointer FLAGS – Flag register Temporary registers All are 16 bit registers. AX,BX,CX,DX registers can be used as 8bit registers by naming AH &AL, BH & BL,CH & CL and DH & DL. •

EU control – Controls the Execution unit

8086/88 Device Specifications • • • •

Both are packaged in DIP (Dual In-Line Packages). 8086: 16-bit microprocessor with a 16-bit data bus 8088: 16-bit microprocessor with an 8-bit data bus. POWER Supply Requirements Both require +5V Supply voltage 8086: Draws a maximum supply current of 360mA. 8086: Draws a maximum supply current of 340mA. 80C86/80C88: CMOS version draws 10mA with temp spec -40 to 225degF. Input/Output current levels:

8086/88 Pinout

8086 In Detail

Pin Functions 1

AD15-AD0 :

Multiplexed address (ALE=1) /data bus(ALE=0).

2

A19/S6-A16/S3 (multiplexed) :

High order 4 bits of the 20-bit address OR status bits S6-S3.

3

M/IO :

Indicates if address is a Memory or IO address.

4

RD :

When 0, data bus is driven by memory or an I/O device.

5

WR :

Microprocessor is driving data bus to memory or an I/O device. When 0, data bus contains valid data.

6

ALE (Address latch enable) :

When 1, address data bus contains a memory or I/O address.

7

DT/R (Data Data bus is transmitting/receiving data. Transmit/Receiv e) :

8

DEN (Data bus Enable) :

Activates external data bus buffers.

9

INTR :

When 1 and IF=1, microprocessor prepares to service interrupt. INTA becomes active after current instruction completes.

10

INTA :

Interrupt Acknowledge generated by the microprocessor in response to INTR. Causes the interrupt vector to be put onto the data bus.

Pin Functions

11

NMI :

Non-maskable interrupt. Similar to INTR except IF flag bit is not consulted and interrupt is vector 2.

12

CLK :

Clock input must have a duty cycle of 33% (high for 1/3 and low for 2/3s)

13

VCC/GND :

Power supply (5V) and GND (0V).

14

MN/ MX :

Select minimum (5V) or maximum mode (0V) of operation.

15

BHE :

Bus High Enable. Enables the most significant data bus bits (D 15 -D 8 ) during a read or write operation.

16

READY :

Used to insert wait states (controlled by memory and IO for reads/writes) into the microprocessor.

17

RESET :

Microprocessor resets if this pin is held high for 4 clock periods. Instruction execution begins at FFFF0H and IF flag is cleared.

18

TEST :

An input that is tested by the WAIT instruction. Commonly connected to the 8087 coprocessor.

19

LOCK

Lock output is used to lock peripherals off the system. Activated by using the LOCK: prefix on any instruction.

20

HOLD:

Requests a direct memory access (DMA). When 1,  microprocessor stops and places address, data and  control bus in high­impedance state. 

21

HLDA (Hold  Indicates that the microprocessor has entered the hold  Acknowledge) : state. 

22

RO/GT1 and  RO/GT0 :

Request/grant pins request/grant direct memory  accesses (DMA) during maximum mode operation. 

23

QS1 and QS0 :

The queue status bits show status of internal  instruction queue. Provided for access by the  numeric coprocessor (8087). 

QS1

QS0

Function

0

0

Queue is Idle

0

1

First Byte of Opcode

1

0

Queue is empty

1

1

Subsequent byte of opcode

24 : S7, S6, S5, S4, S3, S2, S1, S0 S7: Logic 1, S6: Logic 0. S5: Indicates condition of IF flag bits. S4-S3: Indicate which segment is accessed during current bus cycle:

 S2, S1, S0 : Indicate function of current bus cycle (decoded by 8288). 

8284A Clock Generator Single 18 pin chip Clock Generator for 8086and 8088 Basic functions: • Clock generation. • RESET synchronization. • READY synchronization. • Peripheral clock signal.

Pin Functions 1

AEN1 &AEN2

Address enable pins to qualify the bus ready signal, RDY1 & RDY2

2

RDY1 & RDy

The bus ready provided in conjunction with the AEN1 & AEN2 pins to cause wait

3

ASYNC

Ready synchronization selection input selects either 1 or 2 stages of synchronization

4

READY

It is an output pin connected to 8086/8088.

5

X1 & X2

Crystal oscillator pins connect to an external crystal used as timing source

6

F/C

The frequency/ crystal select input

7

EFI

External frequency input.

8

CLK

The clock output pin provides the CLK input signal to 8086/8088. It is one third of the Crystal or EFI signal

9

PCLK

Peripheral clock signal-is one-sixth the crystal or EFI input

10

OSC

Oscillator output-same frequency as the crystal or EFI, it provides the EFI input to other 8284A.

11 RES

The reset input is connected to an RC network that provides poweron resetting

12 RESET

The reset output connected to 8086/8088 RESET input pin.

13 CSYNC

Clock synchronization pin used whenever EFI input provides synchronization.

14 GND

Ground pin connects to ground

15 VCC

Power supply connected to +5v

Operation of 8284A

Three operations • Clock Generation • Reset Synchronization • Ready Synchronization Top half of the logic dig. Represents the clock and reset synchronization. Clock section • If a crystal is attached to X1 & X2 The Oscillator generates a square wave signal at the same frequency as the Crystal. •

This signal is fed to OSC out put through an inverting buffer. This o/p can be connected to the EFI of another 8284A.

•

The AND gate circuit is used to select EFI or the Oscillator generated wave with the help of F/C input.

• •

This selected output is steered through to the divide by 3 counter. the out put of this counter is used as 1) timing for ready synchronization 2)signal to another divide by 2 counter 3)clock signal to 8086 and 8088 The clock signal is buffered before it leaves from the 8284A The out put of the second counter gives a divided by six signal and it is used as the PCLK.(peripheral clock)

• •

Reset section • It is simple and includes a Schmitt trigger buffer and a single D flip-flop • The D flip flop ensures the timing of the 8086/8088 RESET input are met. • This reset out put is given to the microprocessor in the –ve edge of the clock and the mp will sample the reset input in the +ve edge of the clock.

Figure shows 8284A is connected to 8086 • • • •

15MHz crystal provides 5MHz CLK and 2.5MHz PCLK The RC circuit provides a login 0 to RES, when power is first applied After some time it becomes 1 because of capacitor charges A push button switch allows the microprocessor to be reset by the operator • The reset input to become a logic 1 no later than four clock after system power is applied ,( this is accomplished by the flip flop) • and to be held high for at least 50Micro second (this is achieved by RC time constant)

Figure shows 8284A is connected to 8086

BUS BUFFERING AND LATCHING Latching - For de-multiplexing the multiplexed buses eg AD0-AD15 of 8086.Pins are shared to reduce the number of pins of the chip. Buffering – The system must be buffered if it contains more than 10 other components connected to it, because the fan out is10.

Demultiplexing the buses •

Memory and IO require that the address remains valid and stable through out a read or write cycle. Demultiplexing 8088 • Two 74LS373 transparent latches are used for demultiplexing 1) AD0-AD7(address and data connection) 2) A19/S6 – A16/s3 (Address/ status connection) • Latch is like wires, here when ALE=1, the latch pass the input to the output., and when ALE becomes 0 which causes the latches to remember the input. Here A0-A7 are stored in the bottom latch and A19-A16 is stored in the top latch.

Demultiplexing 8086 with 3 74LS373 transparent latches. 1. AD0-AD7 2. AD8-AD15 3. A16/s3 – A19/s6, BHE/S7 Here the memory and IO system see the 8086 as a device with a 20 bit address bus(A19-A0), a 16 bit data bus(D15-D0), and a three line control bus M/IO,RD and WR.

Buffering • The demultiplexed pins are already buffered by the 74LS373 latches. • The buffer’s output currents have been increased so that more TTL unit loads may be driven • A fully buffered signal will introduce a timing delay to the system

Fully buffered 8088 It uses 2 74LS244 octal buffer and a 74LS245 octal bidirectional buffer and 2 74LS373 latches. 373 – Address lines A0-A7 and A16-A19 244 - Address lines A8-A15 245 – Datalines D0- D7 244 – Control bus signals (IO/M,RD,WR) The direction of 245 is controlled by DT/R, and it is enabled and disabled by DEN.

Fully buffered 8086 It uses a 74LS244 octal buffer and 2 74LS245 octal bidirectional buffer and 3 74LS373 latches. 373 - Address lines A0-A19 245 – Datalines D0- D15 244 – Control bus signals (IO/M,RD,WR) The direction of 245 is controlled by DT/R, and it is enabled and disabled by DEN.

Bus Timing • Basic bus operation • Three buses - Address, Data, Control • Basic operations are Reading and writing 1)Writing: • Dump address on address bus. • Dump data on data bus. • Issue a write ( WR ) and set M/ IO to 1 to write to memory in 8086(IO/M to 0 in 8088).

• Reading: • Dump address on address bus. • Issue a read ( RD ) and set M/ IO to 1 to read from memory in 8086(IO/M to 0 in 8088). • Wait for memory access cycle.

• • • • • •

Timing in general

Use the memory and IO in periods called bus cycles. One cycle is 4 system clocking periods(T states) If system CLK is 5 MHz the One cycle is 800ns. Ie one T state is 200ns Mp reads or writes data 1.25 million times in a second. During T1 • Address of the memory or IO is sent out of the Address bus • Control signals ALE,DT/R, and IO/M or M/IO are also output.

• During T2 • Issues RD or WR signal, and DEN • In case of write Data to be written appear on the data bus. • READy is sampled at End of T2.

• During T3 • If READY is low the T3 becomes a wait State (Tw)I. • Allows memory time to access data • In the case of read The data bus is Sampled at the end of T3

• During T4 • All bus signals are deactivated for the next bus cycle. • Also samples the databus for data that are read from the memory or IO • The trailing edge of the WR signal Transfers data to memory or IO.

Read Timing

Bus Read Cycle (Memory or I/O) • The 4 processor clock cycles are called T states. Four cycles is the shortest time that theprocessor can use for carrying out a read or an input cycle. • At the beginning of T1, the processor outputs S2, S1, S0, A16/S3… A19/S6, AD0..AD15 and BHE#/S7. • The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address to pass through the transparent latches (74HC373). The address, along with the BHE# signal is latched when ALE goes low, providing the latched address A0..A19. • During T2 the processor removes the address and data. S3..S6 status is output on the upper 4 address/status lines of the processor. • The AD0..AD15 signals are floated as inputs, waiting for data to be read. • Data bus transceivers (74HC245) are enabled towards the microprocessor (the READ direction) by the DT/R# and DEN signals. • The RD signal is asserted. • The signals are maintained during T3. At the end of T3 the microprocessor samples the input data. • During T4 the memory and I/O control lines are de-asserted.

Write Timing

Bus Write Cycle (Memory or I/O) • The 4 processor clock cycles are called T states. Four cycles is the shortest time that the processor can use for carrying out a write or an output cycle. • At the beginning of T1, the processor outputs S2, S1, S0, A16/S3…A19/S6, AD0..AD15 and BHE#/S7. • The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address to pass through the transparent latches (74HC373). The address, along with the BHE# signal is latched when ALE goes low, providing the latched address A0..A19. • During T2 the processor removes the address and data. S3..S6 status is output on the upper 4 address/status lines of the processor. • Output data is driven out on the AD0..AD15 lines. • Data bus transceivers (74HC245) are enabled away from the microprocessor (the WRITE direction) by the DT/R# and DEN signals. • The MWRC# (ie MEMW#) or IOWC# (IOW#) signal is asserted at the beginning of T3. • The signals are maintained during T3. • During T4 the memory and I/O control lines are de-asserted. In simple Intel Architecture systems, the data is usually written to the memory or output device at the rising edge of the MWRC# or IOWC# signal.