Memoryiointerfacing.pdf

Basic Peripherals and Their Interfacing with 8086

Semiconductor Memory Interfacing Semiconductor memories are of two types: RAM and ROM. The semiconductor memories are arranged as two dimensional arrays of memory locations. For example, 1K X 8 memory chip contains 1024 locations and each of them is one byte wide. i.e. 1024 bytes of information can be stored in that chip. Each location should have an address. So, there has to be certain number of address lines on the memory chips. If we designate it as n, then n = log2N, where N is the number of locations that could be addresses in that chip. For 1K chip n would be 10, for 2K it is 11, for 4k it will be 13 etc. If a microprocessor has x address lines and if a RAM/EPROM IC is to be interfaced which has y lines (x > y), then we connect y lines from microprocessor to those of memory chip. Remaining x-y lines of microprocessor are used for address decoding. Main aim of this decoding circuit is to select one location for the address sent from microprocessor. The general procedure for interfacing static memory to 8086 is as follows: 1. Arrange the available memory chips so that they form a 16 – bit data bus and there should be a provision to access bytes as well as words. 2. Connect address lines, control signals like read, write of the microprocessor with those of memory chip. 3. Remaining address lines along with A0 and BHE are used for decoding the required chip select signals for odd and even banks. Absolute decoding is preferred even though we may have to go for linear decoding sometimes when an application demands. As far as possible, there should not be any windowing in memory map unless otherwise specified and try to avoid foldback. Let us consider some examples: E1. Interface two 4K X 8 EPROMs and two 4K X 8 RAM chips with 8086. Select suitable maps. First we have to write the memory map fro the problem given. It will reveal the logic to be used for decoding circuit. Since the first instruction is fetched from FFFF0h after the microprocessor is reset, we will make that address to be present in EPROM and write the memory map as follows. And, to avoid windowing let us keep the locations to be present in the RAM as immediate addresses. Locations having addresses from FFFFFH to FE000H are allocated to EPROM1 and 2. Immediate address map FDFFFH to FD000H is allocated to RAM1 and 2. The line which is differentiating EPROM from RAM if A13. Let us use it along with A0 and BHE to identify odd and even banks.

-1-

Basic Peripherals and Their Interfacing with 8086

Memory A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address in Flex

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

FFFFFH To FE000H

1

1

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

FDFFFH To FD000H

Since there is continuous address map, we can use a decoder to decode the chip select signals. The inputs for the decoder would be a13, A0 and BHE .

A13 0

A0 0

BHE

0

Chip Selected Even & Odd RAM

Data transfer Word

0

0

1

Even in RAM

Byte

0

1

0

Odd in RAM

Byte

1

0

0

Even & Odd in ROM

Word

1

0

1

Even in ROM

Byte

1

1

0

Odd in ROM

Byte

As the table shows, when the decoder output O0 is enabled it selects both even and odd banks in RAM. Then A0 and BHE can be used accordingly to select only even or only odd bank. Similarly, EPROM is selected by O4. The complete Interface diagram is shown below:

-2-

Basic Peripherals and Their Interfacing with 8086

Control Bus from 8086

Data Bus

MEWR

Address Bus

MERD A1 – A12

BHE

A0

A0

A1

A13

A2

E0 E1

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 E2

D0 – D7

D8 – D15

A0 – A11

0 1 2 3 4 5 6 7

A0 – A11

D0 – D7

D8 – D15

OE

OE CS1

CS2

A0 – A11

A0 – A11

D0 – D7

D8 – D15

RD

RD

WR

WR CS3

0

5 CS1 6

CS3 1 0

5 CS2 7

CS4

CS4 2

-3-

Basic Peripherals and Their Interfacing with 8086

E2: Interface two chips of 16K X 8 EPROMs and two chips of 32 X 8 RAM chips to 8086 microprocessor. Select the starting address of EPROM suitably, but the RAM address must start at 00000H. First let us write the memory map. If you observe the memory map, it shows that the address map is not contiguous. Hence we will use logic gates instead of decoder to design decoding logic.

Memory A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address in Flex

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FFFFFH To F8000H

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0FFFFH To 00000H

Memory map for E2 E3: It is required to interface two chips of 32K X 8 ROM and four chips of 32K X 8 RAM with 8086 according to following map. ROM1 and 2: F0000H – FFFFFH RAM1 and 2: D0000H – DFFFFH RAM3 and 4: E0000H – EFFFFH The necessary memory map is shown below and Interface diagrams is shown next to previous problem solution. Memory Map for E3: Memory A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address in Flex

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FFFFFH To F0000H

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

DFFFFH To D0000H

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

EFFFFH To E0000H

-4-

Basic Peripherals and Their Interfacing with 8086

Interfacing Diagram for E2 Control Bus from 8086

Data Bus

Address Bus

MEWR

MERD A1 – A14

D0 – D7

D8 – D15

A1 – A15

A0 – A13

A0 – A13

D0 – D7 ROM EVEN

OE

D8 – D15 ROM ODD

OE CS1

CS2

A0 – A14

RD

A0 – A14

D0 – D7

D8 – D15

RAM EVEN

RAM ODD

WR

WR CS3

A0

CS4

A0 CS1

CS3

A15

A16

A19

A19 CS2 BHE

RD

CS4 BHE

-5-

Basic Peripherals and Their Interfacing with 8086

Interfacing Diagram for E3

Control Bus from 8086

Data Bus

Address Bus

MEWR

MERD A1 – A15

D0 – D7

D8 – D15

A0 CS1 A16

A0 – A14

A0 – A14

D0 – D7

A19 CS2

OE

D8 – D15 OE

BHE CS1

A0 – A14

CS2

A0 – A14

A0 D0 – D7

CS3

A16 A17 A 7 18 7A19

RD

D8 – D15 RD

WR

WR CS3

CS4

CS4

BHE

A0 – A14

A0 CS5

A16 A17 A 7 18 7A19

D0 – D7 RD

CS6 BHE

A0 – A14 D8 – D15 RD

WR

WR CS5

CS6

Observe this

-6-

Basic Peripherals and Their Interfacing with 8086

Interfacing Memory to 8088 microprocessor Interfacing memory to 8088 microprocessor is very simple and similar to interfacing memory to 8085 microprocessor. The external data bus width of 8088 is only 8 – bits. So, there is no need to divide the memory as even and odd bank. There is no BHE signal on 8088 microprocessor and no special significance to A0 signal. It will be directly connected to address lines of memory chips. The number of address lines of microprocessor connected to memory IC is equal to number of address lines on that IC and remaining address lines are connected to a decoding circuit. Here decoding logic is used not to identify odd or even bank, it is to select a memory chip, rather. Let us study this by taking an example problem. E4: Interface eight 4K X 8 EPROMs to 8088 microprocessor. Select suitable memory maps.

Memory A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address in Flex

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

FFFFF TO FF000 FEFFF TO FE000 FDFFF TO FD000 FCFFF TO FC000 FBFFF TO FB000 FAFFF TO FA000 F9FFF TO F9000 F8FFF TO F8000

Memory Map for the interfacing EPROMs to 8088

-7-

Basic Peripherals and Their Interfacing with 8086

The Interface diagram is shown below

A0 – A11

Address

4K X 8 Data

F8000 – F8FFF A12

A0

F9000 – F9FFF

A13

A1

FA000 - FAFFF

A14

A2

FB000 - FBFFF 74LS138

IO/M A15 A19 +5 V

FC000 - FCFFF

E1

FD000 - FDFFF

E2

FE000 - FEFFF

E3

FF000 - FFFFF

D0 – D7 RD

OE CS CS CS CS CS CS CS CS

-8-

Basic Peripherals and Their Interfacing with 8086

Interfacing I/O Ports I/O devices work with mechanical speed where as microprocessor works with electronics speed. There is always speed and data type incompatibility between them. So, we use some devices which establish communication between microprocessor and I/O devices. They are called I/O ports. They are actually high speed registers controlled by a command register. We can configure command register in such a manner where in which each bit in the command register corresponds to a bit in I/O port or each bit controls the direction of data flow in an entire I/O port. For example, a 1 at a particular bit position in command register indicate all the bits of a port send data to microprocessor. That is they act as input ports. Input activity indicates reading data from external device like keyboards, joy sticks, mouse etc. That is why they are called input devices. Output activity transfers data from the microprocessor to the external devices like monitor, 7 – segment display, printer etc. So, they are called output devices. After executing an OUT instruction, data appears on the data bus and simultaneously a device select signal is generated from the address and control signals. The data should be saved or latched till next data arrives at the input of the device. Also if the output port is to source large currents, the port lines must be buffered. We make use of 74LS373 for this purpose. It contains eight buffered latches and hence can be used as 8 bit port. Following diagram shows the pin diagram of 74LS373:

OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND

1 2 3 4 5 6 7 8 9 10

74LS373

20 19 18 17 16 15 14 13 12 11

VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLK

The chip 74LS245 has 8 buffers and can be used as an 8 – bit input port. 74LS245 is a bidirectional buffer. There is a signal called DIR upon it. This signal determines the direction of

-9-

Basic Peripherals and Their Interfacing with 8086

information flow. Let us keep it at 0, since we use the IC as input port. Signals present on 74LS245 are as shown below: If DIR is 1, then direction is from A to B lines otherwise, the data flow direction is from B to A pins.

DIR A0 A1 A2 A3 A4 A5 A6 A7 GND

1 2 3 4 5

74LS245

6 7 8 9 10

20 19 18 17 16

VCC

15 14 13 12 11

B3

CS B0 B1 B2

B4 B5 B6 B7

Methods of Interfacing I/O devices There are two ways by which one can interface I/O devices to a microprocessor. i) I/O mapped I/O and ii) Memory mapped I/O. In memory mapped I/O, the 1 Mb memory that can be interfaced to 8086/8088 itself is used to address I/O devices. But in I/O mapped I/O there is a separate address space for I/O devices. Some important differences between I/O mapped I/O and memory mapped I/O are listed below: Memory mapped I/O 1. 20 – bit address is used 2. Virtually 1M devices can be connected 3. All memory related instructions can be used like mov, add etc. 4. MRD and MWR signals are used 5. Data transfer can be between I/O and any register 6. Decoding circuit is complex since there are 20 address lines

I/O mapped I/O 1. 16/8 bit address is used 2. 64K or 256 devices can be connected. 3. Only IN and OUT instructions are used 4. IORD and IOWR signals are used. 5. Data transfer is between I/O and AX register only 6. Decoding circuit is comparatively simpler

- 10 -

Basic Peripherals and Their Interfacing with 8086

Memory mapped I/O is seldom used. Hence we will learn interfacing some devices using I/O mapped I/O. Address of the port is 0740H. I1: Interface 8 switches to 8086 microprocessor and read their status (1 – ON, 0 – OFF). Store this information in a register. The Interface diagram is shown below:

IORD

O7

74LS245 D0 – D7

8086 Microprocessor

DIR A15 A14 A13

O0

A12 A11 A10

VCC

A9 A8 IORD A7 A6 A5 A4 A3 A2 A1 A0

The code to read and store the status of switches is as follows:

MOV DX, 0740H ; Variable port addressing mode, hence keep port address in DX register IN AL, DX ; AL will receive the status of switches. MOV BL, AL

- 11 -

Basic Peripherals and Their Interfacing with 8086

I2: Interface 8 switches to 8086 microprocessor and read their status (1 – ON, 0 – OFF). Count the number of 1’s in the byte received. Store this information in a register. The interface diagram is as same as above. The code is as follows:

REPEAT:

NEXT:

MOV DX, 0740H IN AL, DX MOV AH, 00 MOV CX, 00 ROR AL,1 JNC NEXT INC AH

; TO HOLD BIT COOUNT ; NUMBER OF TIMES THE INFORMATION TO BE CHECKED ; IF THERE IS A CARRY, INCREMENT THE COUNTER

LOOP REPEAT MOV BH, AH

; STORE BIT COUNT IN A REGISTER

I2: Interface 8 switches to 8086 microprocessor and read their status. Count the number of 1’s in the byte received. Display it on a seven segment display. Input port address is 0008H and output port address is 000AH. The Interface diagram is shown below. Here we are not decoding the entire address bus. Instead, we used only least significant 4 bits to decode the input and output devices. It creates a problem called foldback where a device has multiple addresses. Since we are not using this interface in any other application, we can sometimes use linear decoding also like this. Sample code is as follows:

REPEAT:

NEXT:

MOV BL, 00 MOV CX, 08H IN AL, 08H ; fixed port addressing mode ROR AL, 1 JNC NEXT INC BL LOOP REPEAT MOV AL, BL OUT 0AH, AL

; to check for 1

; sending information to 7 – segment display connected to port 0AH

- 12 -

Basic Peripherals and Their Interfacing with 8086

IORD

O7 74LS245 D0 – D7

8086 Microprocessor

DIR A3 A2 A1

O0

A0

CS

IIORD

Vcc

IOWR

CLK D0 – D7

74LS373 A3 A2 A1

Decoder

CS

A0

- 13 -