Magazine Issue 1

Tech Cuts: DIGITAL SIGNAL PROCESSING – AN OVERVIEW Signal Processing is an approach to extract the desirable information from the signal using suitable tools. The signal is defined as any physical quantity that varies with time, space or any other independent variable or variables. The signals may be classified based on their nature and characteristics in the time domain as either continuous or discrete time signals. A continuous time signal is a function that is specified for all values of time. On the other hand a discrete time signal is specified for discrete values of time. The signal from a function generator is an example for continuous time signal and the digital clock output is for discrete time sequence. Most of the signals encountered in science and engineering are continuous in nature. The discrete time signals are obtained by sampling the continuous time signal at equidistant points, known as Sampling Process. A discrete time signal may have continuously varying amplitude or constant amplitude. The signal with constant amplitude is called quantized discrete time signal. The continuous time signal was processed using some mathematical tools and it was found that the analog signal processing was very expensive in terms of efficiency and accuracy in real time applications. The digital signal processing is widely preferred due to the following reasons Better Accuracy control: DSP provides superior control of accuracy, because the effects of aging and ambient temperature are not affecting its performance. Data Storage: The storage of digital or discrete data is very easy and can be stored in various storage media such as optical disks & magnetic tapes without any loss. Linear Phase Characteristics : DSP provides desirable linear phase characteristics while analog signal processing does not have linear phase. Implementation: Digital implementation of a system allows easy adjustment of the processor characteristics during processing. The characteristics can be altered simply by changing the values of the coefficients representing the processor in terms of algorithm.

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A basic DSP unit may consist of o

Data acquisition unit

o

Analog to digital converter

o

Processing board / software

o

Digital to analog converter

(enhanced

Data Acquisition Unit

signal)

Signal Processing Software

Analog to Digital Converter

(Continuous time signal)

Digital to Analog Converter

(Analog Signal)

(Processed Digital signal)

Although there are certain limitations like complexity and sampling speed of DSP, the advantages outweigh these disadvantages in many applications. Also the cost of the DSP hardware is decreasing continuously. Consequently, the applications of Digital Signal Processing are increasing rapidly. -Arjun Rajasekar

CISC (Vs) RISC In

this

article

we

are

going

to

talk

about

CPU

architecture.

RISC stands for reduced instruction set computer and CISC - for complex instruction set computer. The major difference is that RISC chips use simpler instructions sets to achieve higher clock frequencies and process more instructions per clock cycle than CISC processors. Typically CISC chips have a large amount of different and complex instructions. The

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philosophy behind it is that hardware is always faster than software; therefore one should make a powerful instruction set, which provides programmers with assembly instructions to do a lot with short programs. In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. Intel and AMD, for example, develop CISC processors (x86) while Apple and SUN use RISC architecture. Major problem of RISC - they don't afford the widespread compatibility that x86 chips do. There is still considerable controversy among experts about which architecture is better. Some say that RISC is cheaper and faster and therefore the architecture of the future. Others note that by making the hardware simpler, RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks. Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper anyway. RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. Further more today's CISC chips use many techniques So

formerly

simply

said:

RISC

associated and

CISC

with are

growing

RISC to

chips. each

other.

-Saravana Kumar

Lighter side: “That was close!” exclaimed the surgeon as he left the operation theater. “What do you mean?” asked a nurse. “A centimeter either way and I would have been out of my specialty!”. *** In mid-1944, during the V-1 raids on England, a buzz bomb hit a block of flats. After the dust had settled the heads were counted, only grandpa was missing. The rescue team heard laughter from the rubble and dug out grandpa, uninjured and still chuckling from the remains of the WC. What was so funny, the rescuers demanded. Replied grandpa,” I pulled the chain and the whole damn house fell down.”

Thought : Never pull a tiger’s tail, but once you do, don’t let go.

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Circuit debugging: Normally, false triggering of time IC555 takes place during power on, resulting in unwanted output, which starts the timer’s time cycle. The circuit becomes inefficient especially when the load has to be energized only when desired. Here is a simple circuit to eliminate false triggering of timer 555.The circuit is wired in monostable mode and grounded via N/O contact of RL(b) as well as switch S2. When power switch S1 is switched on, the circuit will not be grounded until switch S2 is momentarily pressed to provide the triggering pulse to the timer at pin 2. Press switch S2 momentarily. To activate the relay for operating the load, switch on the power to the circuit by pressing switch S1 and then S2 momentarily. The resulting output at pin 3 goes high and energizes relay RL to operate the load. Now after momentarily pressing S2, the circuit remains on as GND gets connected to N/O contact of RL(b). At the same time, pin2 is disconnected from N/C contact of RL(b), which prevents further triggering. The time period for relay energisation (approximately 3 minutes) can be easily changed by changing the values of resistor R1 and capacitor C1 according to the requirement to operate the load. At the end of the cycle, the relay gets de-energized and the circuit becomes ungrounded again.

-Santosh.P

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Future zone:

Common Aptitude Test-CAT CAT examination is conducted by the Indian Institute of Management (IIM) .it is held in the last week if November every year. A CAT paper consists of three sections. Data interpretation: A set of data will be given and questions will be asked based on that data. This section also includes data sufficiency. Basic mathematics: High school maths forms this section. Questions will be based on percentage, logarithms, time & work, geometry etc. Verbal: Questions are framed mainly to test your vocabulary skills. Synonyms, sentence correction and comprehension form the major part. Each section consists of 50 questions. The duration is 2 hrs. A person willing to get a call from any one of the IIM’s must attend atleast 80-100 questions. Mathematics forms the time consuming and difficult section. There are about 6 IIM’s in India, one each in Ahmedabad, Bangalore, Kol Katta, Kozhikode, Lucknow and Indore. IIM-A (Ahmedabad) is considered to be the most difficult business school to get into in the world. Academics wise, it ranks fourth in the world. About 1,50,000 students write CAT exam every year. Only 4000 of them get calls from IIM. CAT needs a regular preparation for a period of about 5 to 6 months. In CAT, choosing the correct question plays the key part. 0.33 marks will be deducted for every wrong answer. Every correct answer gets 1 mark. CAT score is valid till next CAT exam is held. An application form costs about 1200 Rs. Programs: The following programs have appeared in company Q-papers. Try them out. 1. Write a program to reverse a string without using a temporary variable and without using another array to store the string. 2. Reverse a floating point number (e.g: 123.45  321.54) 3. To find whether a given no. is a power of 2 preferable by using bit operators. 4. To reverse a linked list Puzzle: An escalator is descending at constant speed. A walks down and takes 50 steps to reach the bottom. B runs down and takes 90 steps in the same time as A takes 10 steps. How many steps are visible when the escalator is not operating? -Placement Representatives

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Hot n’ Happening: 

Here are the events, activities and everything that’s been happening in the campus for the past two weeks.



To start with, as a part of the placements that has been going on since May, E- Funds, a software company visited our campus and recruited students. Our students attended off – campus placement at PSG Tech for Oracle and IT Solutions.



The admissions for freshers have been going on for the past one week. Our students also had to face their first unit tests on the 9th, 10th & 11th of July. The performance of the students turned out to be an average in most of the subjects.



Our college also witnessed the transfer of senior faculty members to the other colleges. The placement activities of our class gained pace with a series of aptitude tests in Circuits, C, general aptitude and quantitative aptitude.



As a measure to facilitate the students to perform better in the personal interviews, mock interviews were conducted.



Entertaining yet informative activities like Quiz, marketing events, group discussions, extempore, JAM (just a minute) sessions, and seminars drew great response from our students.



Bureau of Indian Standards (BIS) conducted a seminar on standardization in our college which turned out to be very useful for the students. That’s Hot ‘N’ Happening in our campus… -R.Preeti

Vocab Builder: impetus : driving force; impulse or stimulus.(Latin) The impending arrival of summer can be an impetus for staring a diet. hiatus: interruption or break(Latin) Vacation is a desirable hiatus from work. sunder: to separate(old English) Relationships can be sundered by the stresses of modern life. blandish: to influence with flattery.(Latin) No matter how much you blandish me, I will not go to the party with you. pathos: sense of compassion ; pity(Greek) The doctor’s lack of pathos made him ineffective with patients. Ram Prasad.V

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Acknowledgements ‘THE SPIRIT’ has evolved from the sparks emulating from the hearts and minds of III EEE. We thank our patron and Head of the Department, Dr.A.Ebenezer Jeyakumar for his encouragement and guidance. We would also like to thank our Faculty Advisor, Dr.N.Devarajan for his support and ideas. We would also like to thank all those who are behind us and have helped us realize this magazine. Above all, we would like to thank the Almighty for being with us . III-EEE

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