Low-leakage Robust Sram Cell Design For Sub-100nm

6B-2

Low-leakage Robust SRAM cell design for Sub-100nm Technologies †Shengqi Yang, †Wayne Wolf, ¶Wenping Wang ‡N. Vijaykrishnan and ‡Yuan Xie †Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544 ¶Department of Microelectronics, Peking University, Beijing, 100871 ‡Microsystems Design Lab, The Penn State University, University Park, PA, 16802 {shengqiy|wolf}@princeton.edu {wangwp}@ime.pku.edu.cn {vijay|yuanxie}@cse.psu.edu Abstract— A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these important issues have been separately addressed in previous SRAM designs, there exists no design that simultaneously cuts down leakage power and enhances the resistance to soft error. In this work, we have built the first such SRAM cell, by hybrid of high-κ gate dielectric and dynamic threshold voltage which is realized in the form of jointly biased gate and substrate transistor. The HSRAM not only makes the gate leakage negligible, but lessens the severe increase of subthreshold leakage caused by Fringing/Field Induced Barrier Lowering (FIBL) effect accompanied with the introduction of high-κ gate dielectric, and in the same time reduces the susceptibility to soft error by increasing the node capacitance. Experiments were performed in both transistor level and circuit level for this novel HSRAM using ISE8.0 and HSPICE. They indicate that up to 93% reduction in total leakage is possible by using HSRAM cell, with an up to 23% increase in reliability degree and and an up to 73% reduction in bitline delay, compared to standard 6T SRAM.

I. I NTRODUCTION In order to achieve high integration density and high performance, semiconductor devices are aggressively scaled in each technology generation. According to the International Technology Roadmap for Semiconductors (ITRS) 2003 [1], the feature size will reach 65nm by 2007 and 45nm by 2010. Continuous decrease in feature size poses two critical issues for sub-100nm bulk CMOS design: leakage power consumption and soft errors. For sub-100nm technologies, subthreshold leakage power, gate direct tunneling leakage power and reverse-biased pn junction BandTo-Band Tunneling (BTBT) leakage power are dominant leakage components [2]–[4]. Dynamic power was once the dominant power consumption term. However, as the result of technology scaling, leakage power will soon account for a large portion of total power consumption [5]. Leakage power management is becoming indispensable for cost effective packaging and cooling solutions for high-end microprocessors, and it is critical for holding time design for batterysupported low-end mobile System-On-Chips (SOC). Since leakage power is proportional to the number of on-chip transistors, on-chip L1 and L2 caches, which comprise the vast majority of on-chip transistors and represent a sizable fraction of the total power consumption of microprocessors, should be paid much attention from the viewpoint of leakage. Recent power estimation for 100nm process indicates that leakage power accounts for 30% of L1 cache power and as much as 80% of L2 cache power [6]. With technology scaling, leakage power consumption in Static Random Access Memory (SRAM) will become more significant. Soft errors or transient errors are circuit errors caused due to excess charge carriers induced primarily by external radiations [7], [8]. Radiation directly or indirectly induces a localized ionization which upsets internal data states. While these errors cause upset event, the circuit itself is not damaged. These errors are particularly Acknowledgments: This work was supported by National Science Foundation under Grant numbers CCR-0324869 and CCR-0329810.

0-7803-8736-8/05/$20.00 ©2005 IEEE.

troublesome for memory elements as the stored values of the bits are changed. These errors may or may not be noticeable or important to the user. However, when memory elements are used to control the functionality of the device, such as in an SRAM-based FPGA, soft errors can have a much more serious impact and lead not only to corrupt data, but also to a loss of functionality and system critical failures. Soft error phenomenon in memory was known to exist as early as 1970s. As the technology scales down, electronic components become vulnerable to soft errors as they use ever-smaller feature sizes and lower power supply voltage. Many design techniques have been proposed to reduce the subthreshold, gate and BTBT leakage power, including drowsy caches [9], [10], gated-supply voltage (Vdd ) technique [11]–[13], gated-ground technique [14]–[16], asymmetric-cell or dual-threshold voltage (Vth ) SRAM cache [17]–[20], multi-Vth and multi-level cache [21]–[23], reverse/forward body-biased SRAM cache [6], [24]– [26], etc. At the time these SRAM design techniques paid much attention on the leakage reduction, however they neglected a very important issue, the immunity of these techniques to soft error when changing the supply voltage, ground and circuit structure. A recent work [27] compared the soft error rates of some recently proposed SRAM leakage optimization approaches, without considering the gate leakage and BTBT leakage. In this paper, we propose a novel low-leakage robust SRAM cell design, i.e., Hybrid high-κ gate dielectric and jointly-biased gate and substrate SRAM (HSRAM) cell. This novel HSRAM uses high-κ gate dielectric to suppress the gate direct tunneling leakage, and employs jointly-biased gate and substrate which suppress the Fringing/Field Induced Barrier Lowering (FIBL) effect caused by introduction of high-κ gate dielectric, realize dynamic threshold voltage and increase the node capacitance. Suppression of FIBL effect means less Vth shift resulting in less subthreshold leakage. Dynamic threshold voltage mechanism provides low-Vth under on-state and high-Vth under off state, which mean high driving ability under onstate and low subthreshold leakage under off-state. Increased node capacitance definitely increases the immunity of SRAM cell to soft errors. Furthermore, if we realize this SRAM cell in Silicon-OnInsulator (SOI) material, the BTBT leakage power can be greatly reduced. The contributions of this paper are: • •

A novel HSRAM cell design is presented to reduce all leakage power components and increase the immunity to soft error. The first comprehensive comparisons are done for prior SRAM design techniques and our SRAM cell in terms of soft error and leakage power consumption, including subthreshold leakage and gate leakage.

The remainder of this paper is organized as follows. Section II presents some background material and the motivation for this work. Section III describes the design of HSRAM cell in detail. Section IV discusses the experimental results and Section V concludes this paper.

539

ASP-DAC 2005

Gate Source

n+

guiding our following design. Consequently, we simplify the BSIM4 model and explain the gate leakage current as below:

Drain n−

p

+

i1

n−

i2

p

+

tox ·α −B· V

Igate = (A · C) · (W · L) e

n+

i3

i1 : Subthreshold Leakage i2 : Gate Leakage i3 : BTBT Leakage

−Bα −Bα ∂Igate tox = (AC)(W L)( )e Vgs ∂tox Vgs ∂Igate −Bα =( ) · dtox Igate Vgs

Significant leakage components for sub-100nm technologies.

II. BACKGROUND AND M OTIVATION In this section, we will elaborate on some background material that is helpful for understanding the remainder of this paper and furthermore is used to motivate the need for our novel SRAM design. Specifically, we discuss mechanisms, compact models, and typical reduction techniques for significant leakage components, including subthreshold leakage, gate direct tunneling leakage and BTBT leakage as shown in figure 1. We also review the primary source of radiations that induce soft errors and introduce the methodology for measuring the soft error rate. Finally, we point out the issues our novel SRAM cell design needs to address and motivation of this work. A. Leakage Power A.1 Subthreshold Leakage According to BSIM4 model, the equation governing subthreshold leakage current can be expressed as following: Isub = I0 e

Vgs −Vth nkT /q

V − kTds /q

(1 − e

(3)

For the information of these parameters, refer to [28]. We get A = 4.9589 × 10−7 A/V 2 (for NMOS), B = 6.6795 × 1010 (Kg/F · Sec2 )0.5 (for NMOS). Because Vgs and tox are scaled roughly by the same factor, and the leakage current is dominated by the exponential part, here we approximate parameter C as 0.7225 × 1018 V 2 /m2 . Using this simplified model, we can derive the dependence between gate leakage current and gate oxide thickness or gate voltage:

P-type Substrate

Fig. 1.

gs

)

(1)

where Vgs and Vds are gate to source and drain to source voltages. For the meaning of other parameters, refer to [28]. Now we simplify this model to guide our SRAM cell design. We assume the ratio between W and L is fixed for different technology nodes, and Vgs is equal to zero. Furthermore, we neglect the last term (1 − e−(Vds /(kT /q)) ) because Vds is larger by several orders of magnitude than the thermal voltage kT /q. While the drain induced barrier lowering (DIBL) effect is reflected on its effect on threshold voltage variation. Using these assumptions, we can draw a conclusion that the most contributing factor to the subthreshold leakage is the decreasing threshold voltage as described by the following equation: q dIsub =− dVth = 38.63dVth (T = 300K) Isub nkT

(2)

Observing this simplified Equation (2) we have two important conclusions. From the viewpoint of subthreshold leakage reduction, first, Vth of a CMOS transistor should be designed at a high value under off-state; second, Short Channel Effcts (SCE), for example DIBL effect and FIBL effect, should be suppressed to prevent the negative shift of Vth under both off-state and on-state. A.2 Gate Leakage Reduction of gate oxide thickness results in an increase in the field across the oxide. The high electric field coupled with low oxide thickness results in tunneling of electrons from substrate to gate and also from gate to substrate through the gate oxide for an N-type MOS (NMOS) (holes tunneling for PMOS), which is referred as the gate oxide tunneling current. To model this current, many equations were put forward, among which is the BSIM4 gate tunneling model [29]. But the original BSIM4 gate leakage model is too complex and a more simple model to capture the dependence between leakage current and gate oxide thickness or gate voltage is desirable for

Btox α −Bα ∂Igate tox = (AC)(W L)( )e Vgs 2 ∂Vgs Vgs Btox α ∂Igate =( ) · dVgs 2 Igate Vgs ∂Igate −Bα Btox α ) · dVgs =( ) · dtox + ( 2 Igate Vgs Vgs

(4)

(5) (6)

As a result, the feasible and efficient method to reduce gate leakage is increasing the physical thickness of the gate dielectric as illustrated in Equation (6). Reducing the gate voltage is another approach, for example, dynamic voltage scaling, but it is outside the paper’s scope. A.3 BTBT leakage For deep sub-micron technologies, the high substrate doping density and the application of the halo/pocket profile cause the drain-substrate and source-substrate pn junctions more susceptible to electron tunneling. In a highly reverse biased pn junction, the BTBT leakage current is due to the tunneling of electrons from the valence band of the p-region to the conduction band of the n-region. The BTBT leakage current can be greatly reduced when the SOI material, especially the Ultra-Thin-Body (UTB) SOI material [30], is used to substitute the bulk silicon. Moreover, our novel SRAM cell can be easily implemented using SOIMOS without big changes. As a simplification, we will neglect the BTBT leakage component in the following work. B. Soft Error B.1 Primary Source The primary source of radiations that induce soft errors can be classified as high energy neutrons from cosmic radiations, alpha particles from the packaging materials, and the interaction of cosmic ray thermal neutron with the Boron present in the p-type regions of the devices [27], [31], [32]. The most significant source of soft error is high-energy cosmic ray induced neutrons. The impinging neutrons knock off the silicon atom from its lattice. The displaced silicon nucleus breaks down into smaller fragments each of which generates some charge. The charge density is about 25 to 150f C/µm. For alpha particle, it strikes and penetrates the silicon substrate and finally loses its kinetic energy. Its positive charge induces electron-hole pairs through columbic interaction. A single alpha can generate anywhere from 4 to 16f C/µm over its entire range. The third source is the neutron induced 10 B fission. It absorbs the neutrons and breaks apart with the release of an alpha particle and 7 Li (Lithium). B.2 Soft Error Metrics For a soft error to occur at a specific node in a circuit, the collected charge Q at that particular node should be more than a critical charge Qcritical . If this happens, a pulse is generated and latched on, which results in a bit flip at that node. This concept of critical charge is

540

SER ∝ Nf lux ∗ CS ∗ e

−Qcritical QS

WL

'0'

used for estimating the sensitivity of SER. In [33], a method which models an exponential dependence of SER on critical charge for CMOS SRAM was developed and shown as:

BL

BL m4

m3

(7)

m5 n 0

where Nf lux is the intensity of the neutron flux, CS is the cross section area of the node, and QS is the charge collection efficiency. Qcritical is proportional to the node capacitance and the supply voltage. It decreases with the decreasing of voltage and node capacitance. In order to measure Qcritical for a particular node, we define it as: Z tcritical Qcritical = Idrain (t)dt (8) 0

where Idrain (t) is the drain current induced by the charged particle, and tcritical is the flipping time and in memory circuit it can be defined as the point at which the feedback mechanism of the back to back inverters will take over from the incident ion’s current. In the following HSPICE experiment, we model the particle striking current Idrain (t) as an exponential current waveform to account for funneling and diffusion charge collection. The current was injected at the most sensitive node and measured up to a point where the regenerative nature of the circuit takes over and commits a bit flip. Finally the current pulse was integrated to get the critical charge of that node. B.3 Soft Error Reduction Techniques In order to reduce Soft Error Rate (SER), one way is to use pure device material and shield the sensitive circuit from ionizing particles. But such solutions are generally not effective for the highly penetrative neutron rays besides the additional cost. Another way is to increase the node capacitance because of the proportion between Qcritical and node capacitance. However, a distinction should be drawn between two kinds of capacitances. The capacitances from gates or interconnect are healthy and provide robustness for they have little impact on the charge collection process during a soft error event. But we need to trade off the gain from robustness and the loss in the SRAM access time. By adding diffusion capacitance, we increase the total diffusion area at the node, which results in an increase of the charge collecting efficiency during a strike. Hence, this can offset the benefits of the increased node capacitance on Qcritical . In the following work, we will focus on optimization of gate capacitance. C. Motivation The above detailed analysis demonstrates the need for our novel SRAM design to address the following issues: • Cutting down the gate direct tunneling leakage by gate dielectric engineering. • Reducing the subthreshold leakage by introducing techniques to suppress the Vth -shift caused by SCEs, such as FIBL and DIBL. • Improving the immunity of the SRAM cell to soft errors by adjusting node capacitance. • Trading off the robustness and memory access time by elaborately selecting the gate capacitance. III. N OVEL HSRAM D ESIGN In this section, We present the design philosophy and implementation of our novel HSRAM cell. A. Leakage and SER Analysis of Standard 6T SRAM Cell Figure 2 illustrates the dominant leakage components and the nodes which are the most sensitive to soft errors (SE) in a standard 6-transistor (6T) SRAM cell that is storing ’0’ and in standby mode (not accessed). The leakage through m5 and m6 depends on the voltage at which bitlines are pre-charged. Normally BL and BL are pre-charged to Vdd . As the figure shows all the 6 transistors, especially m2, m6 and m3, suffer from large gate leakage. And this

'0'

Vdd

'1'

'0'

m1

n1

m6

m2

'1'

'1'

Gate Leakage Subthreshold Lekage

Fig. 2. Dominant leakage components and sensitive nodes in a standard 6T SRAM cell which is in a standby mode and storing ’0’. Gate Gate

Source

n+

n−

Drain n−

n+

Electric line Drain

Source

n+

n−

n−

P-type Substrate

P-type Substrate

(a) SiO2-NMOS

(b) High k-NMOS

n+

Fig. 3. Illustration of FIBL effect. Thicker gate dielectric means more fringing fields from the gate to the source/drain, and severer FIBL effect.

gate leakage strongly depends on gate to source/drain voltage and gate dielectric thickness. For the subthreshold leakage, it is affected by the number of off transistors in a leaky path. Higher the number of off transistors, lower the subthreshold leakage through that path. In an SRAM cell, there are three subthreshold leakage paths that have only one off transistor. For sub-100nm technologies, gate leakage is the most important component. As a result, leakage reduction techniques should focus on the gate leakage and reduce the negative side-effect on subthreshold leakage and other aspects. Also in the following experiments, the Qcritical is estimated only at specific nodes n0 and n1 which are most sensitive to SE. Current pulses which model the charge generation due to the radiation are supplied to these nodes and the Qcritical for both 0 to 1 and 1 to 0 bit flips of the output is estimated. B. HSRAM Cell Design In order to reduce the dominant gate direct tunneling leakage, a popular method is to use high-κ gate dielectrics to substitute the traditional SiO2 , such as Si3 N4 (κ=7.5), T iO2 (κ=4-86) and BaSrT iO3 (κ=200), where κ means dielectric permittivity. However, the use of high-κ gate dielectrics result in gate dielectric thickness comparable to the device gate length. This means increased fringing fields from the gate to the souce/drain regions which will induce lowering of the potential barrier effect, named as Fringing/Field Indcued Barrier-Lowering effect (FIBL) [34] as shown in Figure 3. This effect causes increased Vth rolling-off, deteriorated subthreshold slope (S) and finally increased subthreshold leakage. Although gate leakage is one of the dominant components for sub100nm technologies, it will be negligible compared with subthreshold leakage after high-κ material applied. As a result, FIBL effect should be suppressed from the viewpoint of subthreshold leakage. Jointly biased gate and substrate Dynamic Threshold voltage MOS (DTMOMS) was proposed by Hu et al. [35] and its cross section and layout are shown in Figure 4. This kind of DTMOS can achieve high driving capability and low subthreshold leakage, because the threshold voltage drops under on state and increases under off state. In addition to these advantages, we find in our work that it can efficiently suppress FIBL effect caused by using high-κ gate dielectric, reduce the subthreshold leakakge, and increase the reliability of HSRAM cell constructed by the new device which is a hybrid of high-κ gate dielectric and jointly biased DTMOS.

541

Gate

Source

n+

Gate

Drain n−

n−

Source

p+

n+

n+

n+

Drain

High k gate Dielectric n−

n+

n

−

n+

P-type Substrate

Fig. 4. (a) Cross section of DTMOS with gate and substrate tied together and (b) layout of gate to substrate connection. WL

'0'

P-type Substrate

(b) Gate to Body Contact

(a) Cross Section of DTMOS

Fig. 6. Schematic cross sectional view of the HSRAM cell transistor. It uses high-κ gate dielectric and connects gate and substrate.

'0'

Vdd

0.60

0.65 BL

0.55

m5 n 0

m4 '1'

'0'

m1

n1

m6

m2

'1'

'1'

Fig. 5.

HSRAM cell design.

For the transistors in the HSRAM cell, the gate is connected to the substrate, thus the fringing fields from the gate to the source/drain are cancelled out by the field from the substrate. The direct benefit is the decreased Vth rolling off and reduced subthreshold leakage. As an inborn feature, the gate capacitance is also increased by the substrate capacitance and side capacitance between gate and source/drain. This results in increased node capacitance in the HSRAM cell and better reliability. The implementation of the novel HSRAM is shown in Figure 5. IV. E XPERIMENTAL R ESULTS We carried out experiments on HSRAM through two levels, i.e., transistor level and circuit level to demonstrate some advantages of the novel HSRAM. A. Transistor Level Experiment For the novel HSRAM cell, it is constructed by six special transistors which combine high-κ gate dielectric and dynamic threshold voltage by jointly biased gate and substrate. The following experiments will show that this special transistor not only achieves the advantages of high-κ and DTMOS, but also shows some novel features which can not obtained by either high-κ or DTMOS seperately, i.e., suppressed FIBL effect, improved subthreshold behavior, and enhanced resistance to SER. Experiments are performed with a two-dimensional (2D) device simulator ISE8.0 [36]. The simulated transistor structure is schematically shown in Figure 6. Here we use NMOS as a typical example. Same simulations can be carried out for PMOS. The doping concentrations for P-type substrate, source/drain region and LDD region are 8 × 1017 cm−3 , 1 × 1020 cm−3 and 1 × 1019 cm−3 , respectively. The effective channel length is 45nm. During the experiments, we fix the thickness of SiO2 for normal NMOS (without high-κ and dynamic threshold voltage), TSiO2 , and vary the dielectric permittivity k of high-κ gate dielectric from 3.9 to 200. Then the physical thickness, Tk , of the gate dielectric is calculated by Equation (9), where 3.9 represents the permittivity of SiO2 . Tk = k × TSiO2 /3.9 (9)

Potential Profile (Volts)

m3

Potential Profile (Volts)

BL

0.60

0.55

High-k

0.50 0.45 0.40

40.5mV

0.35

High-k + DT 0

5

15

20

25

30

35

40

45

Lateral Distance (nm)

0.50 k = 50 k = 3.9

0.45

0.40

10

0

5

10

16.8mV

15

20

25

30

35

40

45

Lateral Distance (nm)

Fig. 7. Potential distribution along the channel for high-κ+DT NMOS and high-κ NMOS.

the barrier potential between the source and the channel, as shown in Figure 7. In this case, the device is biased at off state with Vds = Vdd and Vgs = 0V . For high-κ NMOS at κ = 50, the barrier potential is lowered by 40.5mV as shown in the miniature; while it is lowered only by 16.8mV for hybrid (high-κ+DT) NMOS. Both of them are compared with conventional NMOS with SiO2 as gate dielectric. This reduced barrier potential lowering of hybrid NMOS definitely means less Vth rolling off. Figure 8 compares the Vth rolling off with increased κ between high-κ NMOS and hybrid NMOS. Here, we measure the ∆Vth as ∆Vth = Vth (@Vds = 0.1V ) − Vth (@Vds = Vdd ). This figure shows that the threshold voltage rolling off for hybrid NMOS is much less than high-κ NMOS. From Equation ( 2) we can see, this property facilitates the reduction of subthreshold leakage. It will be further demonstrated in the following circuit level experiments. For this novel hybrid transistor, there are three capacitances which are parallel connected to gate capacitance, Cg . They are two sidewall fringing capacitance, Cside , and Csub . For Cside , it associates with the electric field emerging from the gate region and ending at the source/drain regions. As a result, the total gate capacitance will be (Cg + 2Cside + Csub ). This enlarged gate capacitance compared with normal NMOS will benefit the resistant ability to SER for internal HSRAM cell nodes n0 and n1 . On the other hand, bigger gate capacitance means longer current charging time and slower cell read/write speed. However, this is compensated by the dynamic threshold property. Under on state, the gate and substrate are jointly biased at high voltage. Due to the body effect and FIBL effect, the threshold voltage is lowered and as a result the driving current is

130

High-k+DT MOS High-k MOS

120 110 ∆Vth (mV)

100

In order to reduce the gate direct tunneling leakage, the conventional SiO2 is replaced by a high-κ material as gate dielectric, for example, κ = 50 (Here, we use κ = 50 as a typical example. For other κ values, the basic observation is same.). For sub-100nm technologies, the thickness of high-κ gate dielectric is comparable to channel length. Specifically, it is about 9nm under 45nm technology node at κ = 50. This introduces serious FIBL effect, which lowers

90 80 70 60 50 40 0

30

60

90

120

150

180

210

K

Fig. 8. NMOS.

542

Vth rolling off with increased κ for hybrid NMOS and high-κ

Ratio:Hybrid NMOS / Normal NMOS

TABLE II R ELIABILITY DEGREE (RD) FOR DIFFERENT SRAM DESIGNS .

Total Gate Capacitance Driving Current

4.5 4.0 3.5

RD 6TSRAM κ6TSRAM κ = 7.8 κ6TSRAM κ = 50 HSRAM κ = 7.8 HSRAM κ = 50 DSRAM DRG SRAM

3.0

K=50

2.5 2.0 1.5 1.0

0→ 1 flip 21.55 21.62 21.83 21.74 22.05 4.84 8.78

Normal NMOS (SiO2 Gate)

TABLE III B ITLINE DELAY TIME FOR DIFFERENT SRAM DESIGNS .

0.5 0

30

60

90

120

150

180

210

K

Fig. 9. Ratios of driving current and total gate capacitance between hybrid NMOS and normal NMOS. TABLE I L EAKAGE POWER OF FIVE SRAM DESIGNS . Leakage Power (nWatt) 6TSRAM κ6TSRAM κ = 7.8 κ6TSRAM κ = 50 HSRAM κ = 7.8 HSRAM κ = 50 DSRAM DRG SRAM

1→ 0 flip 1.00 1.03 1.14 1.12 1.23 0.59 0.76

Sub 72.74 138.01 243.31 92.65 164.05 0.02 37.43

30o C Gate 1295.55 0.56 0.00 0.55 0.00 217.50 1295.55

Total 1368.29 138.565 243.31 93.20 164.05 217.52 1332.98

Sub 380.11 568.63 826.19 422.96 467.20 65.79 200.97

80o C Gate 1295.85 0.60 0.00 0.55 0.00 217.52 1295.85

Total 1675.96 569.23 826.19 423.51 467.20 283.53 1496.82

increased. Figure 9 shows the ratios of driving current and total gate capacitance between hybrid NMOS and normal NMOS with increased κ value. Both the ratios of driving current and gate capacitance increase with the increasing of κ value. For the ratio of driving current, its increase is very quick at the beginning, then tends to be slow down with much high κ values. While for the ratio of gate capacitance, its increase is almost linear. From the viewpoint of trading off SER and speed, the optimal value is around κ = 50 as shown by the dashed line in Figure 9. Before this point, κ = 50, the driving current goes up much more quickly than the gate capacitance, and more speed gain can be expected. After this point, the increase of gate capacitance is faster than that of driving current, and this means speed gain gradually diminishes and timing overhead will cancel out the SER benefit. In summer, κ = 50 is an optimal value and will be used in the following experiments. B. Circuit Level Experiment For the circuit level experiments, we custom designed, simulated and compared our novel HSRAM, standard 6T SRAM (6TSRAM), standard 6T SRAM with high-κ gate dielectric (κ6TSRAM), Drowsy SRAM (DSRAM) [9], [10], and DRG SRAM [14]. All the simulations were carried out using HSPICE with the 45nm Berkeley Predictive Technology Model [28] and ISE8.0 to get the gate leakage, subthreshold leakage affected by FIBL effect, Qcrititcal for SER and SRAM access time. The only difference between 6TSRAM and κ6TSRAM is the gate material. For the DSRAM, its supply voltage is fixed at Vdd = 0.3V . And the high Vth access transistors are realized by DELVTO option in HSPICE. For DRG SRAM, the HSPICE parameters of gated ground NMOS transistor are specially designed to make the comparison between different SRAM designs fairly. All the leakage values are computed under two temperatures, 30o C and 80o C. Here we define Reliability Degree (RD) to represent the soft error susceptibility of different SRAM designs compared with the 6TSRAM. And RD is expressed as Equation (10), where Qcritical 6T SRAM and Qcritical SRAM mean the critical charge values for 1 to 0 flip of 6TSRAM and any flips of other kinds of SRAMs. In order to measure the SRAM cell access time, we neglect the row/column address decoding, cell selection, and sense amplification and only take account of the bitline delay, which is defined as the time for the differential voltage between BL and BL to reach 100mV. And it is normalized by that of the 6TSRAM. RD =

Qcritical SRAM Qcritical 6T SRAM

(10)

SRAM Design 6TSRAM κ6TSRAM κ = 7.8 κ6TSRAM κ = 50 HSRAM κ = 7.8 HSRAM κ = 50 DSRAM DRG SRAM

Bitline Delay 1.00 0.77 0.63 0.58 0.27 3.81 1.47

Table I compares the leakage power of seven different SRAM designs under two temperatures, 30o C and 80o C. Compared with 6TSRAM, the gate leakage which is the dominant leakage component for 6TSRAM is reduced almost to zero by using highκ gate dielectric, as illustrated by κ6TSRAM and HSRAM with κ = 7.8/50. The introduction of high-κ gate dielectric causes the increase of subthreshold leakage power because of the FIBL effect, and the higher the κ value, the more increase the subthreshold leakage power. This deteriorated subthreshold behavior of κ6TSRAM is rectified by our novel HSRAM through jointly biasing the gate and substrate. HSRAM brings the subthreshold leakage power back to a considerable level compared with 6TSRAM, makes the gate leakage negligible and is superior than 6TSRAM and κ6TSRAM under different κ values, as shown in Table I. For DSRAM, both the subthreshold leakage power and the gate leakage power are greatly less than that of 6TSRAM. Two significant features contribute to this good property. One is it uses high Vth access transistors which make the bit line subthreshold leakage negligible. The second, which is more important, is that it uses smaller supply voltage at standby mode. From Equation (3) we can see, this reduction on Vdd will make an exponential reduction on gate leakage power. Although the DSRAM is a little better than HSRAM at high temperature (80o C) from the viewpoint of leakage, it uses many additional complementary circuits to realize the variable supply voltage. Table I also illustrates another important issue, i.e., temperature has a strong effect on subthreshold leakage, while little effect on gate leakage. This further demonstrates the necessity of using HSRAM to substitute κ6TSRAM. Because chips are becoming hotter with the scaling progress, which makes the FIBL effect of κ6TSRAM more severe in terms of subthreshold leakage increasing. Table II compares the reliability degree (RD) for 1 to 0 and 0 to 1 flips of different SRAM designs. HSRAM uses high-κ gate dielectric and jointly biases the gate and the substrate. These techniques increase the gate capacitance by Cside and Csub and in turn enhance the reliability of the HSRAM cell. As a result, the RD of 1 to 0 or 0 to 1 flip for HSRAM is higher than that of 6TSRAM and κ6TSRAM. The DSRAM cell is obviously more susceptible to soft errors as compared to the standard 6TSRAM due to its reduced supply voltage in the leakage control mode. For DRG SRAM cell, when it is shut off from the ground using the gated ground NMOS transistor, the virtual ground node does not stay at 0V and charges up to a higher voltage (0.3V). This property makes DRG SRAM cell more vulnerable to a 0 to 1 transition because a smaller induced charge is sufficient to trigger the flip. Table III shows bitline delay for seven SRAM designs. There are two important factors contributing to the reduction on the bitline delay for HSRAM cell. The first is the FIBL effect which lowers the Vth of transistors under on state. The second is the substrate biased at gate voltage which causes a significant body effect that lowers Vth

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greatly for transistors under on state. The lowering of Vth causes a quadratic increase in driving current of the access transistors which determine the bitline delay time. For DSRAM, the high Vth access transistors bring significant bitline delay overhead which is about 3 times longer than that of 6TSRAM. For discharging the bitlines, DRG SRAM uses three NMOS transistors which obviously slow down the discharging speed compared with two transistors in the current pass of 6TSRAM. V. C ONCLUSION In this paper, we presented a novel HSRAM design which combines high-κ gate dielectric and dynamic threshold voltage and exhibits some novel features that cannot be achieved by using these two techniques separately. Experiments were carried out through both transistor level and circuit level. In transistor level, immunity of HSRAM to FIBL effect and potential on leakage reduction are demonstrated. Optimal κ value is found by trading off the driving ability and node capacitance. In circuit level, comparisons from the viewpoint of total leakage, reliability and access time are done among standard 6TSRAM, high-κ 6TSRAM, HSRAM, Drowsy SRAM and DRG SRAM. All the comparisons prove that the goal of the HARM design is achieved. For scalability consideration of this HSRAM design, two important issues need to be paid attention. One is deep understanding of the body effect in SOI implementation and the other is how to realize the idea on double gate transistor. Future work will focus on the above two aspects and a micro-architectural level performance analysis based on the full realization of HSRAM logics including the address decoding logic and sense amplifier logic. R EFERENCES [1] “International technology roadmap for semiconductors 2003 editioin executive summary.” [Online]. Available: http://public.itrs.net [2] S. Mukhopadhyay and K. Roy, “Modeling and Estimation of Total Leakage Current in Nano-Scaled CMOS Devices Considering the Effect of Parameter Variation,” in Proc. Int. Symp. Low Power Electronics and Design, 2003, pp. 25–27. [3] D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, “Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage,” in Proc. Design Automation Conf., June 2003, pp. 175 – 180. [4] D. Lee, H. Deogun, D. Blaauw, and D. Sylvester, “Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization,” in Proc. Design & Test Europe Conf., Mar. 2004. [5] R. Guindi and F. N. Najm, “Design Techniques for Gate-Leakage Reduction in CMOS Circuits,” in Proc. Int. Conf. Quality Electronic Design, Mar. 2003, pp. 61–65. [6] C. H. Kim, J. J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-biased-low-leakage SRAM Cache: Device and Architecture Considerations,” in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003, pp. 6–9. [7] N. Seifert, D. Moyer, N. Leland, and R. Hokinson, “Historical Trend in Alpha-particle Induced Soft Error Rates of the AlphaTM Microprocessor,” in Proc. IEEE Int. Symp. Reliability Physics, May 2001, pp. 259–265. [8] N. Seifert, et al., “Frequency Dependence of Soft Error Rates for Sub-micron CMOS Technologies,” in International Electron Devices Meeting, Technical Digest, Dec. 2001, pp. 14.4.1 –14.4.4. [9] N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, “Drowsy Instruction Caches,” in Proc. IEEE/ACM Int. Symp. Microarchitecture, Nov. 2002, pp. 219–230. [10] K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy Caches: Simple Techniques for Reducing Leakage Power,” in Proc. Int. Symp. Computer Architecture, May 2002, pp. 148–157. [11] M. Powell, S. H. Yang, B. Falsafi, and K. R. adn T. N. Vijaykumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deepsubmicron Cache Memories,” in Proc. Int. Symp. Low Power Electronics and Design, July 2000, pp. 90–95. [12] S. H. Yang, M. D. Powell, B. Falsafi, K. Roy, and T. N. Vijaykumar, “An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-submicron High-performance I-caches,” in Proc. Int. Symp. HighPerformance Computer Architecture, Jan. 2001, pp. 147–157. [13] S. Kaxiras, Z. Hu, and M. Martonosi, “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power,” in Proc. Int. Symp. Computer Architecture, July 2001, pp. 240–251.

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