Logic Analyzer

Logic Analyzer

INTRODUCTION TO THE DIGITAL DOMAIN The advent of digital circuits dramatically changed the concerns of engineers and technicians working with electronic circuits. Ignoring for a moment digital signal quality or signal integrity, the issues switched from the world of bias points and frequency response to the world of logic ones, zeroes, and logic states (see Fig. 1 a ). This world has been called the "data domain." Using off-the-shelf components virtually guarantees correct values of voltage and current if clocks are kept to moderate speeds (less than 50 MHz) and fanin/fan-out rules are observed. The objective for circuit verification and test focuses on questions of proper function and timing. While parametric considerations are simplified, there is a tremendous increase in functional complexity and the sheer number of circuit nodes. Measurements to address these questions and to manage the increased complexity are the fort of the “ Logic analyzer.” Logic analyzers collect and display information in the format and languages of digital circuits. Microprocessors and microcontrollers are the most common logicstate machines. Software, written in the unique form of a microprocessor's instruction set, provides the direction for these handy state machines. Most logic, analyzers can he configured to format their output as a sequence of microprocessor instructions. This makes them useful for debugging software. For real-lime or time-critical embedded controllers, a logic analyzer is an excellent tool to both trace program flow and measure event timing.

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Logic Analyzer

Because logic analyzers do not affect the behavior of processors, they are excellent tools for system performance analysis and verification of real-time interactions. Data stream analysis is also an excellent application for logic analyzers. A stream of data from a digital signal processor or digital communications channel can be easily captured, analyzed, or uploaded to a computer.

BASIC OPERATION In order to understand how logic analyzers work, it is helpful to differentiate between two modes of operation: asynchronous timing mode and synchronous state mode. Clock Data 0 Data 1 Gate_clk Fig. 1(a) Logic timing diagram. Logic value versus time is shown for four signals

Fig1(b) Logic state diagram. Input I &S control transitions from state to state. O & E are output set to new values upon entry to each state. Govt..Poly., Washim

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Logic Analyzer

a) Asynchronous Mode On screen, the asynchronous mode looks very much like an oscilloscope display. Waveforms are shown, but in contrast to an oscilloscope’s two or four channels, there are a large number of channels : eight to over a hundred. The signals being probed are recorded either as a “one” or a “ Zero”. Voltage variation other than being above or below the specified logic threshold is ignored, just as the physical logic elements would do. Figure 2 a compares an analog waveform with its digital equivalent. A logical view signal timing is captured. As with an oscilloscope, the logic analyzer in timing mode provides the time base that determines when data values are clocked into instrument storage. This time base is refereed to as the “internal clock.” A sample logic analyzer display showing waveforms captured in timing mode is shown in Fig. 2 b.

Volts versus time

Threshold

Logic value versus time 0

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Logic Analyzer

Fig. 2 (a) Analog versus digital representations of a signal. b) Synchronous Mode The synchronous state mode samples signal values into memory on a clock edge supplied by the system under lest. This signal is referred to as the "external clock." Just is a flipflop takes on data values only when it is clocked, the logic analyzer samples new data values or stales only when directed by the clock signal. Groupings of these signals can represent state variables. The logic analyzer display shows the progression of states represented by these variables. A sample logic analyzer display showing a trace listing of a microprocessors bus cycles (state mode) is shown in Fig. 3. c) Block Diagram An understanding of how logic analyzers work can be gotten from the block diagram in Fig. 4. Logic analyzers have six key functions: the probes, highspeed memory, the trigger block, the clock generator, the storage qualifier, and the user interface. 1. Probes. The first function block is the probes. The function of the probes is to make physical connection with the target circuit under test. To maintain proper operation of the target circuit, it is vital that the probes not unduly load down the logic signal of interest or disturb its timing. It is common for these probes to operate as voltage dividers. By dividing down the input signal, voltage comparators in the probe function are presented with the lowest possible voltage slew rate. Higher-speed signals can be captured with this approach. The voltage comparators transfer form the input signals into logic values. Different logic families, i.e., TTL, ECL, or CMOS have different voltage threshold, so the comparators must have adjustable thresholds. Govt..Poly., Washim

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Logic Analyzer

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Logic Analyzer

2. High-Speed Memory: The second function is high-speed memory, which stores the sampled logic values. The memory address for a given sample is supplied internally. Typical memory depth is 4096 or 4K sampies. Seine analyzers can store several megasamples. Usually the analyzer user is interested in observing the logic signals around some event. This event is called the "measurement trigger." It will be described in the next functional block. Samples have a timing or sequence relationship with the trigger event but are arbitrarily placed in samples memory depending on the instantaneous value of the internally supplied address. The memory appears to the user as a continuously looping storage system. 3. Trigger Block. The third functional block is the trigger block. Trigger events are a use tied pattern of logical ones and zeroes on selected input signals. Figure 5. shows how a sample trigger pattern corresponds with timing and state data streams. Some form of logic comparators is used to recognize the pattern of interest. Once the trigger event occurs, the storage memory continues to store a selected number of posttrigger samples. Once the posttriger store is complete, the measurement is stopped. Because the storage memory operates as a loop, samples before the trigger event are captured, representing time before the event. Sometimes this pretrigger capture is referred to as "negative time capture." When searching for the causes of a malfunctioning logic circuit, the ability to view events leading up to the problem, i.e., the trigger event, makes the logic analyzer extremely useful.

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Logic Analyzer

100/500MH - LAC

Marker off

Listing

Print

Run

Acquisition Time 23 Apr 1993 22:13:05

Label

ADDP

Base

Hex

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Invasm

FCE05 FCE06 FCE07 FCE08 FCE09 FCE0A FCE0B FCE0C 00138 00139 FCEOD FCEOE FCEOF FCE10 FCE11

8088 Mnemonic

STAT

hex

Symbol

MDV BX, #0138 38 code fetch 01 code fetch MOV [BX],NO410 07 code fetch 10 code fetch 04 code fetch INC BX 10 memory write 04 memory write INC BX MDV [BX],CS OF code fetch MDV AX,# 0040 40 code fetch

CODE FETCH CODE FETCH CODE FETCH CODE FETCH CODE FETCH CODE FETCH CODE FETCH CODE FETCH MEMORY WRIT MEMORY WRIT CODE FETCH CODE FETCH CODE FETCH CODE FETCH CODE FETCH

Fig. 3: State mode display. Listing shows inverse assembly of microprocessor bus cycles.

Fig. 4 : Logic analyzer block diagram Govt..Poly., Washim

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Logic Analyzer

Trigger

S1 S2 S3 Timing Mode

S1

S2

S3

0

0

1

0

1

1

1

1

0

1

0

0

1

0

1

1

1

1

0

1

0

Trigger

Fig 5 Example of trigger pattern showing match found with timing mode data & then state mode data. Trigger pattern is “ 1 0 1 ” for input signals S1, S2 and S3.

4. Clock Generator. The fourth bock is the clock generator. Depending on which of two operating modes is selected, state or timing, sample clocks are either user supplied or instrument supplied. In the state mode, the analyzer clocks in a sample based on a rising or falling pulse edge of an input signal. The clock generator function increases the usability of the instrument by forming a clock from several input signals. It forms the clocking signal by “OR” ing or “AND” ing input signals together. The user could create a composite clock using logic elements in the circuit under test but it is usually more convenient to let the analyzer's clock generator function do it. Govt..Poly., Washim

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Logic Analyzer

In timing mode, two different approaches are used to generate the sample clock. Some instrument offer both approaches, so understanding the two methods will help you to get more from the instrument. The first approach, or "continuous storage mode." simply generates a sample clock at the selected rate. Regardless of the activity occurring on the input signals, the logic values at the time of the internal clock are put into memory (see Fig. 6). Sample clock Signal Sample Value

0

1

1

1

1

0

0

1

1

0

0

0

Memory location 0

1

2

3

4

5

6

7

8

9

10

11

Fig. 6 : Continuous storage mode. Sample value is captured at each sample clock and stored in memory.

The second approach is called “transitional timing mode” the input signals are again sampled at a selected rate. The clock generator function only clocks the input signal values into memory if one or more signals change their value. Measurements use memory more efficiently because storage locations are used only if inputs change. For each sample, a time stamp is recorded. Additional memory is required to store the time stump. The advantage of this approach over continuous storage is that long time records of infrequent activity or bursts of finely timed events can be recorded (see Fig. 7).

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Logic Analyzer

5. Storage Qualifier. The fifth function is the storage qualifier. It also has a role in determining which data samples are clocked into memory. As samples are clocked, either externally or internally the storage qualifier function looks at the sampled data and tests them against a criterion. Like the trigger event, the qualifying criterion is usually a one-zero pattern of the incoming signal. If the criterion is met, then the clocked sample is stored in memory. If the circuit under test is a microprocessor bus, this function can be used to separate bus cycles to a specific input/out-put (I/O) port from instruction cycles or cycles to all other ports. 6. User Interface. The sixth function, the user interface, allows the user to set up and observe the outcome of measurements. Benchtop analyzers typically use a dedicated keyboard and cathode-ray tube (CRT) display. Many products use graphic user interfaces similar to those available on personal computers. Pull-down menus, dialog boxes, touch screens, and mouse pointing device", are available. Logic analyzers are used sporadically in the debug process, so careful attention to a user interface that is easy to learn and use is advised when purchasing. Not all users operate the instrument from the built-in keyboard and screen. Some may operate from a personal computer or workstation. In this case, the "user interface" would be the remote interface: RS-232, IEEE-488, or local area network (LAN).

Time

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

Sample clock

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Logic Analyzer

Signal Sample Stored time 0 Value T0 Memory location 0

1 T1

0 T5

1 T7

0 T9

1

2

3

4

Fig. 7 : Transitional storage mode. The input signal is captured at each sample clock but is stored into memory only when the data changes. A time value is stored at each change so that the waveform can be reconstructed properly.

INSTRUMENT SPECIFICATIONS / KEY FEATURES Key parametric specifications include maximum sample rate for both internal and external clocks, setup and hold or capture aperture, and probe loading. Key functional specifications include the number of channels, memory depth, the number of trigger resources, the availability of preprocessors and inverse assemblers, nonvolatile storage, and time stamps, and correlation between measurement modules. Data and control interfaces for IEEE-488 and RS-232 have been important in manufacturing applications of logic analyzers. Local area network interfaces have emerged as critical links in research and development (R&D) to tie these instruments with project databases. I) Sample Rate Sample rate determines the minimum time interval, which can be resolved and measured in timing mode. The relationship of the sample clock to an input signal transition is completely random. The transition may occur just after a preceding

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Logic Analyzer

clock edge, or it may have happened just before the clock that did capture it. This is shown graphically in Fig. 8. The uncertainty of placing a signal transition is a full sample period. Two edges of the same signal can be measured to an accuracy of two sample periods. Measuring a transition on one signal versus a transition on another signal can be done to an accuracy of two sample periods plus whatever skew exists between the channels. "Channel skew" is the difference in path delay between two channels of the analyzer. Channel skew is usually specified by the analyzer vendor and will typically be one-half the minimum sample period. Sample clock Captured data Actual signal Edge just Edge just Clock and actual data after clock ? before clock have asynchronous or random relationship.

Just after

Just before

One sample Uncertainty Fig 8 : Time interval uncertainty of the timing mode. The analyzer’s captured data represent the actual signal only at the time of the sample clock. The actual signal as shown could have gone high almost a full sample period before it was recorded as high. The same uncertainty exists when the signal goes low; it could have gone low almost a full sample period before it was recorded.

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Logic Analyzer

For state measurements, sample rate determines -the maximum clock rate, which can be measured in the target state machine. The required sample rate for microprocessor buses is usually one-half or one-third the processor's clock. For the processor in Fig. 9 a, bus cycles take up four processor clocks. Figure 9 b. shows a more sophisticated processor, which uses two clocks for most bus cycles but can

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Logic Analyzer

operate with only one clock in a burst mode. These processors and certain reduced instruction set computer (RISC) processors require state sample rates equal to the processor's clock. Careful thought to the maximum bus rate, not the processor clock rate, should be given when determining the need for maximum state sample rate. II) Setup and Hold Closely related stale sample rate are the setup and hold time specifications for the analyzer. Some analyzers have a selectable "capture aperture." Both specifications refer to the time interval relative to a clock edge when the data must be stable for accurate capture. With any synchronous logic circuit, the occurrence of a clock causes the output of a flipflop or register to transition to its next state value. The transition must be complete and stable a specified time before the next clock. Likewise, the inputs to the flipflop must be held for a specified time after the clock. A similar situation exists for microprocessor buses. The output of memories changes as the next address is presented. The memory data must be stable before they are sampled by the processor and held after the clock the required amount. Like flipflops, registers, and memory elements, a logic analyzer also needs stable data a specified time before the external sample clock. This is the "setup time specification." The "hold specification" likewise must be met, but it is typically zero time. For setup time. a number of vendor attitudes are represented in setup specifications. From the perspective of the instrument user, the analyzer should have the same characteristics as the user's circuit. At high clock rates, a very short setup time is difficult for vendors to achieve. It is common for the setup time to be in the range of

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Logic Analyzer

one-half to one-third the clock period at maximum sample rate. Users planning on using the analyzer at its maximum state speed should check this specification to be sure their circuit will present acceptable setup times. Some analyzers have a selectable aperture in which the state data are sampled. This can be an extremely useful feature for checking or characterizing the target system's own setup and hold margins. III) Probe Loading The last parametric specification is "probe loading." Logic analyzer probe

usually come specified with static resistive and capacitive loading values.

Obviously, the target system should not be perturbed by probe loading. However, the effects of these static loads cannot be interpreted for logic analyzers as easily as they might be for an oscilloscope. Logic analyzers are sensitive to edge placement, so signal rise time and delay are more important than pulse response. Latitude can be taken in optimizing the probe-comparator network. Most popular analyzers sampling at 500 MHz and below have probe specifications of 100 kΩ and 0 to 8 pF. In series with this shunt reactance is a 250- to 500-Ω resistance (see Fig. 10). The capacitance is largely isolated from the target system by this series resistance. Thus the difference between 5and 10 pF is relatively unimportant. The nominal dc loading is 100 kΩ, and even high frequencies never see a reactance less than 250 Ω.

250-500Ω To target circuit

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To probe comparators

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Logic Analyzer

6-8 pF

100kΩ.

Fig. 10: Equivalent circuit for logic analyzer probe.

Analyzers having greater than a 1-GHz sample rate have started supplying SPICE models for their probes so that the true impact on signal integrity can be evaluated. IV) Channel Count The key functional specification is "channel count." The number of input channels, along with maximum sample rate. drives the cost of a logic analyzer. Selecting the appropriate number of channels for a current project as well as future needs is very important. The use model for debugging a problem in timing mode often involves an incremental hunt and probe approach. A minimum count of 32 channels is recommended. Thirty-two channels n also the minimum for probing an 8-bit microprocessor: 16 channels for addresses, 8 channels for data and about 8 channels for status and random circuit points. For 16 –bit processors the, minimum is closer to 56 channels: 24 for addresses, 16 for data and 16 for Status and random probes. For 32-bit processors, the number is 80 channels: 32 for addresses, 32 for data, and 16 for status. For analyzers, which can be configured to operate as two simultaneous machines, e.g., one as a state analyzer and the other as a timing analyzer, 8 to 32 channels should be added to the preceding recommendations.

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Logic Analyzer

V) Memory Depth/Maximum Samples Memory depth is directly related to the maximum time window captured in timing mode or the total number of states or bus cycles captured in state mode. Often depth is traded against sample - rate, channel count, or the availability of instrument resources such as time stamps for state samples. Memory can sometimes be cascaded or interleaved for more depth, but at the expense of channels or time stamps. The high cost of memory components makes it uneconomical to record directly into logic analyzer memory at 100 MHz to 2 GHz. The data are usually decorated or fanned out to multiple banks of memory. Memory banks can be interleaved together to achieve maximum sample rates. This also provides "double depth" memory. If the interleaving is switched off, the sample rate must drop along with a decrease in memory depth. The remaining memory can be used to create additional channels. As a general rule more memory depth is better. Most analyzer, provide from 4096 to 1 million samples. Capturing a packet of data such as a single scan line from a television or computer" monitor may require a certain analyzer depth. A common measurement is to trace a processor "crash.". A crash occurs when a processor fetches an instruction stream, which directs it to a portion of memory that has not been loaded with a valid program. In each a case, the processor will fetch an invalid instruction or one intended to literally stop the processor's execution. Once the crash is detected, deep memory can be searched backward to the root cause of the crash. A third purpose of deep memory is to trace software written in a high-level programming

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Logic Analyzer

language. Ten or more bus cycles may be needed to capture a single high-level instruction. A useful snapshot will require the capture of a couple of hundred high-level instructions, meaning several thousand bus samples. The down side of deep memory is a sluggish user interface and the potential waste of time while wading through thousands of samples. Transitional storage mode for timing measurements is an excellent feature to optimize memory needs. Samples are only stored when input signals change values. High-resolution pictures over wide time windows can be captured. The tradeoff here is the maximum sample rate and richness of trigger features, which can be achieved in this mode relative to the simpler continuous storage mode. VI) Trigger Resources The key to finding obscure or subtle problems is in the number and sophistication of trigger resources. Most important are the number of patterns and some number of sequencer levels. "Sequence levels" refer to the number of states that the trigger block can be programmed to step through while finding the trigger event or while finding the trigger event or while controlling storage qualification. For example, a three-level sequencer could be set to first find pattern 1 and then find pattern 2 before finally finding pattern 3 and triggering. Studies have been done on the usefulness of multiple sequence levels, It is rare to find a measurement needing more than three sequence levels. Even two levels are used infrequently.

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Logic Analyzer

It is common for instruments, except the highest-sample-rate machines, to offer 8 to 16 simultaneous patterns and a like number of sequence levels. From a user-interface perspective, 20 or 30 patterns can sometimes be defined and kept ready for a measurement. The instrument hardware is usually more limited than that allowing less than 16 simultaneous patterns. Usually there is a counter associated with each level of the sequencer. Range patterns are expensive to implement. Unless the analyzer has been specifically designed for software tracing,-there will usually only be one or two range patterns. Rich trigger capabilities can be more effective than capturing a long record with deep memory and then having to wade through all the data. VII) Preprocessors/Inverse Assemblers A key benefit to using a logic analyzer is looking at many channels of data simultaneously. Hooking up all these channels is the number one barrier to using a logic analyzer. Prewired probes called “preprocessors”are an effective way to overcome this barrier. They are available for many microprocessors and standard buses ,such as the personal computer extended industry standard architecture (EISA) bus and the serial bus RS-232. Many package types like dual-in-line (DIP), pin-grid array (PGA), and leadless carriers are available. Purchasing a preprocessor is well worth the money. Not all vendors support all processors nor all their package variants, so careful attention should be paid to this limitation when selecting an analyzer vendor. Close companions to preprocessors are irrerse assembler software packages. They run on the logic analyzer to format the captured data as processor

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Logic Analyzer

instructions. This greatly enhances the readability of displays and usefulness of Ate instrument. Early microprocessors had their execution units tied directly to their bus interface.

The

correlation

of

bus

activity

with

instruction

execution

was

straightforward. Today, processors employ pipelining, caching, and memory address translation. These methods cause a poor correlation between bus activity (which is what a logic analyzer observes) and instruction execution. Preprocessors for these chips incorporate special hardware, and their inverse assemblers use sophisticated techniques to overcome these problems as best they can. Preprocessors and inverse assemblers have become matched sets. There is a wide disparity of function among vendors on the quality of inverse assembler displays. VIII) Nonvolatile Storage Instrument setup involves channel selection and creation of data labels and trigger specs. The ability to save these setups along with measurement data in nonvolatile storage is critical to productivity. Flash memory and disk drives are the two most common options available. Closely related to setup is the documentation of setups and measurement results. Connection of the analyzer to a printer or plotter is a good way to output this information, but transfer of the data to a personal computer via a compatible disk drive is quickly becoming the preferable route. In this case, popular documentation packages, database programs, or spreadsheets can use the information

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Logic Analyzer

directly. In addition to the media compatibility between PC and instrument, the data format compatibility with word processors or graphics packages must be considered. IX) Time Stamps When operating in state mode, the timing of clocks is determined by the circuit under test. Sometimes the clocking is sporadic, or store qualification is engaged, which obliterates any implied timing from a regularly paced state clock. The ability of a logic analyzer to store a time value along with the captured data can be very useful. The stored time value is called a "time stamp." The time stamp is especially useful with an instrument split into state and timing machines. It enables the user to correlate the state and timing measurements. Modular instruments that can host multiple logic analyzers or other measurement modules such as pattern generators or oscilloscopes sometimes are able to time stamp and correlate events from each of the modules.

GETTING THE MOST FROM LOGIC ANALYZER The attributes of a logic analyzer, which make it useful—logic domain data capture and presentation, large channel count, and flexibility of measurement—also can make the instrument intimidating. The recommendations, which follow, should help you overcome whatever fears keep you from getting the most from your logic analyzer. The most common task when troubleshooting a logic signal is the incremental "hunt and probe" session. Many people use oscilloscopes for this procedure, but logic analyzers can be substantially more productive. In a "hunt and

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Logic Analyzer

probe" session, a symptom is identified by probing a single channel. Looking upstream, the probe is moved or more probes are added. Specific events, usually Boolean combinations of signals, are used to isolate events. If the target system is a microprocessor, the symptom is often see as state behavior or software behavior. A) Recommendations to Improve Usability 1. Plan the use of input channels. Multibit uses such as address, data, and status should all be assigned to adjacent channels. Hold out some channels on a free pod for “hunt and probe” timing measurements. First choice is for these channels to be the default setup. When the instrument is first turned on, check to see what the default channel assignment is. Usually the instrument will default to a timing mode measurement. Identify which pod (probably it will be pod 1) contains the selected channels. As you move these exploratory channels along, you may find that you've probed a multibit bus. You may want to add this signal and its companions to your suite of input channels. If you took the time to plan ahead, you'll have already reserved channels for all the other bits. If a split timing and state measurement looks promising, it will be easy to incrementally set up the machine, since usable pod configurations will have been reserved. 2. Use preprocessors or specially designed, package clips to mass connect the probes. Little value is added by the user to hook up all these lines. And the frustration can be overwhelming when general-purpose clips fall off. Preprocessors usually come with preconfigured setup including labels and symbols. And they come with inverse

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Logic Analyzer

assemblers or data formatters so that information can be presented in standard mnemonics. 3. Physically label the probes if the flying-lead probes arc used. Most people just a keep track mentally of four to a hundred probe lines. 4. Take the time to create labels and multibit symbols. After the potential for a probing snarl, the next opportunity for contusion will be when making sense of the display. Labels and symbols keep the instrument tracking your thought process and avoid mistakes of interpretation. 5. Store setups, labels, and symbols on your storage. Store your "hunt and probe" setup well as snapshots of your incremental measurement, especially complicated triggers or split machine configurations. These stored setups and measurements will allow you almost single button recall of your thoughts during the troubleshooting process 6. Invest in hardcopy output for your analyzer, and use it. Manual notes and sketches of waveforms or trace listings are unnecessary and time consuming. Directly output to a printer or use a LAN connection to transfer machine-readable data to your PC or workstation. 7. Learn how to set triggers or store qualify data beyond a simple single pattern. Most users never get beyond the simple single pattern. Understanding concepts such as sequencing and special trigger events such as edges, etc., will stick even if the specific setup of a specific analyzer fades from your memory. It has been said that no one ever got rich by being a logic analyzer guru. That's true, hut people do get paid for solving

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Logic Analyzer

tough problems in the shortest possible time. The trigger controls are the key to achieving this. 8. Invest in an instrument with a point and shoot user interface. Usually this means a touch screen or a mouse pointer. Keyboards for entering labels and symbols will enhance usability. The flexibility of these instruments means that many potential choices need to be made. Directly pointing to these choices instead of moving incrementally to them with arrow keys will greatly speed things up.

CONCLUSION In this way we conclude that logic analyzer is advanced, most efficient and effective equipment which has many application in educational as well an industrial field.

REFERENCE Govt..Poly., Washim

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Logic Analyzer

1. ELECTRONIC INSTRUMENT HANDBOOK ( Second Edition) CLYDE. F. COOMBS, Jr. Chapter 31 : By David B. Richey 2. TLA 700 LOGIC ANALYZER USER MANUAL 3. TLA 700 LOGIC ANALYZER INSTALLATION MANUAL.

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