Lecture 6
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COSC 243 Computer Architecture And Operating Systems
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
1
Overview • This Lecture – Memory and Storage Systems – Source: Chapters 4, 5.1, 6 – Reading assignment • Section 5.1: Semiconductor Main Memory • Chapter 6: External Memory – Read magnetic disk section (6.1) in detail – Understand general concepts of RAID section (6.2) – Read Optical memory section (6.3)
• Next Lecture – Input/Output COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
2
Memory Hierarchy
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
3
Memory Hierarchy (cont) • Registers – 8-64 typical
• Cache – 2K-512K typical – Level 1 and Level 2
• Main memory – 512MB - 4GB
• Secondary storage Disk, . . . COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
4
Memory Hierarchy (cont) • Tradeoffs – Shorter access time -> Greater cost per bit – Greater capacity -> Smaller cost per bit – Greater capacity -> Longer access time
• Going down the hierarchy diagram – – – –
Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access by CPU
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
5
Secondary Storage • External to the CPU • Access via a bus • Bus examples – IDE – EIDE – USB – Firewire – ATA, SATA COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
6
Secondary Storage (cont) • Secondary storage examples – Disk – USB drive – Memory cards (cameras, etc) – Tape – CD-ROM – DVD
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
7
Magnetic Disk
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
8
Magnetic Disk (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
9
Magnetic Disk (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
10
Characteristics of Magnetic Disk • • • • • •
Number of platters Single vs. two sided Number of tracks Number of sectors per track Number of bytes per sector Cylinders
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
11
Speed Characteristics of Magnetic Disk • • • • •
Seek time Rotational latency Access time Block transfer time Which is longest?
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
12
RAID • Redundant Array of Inexpensive (Independent) Disks • A set of disk drives is viewed by the OS as a single logical drive • Data is distributed across drives • Parallelism • Redundant disk capacity used to store additional bits for reliability COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
13
RAID (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
14
RAID (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
15
CD-ROM
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
16
Other Media • • • • •
Writable versions of CD DVD Writable versions of DVD Tapes Memory cards (cameras, etc)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
17
Primary Storage • • • • • • •
Often called main memory Unique address for each location n address bits can address 2n locations Access one word at a time Basic operations are read and write Storage cells exhibit two stable states: 0, 1 Can be written into (at least once) to set the state • Can be read to sense the state COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
18
Operation of Memory • Example (assuming 8 bit address and data sizes)
Read
Address
Write
Memory
Data bus
Basic Memory Structure
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
19
Operation of Memory (cont) • Read – Load the address register with 175 – Set the read control signal – Some time later, the contents of word 175, 38 in this example, will be on the data output lines of the memory
• Write – Load the address register with 175 – Load the data buffer register with the new contents of word 175 – Set the write control signal – Some time later, the contents of word 175 will have the new value. COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
20
Properties of Main Memory • Random access (RAM) – Same access time to access any memory location – Contrast to tapes and disks – Synonymous with read-write memory
• Cycle time – Minimum time required between two successive read or write operations – Physical property of the memory COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
21
Properties of Main Memory (cont) • Access time – Delay between the start and finish of a memory operation - usually measured in nanoseconds (10-9) or picoseconds (10-12)
• Volatility – Semiconductor RAM memories lose data when power is removed. – Disks and tape retain data for years – Some memories have battery backup COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
22
Properties of Main Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
23
Static vs. Dynamic Memory • Static – No action is required to maintain a stored value
• Dynamic – – – –
Value stored as a charge on a capacitor Gradually disappears Must be recharged continually (refreshed) Read operation is destructive so special circuitry is included to rewrite the contents after a read – 1-2 millisecond refresh interval – Refresh by dummy reads when not in use COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
24
Static vs. Dynamic Memory (cont) • Comparison – Dynamic cells are smaller (1/4) than static – Dynamic is cheaper – Dynamic requires less chips
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
25
Types of Memory
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
26
A Typical Static RAM • • • • • •
Convenient for small memories 2048 (211) words of memory 11 address lines Each word is 8 bits wide 8 data lines 2 control signals
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
27
A Typical EPROM • Similar to a static RAM • Erasable by exposure to ultraviolet light of the correct wavelength
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
28
A Typical Dynamic RAM
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
29
A Typical Dynamic RAM (cont) • 4M x 4 • 22 address bits normally required • Only 11 pins available owing to technological limitations on the number of pins • 22 bits are multiplexed on the eleven pins • Organised as 2048 x 2048 array (4,194,305) which are addressed separately by row and column (RAS and CAS) • 4 bits of data in each location • Refresh by cycling through all rows of memory with RAS low and CAS high COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
30
Other Memory Issues • Simultaneous multiple word access • Parity • ECC
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
31
Cache Memory • Memory is slow compared to the time required to execute instructions. • Memory becomes more expensive as it gets faster • Compromise – Place a small amount of very high speed memory to temporarily hold a portion of the memory being accessed. COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
32
Cache Memory (cont) • If the addressed location is in cache, it is used. Otherwise a block of memory is transferred from memory to cache. • Principle of locality
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
33
Cache Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
34
Cache Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
35
Cache Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
36
Cache Memory (cont) • Performance is measured by hit ratio • Typical hit ratios are 0.9 - 1.0 • Update of main memory – Write through - write memory when cache is updated – Write behind (back) - a flag (valid bit) indicates cache location was changed. Write memory when cache must be reused. COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
37
Cache Examples • Main memory is 16 MBytes – 24 bit address – Byte addressable
• Memory block is 4 bytes • Memory is 4M blocks of 4 bytes each • Cache can hold 64 KBytes • Cache is 16K lines of 4 bytes each COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
38
Cache Mapping • Direct mapping cache • Associative cache • Set Associative cache
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
39
Direct Mapping Cache • Least expensive form • Maps each block of main memory into only one possible line of cache Cache Line 0 1 2 . . . m-1
COSC 243 (Computer Architecture)
Main memory blocks assigned 0, m, 2m, . . ., 2s-m 1, m+1, 2m+1, . . ., 2s-m+1 2, m+2, 2m+2, . . ., 2s-m-2
m-1, 2m-1, . . ., 2s-1
Lecture 6 - Memory and Storage Systems
40
Direct Mapping Cache (cont) i = j modulo m where i = cache line number m = number of lines in the cache j = main memory block number
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
41
Direct Mapping Cache (cont) • Split the full address into tag, line, and word fields • Address the cache with the line • Check that the tag in cache matches tag field of address
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
42
Direct Mapping Cache (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
43
Direct Mapping Cache (cont) • w=2 – (4 words in each cache line)
• s = 22 • r = 14 – (16K lines of cache)
• s-r = 8
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
44
Associative Cache • Most expensive form • No fixed mapping between main memory and cache lines • Split the full address into tag and word fields • Comparison between the required address tag and all stored tags is done simultaneously COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
45
Associative Cache (cont) • Cache replacement is typically round robin, FIFO(first in first out), or LRU (least recently used) • w=2 • s = 22
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
46
Associative Cache (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
47
Set Associative Cache • Cost compromise • Cache is split into v sets of k lines • number of lines in cache = v * k i = j modulo v where i = cache set number j = main memory block number v = number of sets in the cache
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
48
Set Associative Cache (cont) • A main memory block Bj can be mapped into any of the lines of set i • Several main memory blocks map to the same set, but can be put into any of the lines of the set • Split the full address into tag, set, and word fields • Common values of k (number of lines in a set) are 2, 4 COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
49
Set Associative Cache (cont) s+w
Tag
Memory Address Tag
Set
Word
d
w
s-d
Cache
Main Memory
Data
B0 Set 0
B1 B2
Set 1 X
X
Bj s+w
Compare
(hit in cache)
(miss in cache)
Two-way set associative cache organisation
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
50
Set Associative Cache (cont) • w=2 – (4 words in each cache line)
• s = 22 • d = 13 – (1 less than before since there are one-half as many sets as the 16 K lines of cache)
• s-d = 9 COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
51
Cache Replacement Algorithms • LRU – least recently used
• FIFO – first in first out
• LFU – least frequently used
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
52
Other Cache Issues • Single vs. 2-level cache • Unified vs. split cache
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
53
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
1
Overview • This Lecture – Memory and Storage Systems – Source: Chapters 4, 5.1, 6 – Reading assignment • Section 5.1: Semiconductor Main Memory • Chapter 6: External Memory – Read magnetic disk section (6.1) in detail – Understand general concepts of RAID section (6.2) – Read Optical memory section (6.3)
• Next Lecture – Input/Output COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
2
Memory Hierarchy
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
3
Memory Hierarchy (cont) • Registers – 8-64 typical
• Cache – 2K-512K typical – Level 1 and Level 2
• Main memory – 512MB - 4GB
• Secondary storage Disk, . . . COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
4
Memory Hierarchy (cont) • Tradeoffs – Shorter access time -> Greater cost per bit – Greater capacity -> Smaller cost per bit – Greater capacity -> Longer access time
• Going down the hierarchy diagram – – – –
Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access by CPU
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
5
Secondary Storage • External to the CPU • Access via a bus • Bus examples – IDE – EIDE – USB – Firewire – ATA, SATA COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
6
Secondary Storage (cont) • Secondary storage examples – Disk – USB drive – Memory cards (cameras, etc) – Tape – CD-ROM – DVD
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
7
Magnetic Disk
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
8
Magnetic Disk (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
9
Magnetic Disk (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
10
Characteristics of Magnetic Disk • • • • • •
Number of platters Single vs. two sided Number of tracks Number of sectors per track Number of bytes per sector Cylinders
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
11
Speed Characteristics of Magnetic Disk • • • • •
Seek time Rotational latency Access time Block transfer time Which is longest?
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
12
RAID • Redundant Array of Inexpensive (Independent) Disks • A set of disk drives is viewed by the OS as a single logical drive • Data is distributed across drives • Parallelism • Redundant disk capacity used to store additional bits for reliability COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
13
RAID (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
14
RAID (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
15
CD-ROM
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
16
Other Media • • • • •
Writable versions of CD DVD Writable versions of DVD Tapes Memory cards (cameras, etc)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
17
Primary Storage • • • • • • •
Often called main memory Unique address for each location n address bits can address 2n locations Access one word at a time Basic operations are read and write Storage cells exhibit two stable states: 0, 1 Can be written into (at least once) to set the state • Can be read to sense the state COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
18
Operation of Memory • Example (assuming 8 bit address and data sizes)
Read
Address
Write
Memory
Data bus
Basic Memory Structure
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
19
Operation of Memory (cont) • Read – Load the address register with 175 – Set the read control signal – Some time later, the contents of word 175, 38 in this example, will be on the data output lines of the memory
• Write – Load the address register with 175 – Load the data buffer register with the new contents of word 175 – Set the write control signal – Some time later, the contents of word 175 will have the new value. COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
20
Properties of Main Memory • Random access (RAM) – Same access time to access any memory location – Contrast to tapes and disks – Synonymous with read-write memory
• Cycle time – Minimum time required between two successive read or write operations – Physical property of the memory COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
21
Properties of Main Memory (cont) • Access time – Delay between the start and finish of a memory operation - usually measured in nanoseconds (10-9) or picoseconds (10-12)
• Volatility – Semiconductor RAM memories lose data when power is removed. – Disks and tape retain data for years – Some memories have battery backup COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
22
Properties of Main Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
23
Static vs. Dynamic Memory • Static – No action is required to maintain a stored value
• Dynamic – – – –
Value stored as a charge on a capacitor Gradually disappears Must be recharged continually (refreshed) Read operation is destructive so special circuitry is included to rewrite the contents after a read – 1-2 millisecond refresh interval – Refresh by dummy reads when not in use COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
24
Static vs. Dynamic Memory (cont) • Comparison – Dynamic cells are smaller (1/4) than static – Dynamic is cheaper – Dynamic requires less chips
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
25
Types of Memory
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
26
A Typical Static RAM • • • • • •
Convenient for small memories 2048 (211) words of memory 11 address lines Each word is 8 bits wide 8 data lines 2 control signals
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
27
A Typical EPROM • Similar to a static RAM • Erasable by exposure to ultraviolet light of the correct wavelength
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
28
A Typical Dynamic RAM
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
29
A Typical Dynamic RAM (cont) • 4M x 4 • 22 address bits normally required • Only 11 pins available owing to technological limitations on the number of pins • 22 bits are multiplexed on the eleven pins • Organised as 2048 x 2048 array (4,194,305) which are addressed separately by row and column (RAS and CAS) • 4 bits of data in each location • Refresh by cycling through all rows of memory with RAS low and CAS high COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
30
Other Memory Issues • Simultaneous multiple word access • Parity • ECC
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
31
Cache Memory • Memory is slow compared to the time required to execute instructions. • Memory becomes more expensive as it gets faster • Compromise – Place a small amount of very high speed memory to temporarily hold a portion of the memory being accessed. COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
32
Cache Memory (cont) • If the addressed location is in cache, it is used. Otherwise a block of memory is transferred from memory to cache. • Principle of locality
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
33
Cache Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
34
Cache Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
35
Cache Memory (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
36
Cache Memory (cont) • Performance is measured by hit ratio • Typical hit ratios are 0.9 - 1.0 • Update of main memory – Write through - write memory when cache is updated – Write behind (back) - a flag (valid bit) indicates cache location was changed. Write memory when cache must be reused. COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
37
Cache Examples • Main memory is 16 MBytes – 24 bit address – Byte addressable
• Memory block is 4 bytes • Memory is 4M blocks of 4 bytes each • Cache can hold 64 KBytes • Cache is 16K lines of 4 bytes each COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
38
Cache Mapping • Direct mapping cache • Associative cache • Set Associative cache
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
39
Direct Mapping Cache • Least expensive form • Maps each block of main memory into only one possible line of cache Cache Line 0 1 2 . . . m-1
COSC 243 (Computer Architecture)
Main memory blocks assigned 0, m, 2m, . . ., 2s-m 1, m+1, 2m+1, . . ., 2s-m+1 2, m+2, 2m+2, . . ., 2s-m-2
m-1, 2m-1, . . ., 2s-1
Lecture 6 - Memory and Storage Systems
40
Direct Mapping Cache (cont) i = j modulo m where i = cache line number m = number of lines in the cache j = main memory block number
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
41
Direct Mapping Cache (cont) • Split the full address into tag, line, and word fields • Address the cache with the line • Check that the tag in cache matches tag field of address
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
42
Direct Mapping Cache (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
43
Direct Mapping Cache (cont) • w=2 – (4 words in each cache line)
• s = 22 • r = 14 – (16K lines of cache)
• s-r = 8
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
44
Associative Cache • Most expensive form • No fixed mapping between main memory and cache lines • Split the full address into tag and word fields • Comparison between the required address tag and all stored tags is done simultaneously COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
45
Associative Cache (cont) • Cache replacement is typically round robin, FIFO(first in first out), or LRU (least recently used) • w=2 • s = 22
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
46
Associative Cache (cont)
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
47
Set Associative Cache • Cost compromise • Cache is split into v sets of k lines • number of lines in cache = v * k i = j modulo v where i = cache set number j = main memory block number v = number of sets in the cache
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
48
Set Associative Cache (cont) • A main memory block Bj can be mapped into any of the lines of set i • Several main memory blocks map to the same set, but can be put into any of the lines of the set • Split the full address into tag, set, and word fields • Common values of k (number of lines in a set) are 2, 4 COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
49
Set Associative Cache (cont) s+w
Tag
Memory Address Tag
Set
Word
d
w
s-d
Cache
Main Memory
Data
B0 Set 0
B1 B2
Set 1 X
X
Bj s+w
Compare
(hit in cache)
(miss in cache)
Two-way set associative cache organisation
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
50
Set Associative Cache (cont) • w=2 – (4 words in each cache line)
• s = 22 • d = 13 – (1 less than before since there are one-half as many sets as the 16 K lines of cache)
• s-d = 9 COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
51
Cache Replacement Algorithms • LRU – least recently used
• FIFO – first in first out
• LFU – least frequently used
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
52
Other Cache Issues • Single vs. 2-level cache • Unified vs. split cache
COSC 243 (Computer Architecture)
Lecture 6 - Memory and Storage Systems
53
