Lab 10
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Datasheet for Lab #10: DFFs and Registers Rising Edge Triggered D Flip-Flop Positive (Rising) Edge-Triggered D-Flip-Flops in Verilog Using the diagram of a positive-edge triggered D-FF created using an all NAND implementation shown in the lab manual, give the equations for F1-F6 in terms of D, CLK and other F1-F6 inputs. The first is done for you. f1 = ~(f4 & f2); f2 = ~(f1 & f5); f3 = ~(f6 & f4); f4 = ~(f3 & clk); f5 = ~(f4 & clk & f6); f6 = ~(f5 & d); After you have your equations, you should draw a black box diagram of your circuit that you are building. Draw a black box diagram of the DFF indicating specific switch values and LEDs are assigned to each input (this one is done for you). Label the inputs of the device as well as the input names assigned to each. The assignment for this step was to create a top-level module (use swt[0] for the clk, and swt[1] for D, LED[0] for q and LED[1] for q_not).
DFF swt[1]
swt[0]
Contains material © Digilent, Inc.
D
q
led[1]
q_not
led[0]
clk
www.digilentinc.com
4 pages
Exercise #10: DFFs and Registers
Page 2
Paste a copy of your code for the top level module as well as the DFF module.
Write the state table for a rising-edge triggered D flip-flop.
Fill in the following table based on your testing. Indicate when the value of D is locked into the D FF. Obviously, you can’t have a clock period of 175nsec using the switches for the clock. Just use the following as a guideline.
Exercise #10: DFFs and Registers
Page 3
Positive Edge-Triggered D-Flip-Flops with Preset (Set) and Clear (Reset) Using the diagram of the positive edge-triggered D FF with asynchronous inputs of preset and clear given in the lab manual, write the new equations for F1-F6. Use ACLR for clr, and PRE for set in the new equations. Equations for f1-f6. f1 = ~(f4 & f2 & ~preset); f2 = ~(f1 & f5 & ~clear); f3 = ~(f6 & f4 & ~preset); f4 = ~(f3 & clk & ~clear); f5 = ~(f4 & clk & f6 & ~preset); f6 = ~(f5 & d & ~clear); Draw a new black box diagram of the DFF indicating specific switch values and LEDs are assigned to each input. Label the inputs of the device as well as the input names assigned to each. Use swt[0] for the CLK, and swt[1] for ACLR, swt[2] for PRE, swt[3] for D, LED[0] for q and LED[1] for q_not.
Make the changes to your DFF module and to the top level module to create the new device Paste a copy of your code for the top level module as well as the DFF module.
Exercise #10: DFFs and Registers
Page 4
Program your BaSYS board and show that the output changes on the active edge of the clock only. Create a state table for a DFF clearly indicating the outputs for the device. Make certain to indicate the changing edge of the clock as an up arrow.
Exercise #10: DFFs and Registers
Page 5
Test your device with the following data and draw the outputs on the timing diagram. Make certain to clearly indicate the outputs to show synchronous and asynchronous input effects on the circuit.
Registers Use instantiations of the modules to create a one-bit register. Below is the diagram for a one bit register.
q_out mux_out DIN
q_out
DFF D
q
D_OUT
LD CLK
clk q_not
ACLR
Write the code for a one bit register module that would create one instantiation of the 2:1 mux and one instantiation of the DFF with PRE, ACLR capability. Have the q output of the FF be the I0 input into the mux. You should have four port inputs (DIN, LD, CLK, ACLR) and one output (D_OUT). Use a wire for mux_out. Use the names shown in the diagram above for your inputs and outputs.
Exercise #10: DFFs and Registers
Page 6
Four-bit Register
four-bit Register swt[6:3]
DIN[3:0]
swt[1]
LD
swt[0]
CLK
swt[2]
ACLR
DOUT[3:0]
led[3:0]
Show that your four-bit register works by changing the value of D, clock, ld and aclr. Show the code for a module for a four-bit register. Use four instantiations of the one-bit register module.
Show the code for a top level module, download the four bit register onto your BaSYS board and show that you can store data in the register.
Exercise #10: DFFs and Registers
Page 7
DFF swt[1]
swt[0]
Contains material © Digilent, Inc.
D
q
led[1]
q_not
led[0]
clk
www.digilentinc.com
4 pages
Exercise #10: DFFs and Registers
Page 2
Paste a copy of your code for the top level module as well as the DFF module.
Write the state table for a rising-edge triggered D flip-flop.
Fill in the following table based on your testing. Indicate when the value of D is locked into the D FF. Obviously, you can’t have a clock period of 175nsec using the switches for the clock. Just use the following as a guideline.
Exercise #10: DFFs and Registers
Page 3
Positive Edge-Triggered D-Flip-Flops with Preset (Set) and Clear (Reset) Using the diagram of the positive edge-triggered D FF with asynchronous inputs of preset and clear given in the lab manual, write the new equations for F1-F6. Use ACLR for clr, and PRE for set in the new equations. Equations for f1-f6. f1 = ~(f4 & f2 & ~preset); f2 = ~(f1 & f5 & ~clear); f3 = ~(f6 & f4 & ~preset); f4 = ~(f3 & clk & ~clear); f5 = ~(f4 & clk & f6 & ~preset); f6 = ~(f5 & d & ~clear); Draw a new black box diagram of the DFF indicating specific switch values and LEDs are assigned to each input. Label the inputs of the device as well as the input names assigned to each. Use swt[0] for the CLK, and swt[1] for ACLR, swt[2] for PRE, swt[3] for D, LED[0] for q and LED[1] for q_not.
Make the changes to your DFF module and to the top level module to create the new device Paste a copy of your code for the top level module as well as the DFF module.
Exercise #10: DFFs and Registers
Page 4
Program your BaSYS board and show that the output changes on the active edge of the clock only. Create a state table for a DFF clearly indicating the outputs for the device. Make certain to indicate the changing edge of the clock as an up arrow.
Exercise #10: DFFs and Registers
Page 5
Test your device with the following data and draw the outputs on the timing diagram. Make certain to clearly indicate the outputs to show synchronous and asynchronous input effects on the circuit.
Registers Use instantiations of the modules to create a one-bit register. Below is the diagram for a one bit register.
q_out mux_out DIN
q_out
DFF D
q
D_OUT
LD CLK
clk q_not
ACLR
Write the code for a one bit register module that would create one instantiation of the 2:1 mux and one instantiation of the DFF with PRE, ACLR capability. Have the q output of the FF be the I0 input into the mux. You should have four port inputs (DIN, LD, CLK, ACLR) and one output (D_OUT). Use a wire for mux_out. Use the names shown in the diagram above for your inputs and outputs.
Exercise #10: DFFs and Registers
Page 6
Four-bit Register
four-bit Register swt[6:3]
DIN[3:0]
swt[1]
LD
swt[0]
CLK
swt[2]
ACLR
DOUT[3:0]
led[3:0]
Show that your four-bit register works by changing the value of D, clock, ld and aclr. Show the code for a module for a four-bit register. Use four instantiations of the one-bit register module.
Show the code for a top level module, download the four bit register onto your BaSYS board and show that you can store data in the register.
Exercise #10: DFFs and Registers
Page 7
