Kernel Based On Genetic Algorithms

  • Uploaded by: Ankita
  • 0
  • 0
  • May 2020
  • PDF

This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA


Overview

Download & View Kernel Based On Genetic Algorithms as PDF for free.

More details

  • Words: 2,357
  • Pages: 4
A General-purpose Kernel based on Genetic Algorithms for Optimization of Complex Analog Circuits B. Vaz1,2, R. Costa1,2, N. Paulino1,2, J. Goes1,2, R. Tavares1,2 and A. Steiger-Garção1,2 1

UNINOVA – CRI Campus da Faculdade de Ciências e Tecnologia 2825 – 114 Monte da Caparica – PORTUGAL E-mail: [email protected] Abstract - This paper presents a general-purpose kernel based genetic algorithms for optimizing complex analog circuits and systems. The developed tool is very flexible allowing optimizations at different levels of abstraction. The optimization of any new block is basically carried-out by simply providing two additional files to the kernel. A text file containing the information of the genes (variables) of the chromosome and, on the other hand, a dynamic link library (DLL) type file, which is obtained by compiling a C++ code-source file comprising the overall fitness function. Optimization examples of two low-voltage circuits clearly assess the attractiveness of this tool.

1. INTRODUCTION According to the Semiconductor Industry Association’s roadmap [1] a fast scaling-down of the transistor’s minimum channel lengths is expected. Furthermore, this technology scaling will be accomplished by a reduction of the supply voltages of the circuits (1.8 Volt by 2000 and 0.3 Volt by 2014). However, this reduction of the supply voltage severely affects the analog circuit design basically due to two main reasons. Firstly, in smaller technologies, the supply voltage scales roughly linear with the minimum feature size but the threshold voltages of the transistors do not. As a consequence, the number of topologies capable of operating at low voltages is highly reduced. On the other hand, since the voltage swings have to be proportionally decreased, the signal-to-noise ratios of the circuits are directly affected. In order to maintain the current efficiency (power dissipation) is mandatory to have efficient optimization tools to assure that the overall performance of the circuit or system is not degraded. Moreover, from the IC market point of view is highly desirable to have short redesign cycles either for different technologies or specifications. Several approaches for automatic design and optimization (automatic sizing) of analog cells were already proposed using statistical optimization techniques such as simulated annealing, either in equation-based systems [2] or in simulation-based systems [3]. The optimization tool proposed in this paper follows, as suggested in [4], an equation-based approach for optimization of analog building blocks using

2

Faculdade de Ciências e Tecnologia Campus da Faculdade de Ciências e Tecnologia 2825 – 114 Caparica – PORTUGAL E-mail: [email protected] genetic algorithms. The optimization of any new block is basically carried-out by simply providing two additional files to the kernel. A text file containing the information of the genes (variables) of the chromosome and, on the other hand, a dynamic link library (DLL) type file, which is obtained by compiling a C++ code-source file comprising the overall fitness function. Two examples are given to illustrate the efficiency of the optimizer at both, circuit and system levels. In section 3 the results of the optimization of a lowvoltage pipelined ADC are shown, taking into account major issues, such as, thermal noise, power dissipation and linearity. In section 4, the results of the optimization of a lowvoltage two-stage Miller compensated amplifier are presented and compared with simulated results. Finally, conclusions are drawn in section 5.

2. DESCRIPTION OF THE GENERAL-PURPOSE KERNEL STRUCTURE

2.1 – ARCHITECTURE OF THE TOOL

Figure 1 – Tool’s Architecture. The architecture of the proposed kernel is presented in Figure 1. There are two text files that should be provided to the application: one contains the structure of the chromosome and another the desired parameters that are envisaged. The chromosome, x , consists of one or more genes. Basically, the genes are the variables, xi, that the algorithm will found

that best fit the desired goals. The first file comprises the information regarding the upper (Lmax) and lower (Lmin) limits of the genes and also the resolution of each gene (Rg). The second file contains the desired value and the relative strength of all of them. Additionally it can be provided, depending on the problem, another text file containing specific parameters – Technology file -. One of the most important blocks of this architecture is the DLL that contains the fit-

()

ness function, f x . This file has all the mathematical functions that model the behavior circuit. The chromosome that best fits the goal (the entire set of the desired parameters) is saved for later simulation and confirmation of the results.

a)

b)

Figure 2 – (a) Roulette System for 5 individuals; (b) Rank System for 5 individuals B – Cross-operator

2.2 – GENETIC ALGORITHM

Within each chromosome, genes are represented in binary code where the number of bits is dependent of the desired precision according to:

The heart of the application is the genetic algorithm. A full description of the genetic algorithm’s theory is out of the scope of this paper. Basically, this algorithm can be summarized in the next steps.

x i = L min + (L max − L min )

1. 2.

Initialize the population P with a set of d individuals While the stop condition isn’t reached:

()



For each individual (chromosome) x , calculate f x



Select s individuals form P to be in the new population Ps. Each individual is selected according with his probability of selection Select (d-s) individuals to be crossed. Each individual is selected according to his probability of selection. The new individuals are placed into the new population Ps Select m individuals of Ps and apply the mutation operator P = Ps

• • •

Rg −1

∑b j =0

j

⋅2 j

(2

Rg

)

−1

(1)

With this type of coding, the cross and the mutation operators can be easily implemented. To cross two selected individuals (parents), first a random cross point is chosen and the new individuals are made of genetic material of his parents. An example of the cross-operator is shown in Figure 3.

A - Selection One possible approach to select the individuals is to predefine a percentage of individuals that are directly copied into the next population. The remaining individuals are crossed and finally the mutation operator is applied to new population. A different approach is that only the best chromosome is copied to next population and it remains unchanged. There are two ways of selecting individuals: roulette and rank systems. In the Roulette system, each individual has a fitness associated, fi, which consists on a normalized value between 0 and 1. This value represents directly the probability that one individual has to be chosen. An example is presented in Figure 2 (a). Another possibility of selection is the Rank system as illustrated in Figure 2 (b). Firstly, all the individuals are ordered according to their fitness and, secondly, the probability of one individual to be selected is proportional to its position. Again, Figure 3, illustrates the rank system for an example of a population with five individuals.

Figure 3 – The Cross-operator. C – The Mutation Operator The mutation operator work as follows. Firstly, one bit of the gene to be mutated is randomly chosen. This bit changes its digital value as it is represented in Figure 4.

Figure 4 – The Mutation Operator. There is a possibility of varying the mutation bit according to the number of the generation. In the beginning all the bits might be chosen to be mutated but, after a given number of generations only the least significant bits can be mutated.

3. SYSTEM-LEVEL OPTIMIZATION OF A LOWVOLTAGE LOW-POWER PIPELINE ADC Previous studies concerning the problem of optimizing the resolution-per-stage in pipeline ADCs while minimizing the power dissipation have been already reported [5, 6], but none of these works optimize the distribution of the noise contributions of the several pipelined stages to the total input referred noise. This is an issue harder to manage by the need of keeping the unit capacitances above a minimum for feasibility and matching reasons. The methodology and the tool addressed in this paper is quite general, since it is capable of exploring different noise distributions while optimizes simultaneously several other design parameters, namely, power dissipation, resolution-per-stage and maximum expectable DNL errors. The fitness function was defined as

lengths of the transistors, Li, and their saturation voltages, Vdsati. M1 represents the PMOS transistors of the differential-pair, and M6 is the transistor of the second gain stage. M2, M4 are, respectively, the PMOS and the NMOS current sources. Ibias is the value of the biasing current of the differential-pair and gene MF represents the mirror factor of this current to the output branch (second stage). Cc and Rc are, respectively, the compensation capacitor and resistor.  A _ achieved    Output _ swing _ achieved      − 0 −   A0 _ desired     Output _ swing _ desired  1 f ( x ) ≈ 1 − e e −       (3)     2 nd _ pole _ achieved    total _ current _ desired      − −   2 nd _ pole _ desired     total _ current _ achieved   1 − e 1 − e      

 noise _ desired    DNL _ desired      −  −   noise _ achieved     DNL _ achieved  f ( x ) ≈ 1 − e 1 − e        (2)  PowerDiss _ desir .     −   2   PowerDiss _ achiev.   1 − e  − (Re s − Re s _ desir.) (Re s − Re s _ desir.)  + e    e  

For the sake of simplicity, complex equations for calculating all achieved parameters are not shown. The structure of the chromosome is depicted in Figure 5 as well as the results of the best chromosome. The desired specifications were, respectively for the input-referred squared-noise, for the power dissipation and for the DNL, 79.5 nV2, 13.3 mW and 0.5 LSB. The output of the optimizer is shown in Figure 6 for an example of the optimization of a 10-bit (Res_desired) 20 MS/s 1.5 Volt pipelined ADC designed for a 0.35µm CMOS technology. The achieved squared-noise, power dissipation and maximum DNL error were, respectively, 77 nV2, 10.4 mW and 0.52 LSB@10bit. # of stages (NS)

5

C (S&H)

0.64pF

3b

Res. stage 1

0.016pF

Cunit Res. (stage 1) stage 2

3b

0.05pF

Cunit (stage 2)

3b

0.05pF

... 3b

Res (stage NS)

0.05pF

2b

Figure 5 – Chromosome used for the optimization of a lowvoltage pipeline ADC and best chromosome results.

4. CIRCUIT-LEVEL OPTIMIZATION OF A LOWVOLTAGE TWO-STAGE MILLER-OPAMP The second example presented in this paper comprises the design and the optimization of a 1.5 Volt CMOS two-stage Miller-compensated opamp. The fitness function was roughly defined according to expression (3). The structure of the chromosome is depicted in figure 7 as well as the results of the best chromosome. The genes are basically the channel

Figure 6 – Evolution of the squared-noise, power dissipation and maximum DNL error during 120 generations.

L1

Vdsat1

1.2 µ m 175mV

L2

Vdast2

L4

Vdsat4

1.2 µ m 250mV 1.2 µ m 166mV

L6

Vdsat6

1.2 µ m 100mV

Ibias

MF

65 µ A 1.83

Cc

Rc

1.79pF 1.16k Ω

Figure 7: Format of the chromosome used in the genetic algorithm for the 2-stage opamp optimization and best chromosome results

simulated values using an electrical simulator (HSPICE) and BSIM3.v3 models. As it can be observed both achieved and simulated values are relatively close. The major differences between the desired specifications and the achieved/simulated occur for the DC gain due to problems on modeling the drain-source impedance of the transistors at low voltages. The 2nd. pole frequency achieved was also larger than the desired since desired total current was larger than the required value to reach the desired specs. Table 1. Optimized and post-simulated results for the opamp. Specs. Specs. Simulated desired achieved Results 60 94 93 A0 (dB) 60 95 120 2nd. pole freq.(MHz) 1 1.04 1.02 Output Swing (V) 200 185 186 Total current (µA)

5. CONCLUSIONS This paper presented a general-purpose kernel based genetic algorithms for optimizing complex analog circuits and systems. The developed tool is very flexible allowing optimizations at different levels of abstraction. Optimization examples of two low-voltage circuits were presented to clearly assess the attractiveness of this tool.

ACKNOWLEDGMENTS The research work that led to this implementation was partially supported by the Portuguese Foundation for Science and Technology under ADOPT (PCTI/1999/ESE/33311) Project.

REFERENCES

Figure 8. Evolution of the DC gain (A0), output swing, 2nd. pole frequency and total current during 120 generations. Figure 8 show the evolution results during 120 generations, of the DC gain (A0), output swing, 2nd. pole frequency and total current. Table 1 compares the obtained values of these parameters after the optimization concluded with post-

[1] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1999. [2] G. E. Gielen, H. Walsharts and W. Sansen, “Analog circuits design optimization based on symbolic simulation and simulated annealing”, IEEE Journal of Solid-State Circuits, vol. 25, pp. 707-713, June 1990. [3] F. Medeiro, R. Rodríguez-Macías, F. V. Fernández, R. Domínguez-Castro, J. L. Huertas and A. Rodríguez-Vázquez, “Global Design of Analog Cells Using Statistical Optimization Techniques”, Analog Integrated Circuits and Signal Processing, 6, 179-195, Kluwer Academic Publishers, 1994. [4] Nuno Paulino, João Goes and Adolfo Steiger-Garção, “Design Methodology for Optimization of Analog Building-Blocks using Genetic Algorithms”, IEEE International Symposium on Circuits and Systems (ISCAS’2001), Australia, May 2001. [5] Stephen H. Lewis, “Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications”, IEEE Transactions on Circuits and Systems – II, vol. 39, no. 8, pp. 516-523, August 1992. [6] João Goes, João C. Vital and José E. Franca, "Systematic Design for Optimization of High-Speed Pipelined A/D Converters using Self-Calibration", IEEE Transactions on Circuits and Systems, vol. II, pp. 1513-1526, December 1998.

Related Documents


More Documents from ""