IRF9540, RF1S9540SM Data Sheet
19A, 100V, 0.200 Ohm, P-Channel Power MOSFETs These are P-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. Formerly Developmental Type TA17521.
Ordering Information PART NUMBER
PACKAGE
January 2002
Features • 19A, 100V • rDS(ON) = 0.200Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol BRAND
IRF9540
TO-220AB
IRF9540
RF1S9540SM
TO-263AB
RF1S9540
D
G
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S9540SM9A.
S
Packaging JEDEC TO-220AB
JEDEC TO-263AB SOURCE DRAIN GATE
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
DRAIN (FLANGE) GATE SOURCE
IRF9540, RF1S9540SM Rev. B
IRF9540, RF1S9540SM TC = 25oC, Unless Otherwise Specified
Absolute Maximum Ratings
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
IRF9540, RF1S9540SM -100 -100 -19 -12 -76 ±20 150 1 960 -55 to 175
UNITS V V A A A V W W/oC mJ oC
300 260
oC oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS V
Drain to Source Breakdown Voltage
BVDSS
ID = -250µA, VGS = 0V (Figure 10)
-100
-
-
Gate to Threshold Voltage
VGS(TH)
VGS = VDS, ID = -250µA
-2
-
-4
V
VDS = Rated BVDSS, VGS = 0V
-
-
-25
µA µA
Zero Gate Voltage Drain Current
IDSS
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC On-State Drain Current (Note 2)
ID(ON)
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge
rDS(ON) gfs td(ON) tr td(OFF)
VGS = ±20V
Qg(TOT) Qgs Qgd
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS LD
LS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
©2002 Fairchild Semiconductor Corporation
-
-250
-
-
A
-
-
±100
nA
ID = -10A, VGS = -10V (Figures 8, 9)
-
0.150
0.200
Ω
5
7
-
S
VDD = -50V, ID ≈19A, RG = 9.1Ω, RL = 2.3Ω, VGS = -10V, (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature
-
16
20
ns
-
65
100
ns
-
47
70
ns
-
28
70
ns
VGS = -10V, ID = -19A, VDS = 0.8 x Rated BVDSS, Ig(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature
-
70
90
nC
-
14
-
nC
-
56
-
nC
VDS = -25V, VGS = 0V, f = 1MHz (Figure 11)
-
1100
-
pF
-
550
-
pF
-
250
-
pF
-
3.5
-
nH
-
4.5
-
nH
-
7.5
-
nH
-
-
1
oC/W
-
-
62.5
oC/W
Measured From the Contact Screw on Tab to the Center of Die Measured From the Drain Lead, 6mm (0.25in) from Package to the Center of Die
Internal Source Inductance
-19
VDS > ID(ON) x rDS(ON) MAX, ID = -6A (Figure 12)
tf
Gate to Drain “Miller” Charge
Internal Drain Inductance
VDS > ID(ON) x rDS(ON) MAX, VGS = -10V
Measured From the Source Lead, 6mm (0.25in) From Package to Source Bonding Pad Typical Socket Mount
Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S
IRF9540, RF1S9540SM Rev. B
IRF9540, RF1S9540SM Source to Drain Diode Specifications PARAMETER
SYMBOL
Continuous Source to Drain Current Pulse Source to Drain Current (Note 3)
ISD ISDM
TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
MIN
TYP
MAX
-
-
-19
UNITS A
-
-
-76
A
-
-
-1.5
V
-
170
-
ns
-
0.8
-
µC
D
G
S
Source to Drain Diode Voltage (Note 2) Reverse Recovery Time
VSD trr
Reverse Recovery Charge
QRR
TC = 25oC, ISD = -19A, VGS = 0V (Figure 13) TJ = 150oC, ISD = 19A, dISD/dt = 100A/µs TJ = 150oC, ISD = 19A, dISD/dt = 100A/µs
NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 4mH, RG = 25Ω, peak IAS = 19A. (Figures 15, 16). Unless Otherwise Specified
1.2
-20
1.0
-20
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8 0.6 0.4 0.2 0 25
0
125 50 75 100 TC , CASE TEMPERATURE (oC)
150
175
-15
-10
-5
0 25
75
175
125
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
ZθJC, TRANSIENT THERMAL IMPEDANCE (oC/W)
1 0.5 0.2 0.1
PDM
0.1 0.05
t1
0.02 0.01
t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x RθJC + TC
SINGLE PULSE
0.01 10-5
10-4
10-3 10-2 10-1 t1 , RECTANGULAR PULSE DURATION (s)
1
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
IRF9540, RF1S9540SM Rev. B
IRF9540, RF1S9540SM Typical Performance Curves
Unless Otherwise Specified (Continued)
200
-100
VGS = -16V
100 ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
10µs 100µs 1ms
10
10ms 100ms
OPERATION IN THIS AREA IS LIMITED BY rDS(ON)
1
DC
TC = 25oC TJ = MAX RATED 0.1
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
-80
VGS = -12V
-60
VGS = -10V -40 VGS = -9V VGS = -8V -20 VGS = -5V
SINGLE PULSE 1
0
10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)
500
0
VGS = -12V
-40 VGS = -10V VGS = -9V
-30
VGS = -8V -20 VGS = -7V VGS = -6V
-10
0
0
-2
-4
VGS = -5V VGS = -4V -6 -8
-10
-100
TJ = 125oC -1
TJ = 25oC TJ = -55oC
-0.1
0
-2
VGS = -20V
0.14
0.10
-20
-40 -60 ID, DRAIN CURRENT (A)
-80
-100
NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
©2002 Fairchild Semiconductor Corporation
-14
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
RESISTANCE (Ω)
rDS(ON), DRAIN TO SOURCE ON
VGS = -10V
0
-12 -4 -6 -8 -10 VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
0.18
-50
-10
FIGURE 6. SATURATION CHARACTERISTICS
0.22
VGS = -4V -40
-30
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.26
-20
FIGURE 5. OUTPUT CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = -16V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -14V
-10
VGS = -7V VGS = -6V
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
-50
VGS = -14V
1.5
VGS = -10V, ID = 10A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
1.0
0.5
0.2 -40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
IRF9540, RF1S9540SM Rev. B
IRF9540, RF1S9540SM Typical Performance Curves
Unless Otherwise Specified (Continued)
2000
1.15
0.95
0.85
CISS
1200
800
COSS
400
CRSS
0
0.75 -40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
-10
0
160
-30
-20
-50
-40
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
100
15
12
ISD, SOURCE TO DRAIN CURRENT (A)
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX gfs, TRANSCONDUCTANCE (S)
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD
1600 1.05
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
ID = 250µA
TJ = -55oC
9
TJ = 25oC TJ = 125oC
6
3
-20
-40 -60 ID, DRAIN CURRENT (A)
-80
TJ = 150oC TJ = 25oC
10
1
0.1 0.4
0 0
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
-100
0.8
1.0
1.2
1.4
1.6
1.8
VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
VGS, GATE TO SOURCE (V)
0.6
ID = -19A
-5
VDS = -20V VDS = -50V
-10
VDS = -80V
0
20 40 60 Qg(TOT) , GATE CHARGE (nC)
80
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation
IRF9540, RF1S9540SM Rev. B
IRF9540, RF1S9540SM Test Circuits and Waveforms
VDS tAV L
0
VARY tP TO OBTAIN
-
RG
REQUIRED PEAK IAS
+
VDD
DUT
0V
VDD
tP
VGS
IAS
IAS
VDS
tP 0.01Ω
BVDSS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF td(OFF)
td(ON) tr 0
RL
-
DUT VGS
+
10%
10%
VDS
VDD
RG
tf
90%
90%
VGS 0
10% 50%
50% PULSE WIDTH 90%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
-VDS (ISOLATED SUPPLY)
CURRENT REGULATOR
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
0 VDS
DUT 12V BATTERY
0.2µF
50kΩ 0.3µF Qgs
Qg(TOT)
DUT
G
VGS Qgd
D
VDD 0 S
Ig(REF) IG CURRENT SAMPLING RESISTOR
0 +VDS ID CURRENT SAMPLING RESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
Ig(REF)
FIGURE 20. GATE CHARGE WAVEFORMS
IRF9540, RF1S9540SM Rev. B
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Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4