Introduction To Vhdl

INTRODUCTION TO VHDL VHDL offers the following advantages for the digital design: · Standard: VHDL is an IEEE standard. Just like any standard it reduces confusion and makes interface easier. · Support from Industry: With the advent of more powerful and efficient VHDL tools, it has gained more support from the electronic industry. · Modeling Capability: VHDL was developed to model all levels of design. VHDL can accommodate behavioral constructs and mathematical routines that describe the complex models. · Reusability: changing the value of the parameters can reuse generic codes written in VHDL.

WHAT IS LOGIC SYNTHESIS? Logic synthesis is the process of taking a form of input (VHDL), translating it into form and then optimizing in terms of propagation delay or area. Once the VHDL code is translated into an internal form, the optimization process can be performed based on the nature of constraints such as speed, area, power and So on.

VHDL TERMS Before we go further, let’s define some of the terms that we will be using throughout the book. There are some basic VHDL building blocks that are used in almost every description. 1) Entity: All designs are expressed in terms of entities. An entity is the most basic Building block in a design. 2) Architecture: All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity. 3) Configuration: A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a part list for a design. It describes which behavior to use for each entity. 4) Package: A Package is a collection of commonly used data types and subprogram used in a design. 5) Bus: The term bus usually brings to mind a group of signals or a particular method of communication used in the design of hardware. 6) Driver: This is a source on a signal. If a signal is driven by two tristate inverters, when both inverters are active, the signal will have two drivers.

7) Process: A Process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes. 8) Generic: A Generic is a VHDL’s term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and fall delay, values for the rise and fall delays could be passed into the entity with the generics.

EXPERIMENT 1 AIM: To design and verify all basic gates using VHDL.

THEORY: First, VHDL code for basic gates was written and block was generated. Code for basic gates is written. The logic function can be realized using only basic gates.

VHDL code of Basic Gates: library ieee; use ieee.std_logic_1164.all;

entity checkgates is port(a,b:in std_logic; c,d,e,f,g,h,i: out std_logic); end checkgates;

architecture ar_checkgates of checkgates is begin c<=( a and b); d<=( a or b); e<=( not a); f<=( a nor b); g<=( a nand b); h<=( a xor b); i<=(not (a xor b)); end ar_checkgates;

RTL VIEW:

SIMULAION WAVEFORM:

CONCLUSION: 1. Truth table for all the basic gates are verified from output waveform. 2. RTL viewer of different basic gates are obtained.

EXPERIMENT 2 AIM: To design a half adder using data flow modelling.

THEORY: First, VHDL code for half adder was written and block was generated. Half adder block as component and basic gates, code for half adder is written. The truth tables are as follows: HALF ADDER: A B SUM CARRY 0 0 1 1

0 1 0 1

0 1 1 0

0 0 0 1

FULL ADDER: A B CIN SUM COUT 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

SUM

0 1 0 1 0 1 0 1 0 0

0 1

1

0 1 1 0 1 0 0 1 0 1 1

1 1

0 0 0 1 0 1 1 1 10 1

1 CARRY

00

01

0 1 SUM = A XOR B XOR C;

11

10

1 1

1

CARRY = AB + AC + BC;

1

VHDL code of Half Adder: library IEEE; use IEEE.STD_LOGIC_1164.all; entity HA is port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC); end HA; architecture struct of HA is component myXOR port(in1,in2:in STD_LOGIC; out1:out STD_LOGIC); end component; begin X1: myXOR port map(A,B,Sum); Carry<=A and B; end struct;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSION: 1. Truth table for all the models of half adder and full adder are verified from output waveform. 2. RTL of different models half adder and full adder are obtained.

EXPERIMENT 3 AIM: To design a full adder using data flow modelling.

THEORY: First, VHDL code for full adder was written and block was generated. Half adder block as component and basic gates, code for full adder is written. The truth tables are as follows: FULL ADDER: A B CIN SUM COUT 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

SUM

0 1 0 1 0 1 0 1 0 0

0 1

1

0 1 1 0 1 0 0 1 0 1 1

1 1

0 0 0 1 0 1 1 1 10 1

1 CARRY

00

01

0 1 SUM = A XOR B XOR C;

11

10

1 1

1

CARRY = AB + AC + BC;

1

VHDL code of Full Adder: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FA_DF is port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT); end FA_DF; architecture FA_dataflow of FA_DF is begin Fs <= Fx XOR Fy XOR Fcin; Fcout <= (Fx AND Fy) OR (Fx AND Fcin) OR (Fy AND Fcin); end FA_dataflow;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSION: 1. Truth table for all the models of full adder are verified from output waveform. 2. RTL of different models full adder are obtained.

EXPERIMENT 4 AIM: To design JK flip flop using select statement and case statement.

THEORY: There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or complement its output. The JK flip-flop performs all three operations. The J input set the flipflop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented. This can be verified by investigating the circuit applied to the D input: D = JQ’ + K’Q When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1. When J = 0 and K = 0, so the next clock edge resets the output to 0. When J = K = 1, D = Q’, the next clock edge complements the output. When both J = K = 0, D = Q, the clock edge leaves the output unchanged. The truth table for jk flip-flop are as follows:

J

K

Q(t + 1)

0

0

0

1

1

0

1

1

VHDL CODE FOR JK FLIP-FLOP: library ieee; use ieee.std_logic_1164.all;

entity jkff is port(clk, j, k: in BIT; a, b: buffer BIT); end jkff;

Architecture beh of jkff is begin process(clk) begin if clk'event and clk = '1' then a <= ((j and b)or((not k)and a)); b <= (not((j and b)or((not k)and a))); end if; end process; end beh;

RTL VIEW:

Q(t) No change 0 1

Reset Set

Q’(t)Complement

SIMULATION WAVEFORM:

Conclusion: 1.The truth table for JK flip-flop is verified. 2.The RTL were obtained.

EXPERIMENT 5 AIM: To design 4X1 multiplexer.

THEORY: A multiplexers is a combinational circuit has selects binary informational from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected. The truth table for 4x1 multiplexer are as follows:

S1

S0

Y

0

0

D0

0

1

D1

1

0

D2

1

1

D3

VHDL CODE FOR MULIPLEXER USING WITH SELECT STATEMENT: use IEEE.std_logic_1164.all; library IEEE; entity mux41v2 is port( d0 d1 d2 d3 s y

: in : in : in : in : in : out

std_logic; std_logic; std_logic; std_logic; std_logic_vector(1 downto 0); std_logic

); end mux41v2; architecture arch1 of mux41v2 is begin with s select y <= d0 when "00", d1 when "01", d2 when "10", d3 when "11"; end arch1;

VHDL CODE FOR MULIPLEXER USING CASE STATEMENT: library IEEE; use IEEE.std_logic_1164.all; entity mux_logic is

port(A,B,C,D:in std_logic; ctrl:in std_logic_vector(0 to 1); z:out std_logic); end mux_logic; architecture mux_1 of mux_logic is constant mux_delay:time:=10 ns; begin pmux:process(A,B,C,D,ctrl) variable temp:std_logic; begin case ctrl is when "00"=>temp:=A; when "01"=>temp:=B; when "10"=>temp:=C; when "11"=>temp:=D; when others=>temp:=A; end case; z<=temp after mux_delay; end process pmux; end mux_1;

VHDL CODE FOR MULIPLEXER USING IF-ELSE STATEMENT: library IEEE; use IEEE.std_logic_1164.all; entity mux2 is port(A,B,C,D:in std_logic; ctrl:in std_logic_vector(0 to 1); z:out std_logic); end mux2; architecture mux_logic of mux2 is begin p1:process(A,B,C,D,ctrl) variable temp:std_logic; begin if ctrl="00" then temp:=A; elsif ctrl="01" then temp:=B; elsif ctrl="10" then temp:=C;

elsif ctrl="11" then temp:=D; else temp:='0'; end if; z<=temp; end process; end mux_logic;

RTL VIEW:

SIMULATION WAVEFORM:

Conclusions: 1.4X1 multiplexer was realized using behavioral model as the architecture. 2. The 4X1 multiplexer verified for various combination of inputs.

EXPERIMENT 6 AIM: To design priority encoder.

THEORY: A priority encoder is an encoder that includes the priority functions.the operation of the priority encoder is such that if two or more inputsare equal to 1 at the same time,the inputs having the highest priority will take precedence.the truth table of a four-input priority encoder are as follows: INPUTS

OUTPUTS

D0 0 1 X X

D1 D2 D3 Y2 Y1 Y 0 0 0 X X 0 0 0 0 0 0 1 1 0 0 0 1 1 X 1 0 1 0 1

X

X

X

1

1

1

1

VHDL CODE FOR PRIORITY ENCODER USING CASE,IF-ELSE STATEMENT: library ieee; use ieee.std_logic_1164.all; entity pri_encoder_using_if is port ( enable :in std_logic; -- Enable for the encoder encoder_in :in std_logic_vector (15 downto 0);-- 16-bit Input binary_out :out std_logic_vector (3 downto 0) -- 4 bit binary Output ); end entity; architecture behavior of pri_encoder_using_if is begin process (enable, encoder_in) begin binary_out <= "0000"; if (enable = '1') then if (encoder_in = "XXXXXXXXXXXXXX10") then binary_out <= "0001"; elsif (encoder_in = "XXXXXXXXXXXXX100") then binary_out <= "0010"; elsif (encoder_in = "XXXXXXXXXXXX1000") then binary_out <= "0011"; elsif (encoder_in = "XXXXXXXXXXX10000") then binary_out <= "0100"; elsif (encoder_in = "XXXXXXXXXX100000") then binary_out <= "0101"; elsif (encoder_in = "XXXXXXXXX1000000") then binary_out <= "0110"; elsif (encoder_in = "XXXXXXXX10000000") then binary_out <= "0111"; elsif (encoder_in = "XXXXXXX100000000") then binary_out <= "1000"; elsif (encoder_in = "XXXXXX1000000000") then binary_out <= "1001"; elsif (encoder_in = "XXXXX10000000000") then binary_out <= "1010"; elsif (encoder_in = "XXXX100000000000") then binary_out <= "1011"; elsif (encoder_in = "XXX1000000000000") then binary_out <= "1100"; elsif (encoder_in = "XX10000000000000") then binary_out <= "1101";

elsif (encoder_in = "X100000000000000") then binary_out <= "1110"; else binary_out <= "1111"; end if; end if; end process; end architecture;

VHDL CODE FOR PRIORITY ENCODER USING WHEN ELSE STATEMENT: library ieee; use ieee.std_logic_1164.all; entity pri_encoder_using_when is port ( enable :in std_logic; -- Enable for the encoder encoder_in :in std_logic_vector (15 downto 0);-- 16-bit Input binary_out :out std_logic_vector (3 downto 0) -- 4 bit binary Output ); end entity; architecture behavior of pri_encoder_using_when is begin binary_out <= "0000" when (enable = '0') else "0000" when (encoder_in = "XXXXXXXXXXXXXXX1") else "0001" when (encoder_in = "XXXXXXXXXXXXXX10") else "0010" when (encoder_in = "XXXXXXXXXXXXX100") else "0011" when (encoder_in = "XXXXXXXXXXXX1000") else "0100" when (encoder_in = "XXXXXXXXXXX10000") else "0101" when (encoder_in = "XXXXXXXXXX100000") else "0110" when (encoder_in = "XXXXXXXXX1000000") else "0111" when (encoder_in = "XXXXXXXX10000000") else "1000" when (encoder_in = "XXXXXXX100000000") else "1001" when (encoder_in = "XXXXXX1000000000") else "1010" when (encoder_in = "XXXXX10000000000") else "1011" when (encoder_in = "XXXX100000000000") else "1100" when (encoder_in = "XXX1000000000000") else "1101" when (encoder_in = "XX10000000000000") else "1110" when (encoder_in = "X100000000000000") else "1111"; end architecture;

RTL VIEW:

SIMULATION WAVEFORM:

Conclusions: 1.Priority Encoder was realized using behavioral model as the architecture. 2. The Priority Encoder verified using simulation waveform.

EXPERIMENT 7 AIM: To design decoder using behavioural model.

THEORY: Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is capable of representing up to 2 n distinct elements of coded information. A decoder is a combinational circuit that converts binary informational from n input lines to a maximum of 2n unique output lines. If the n-bit coded information has unused combinations, the decoder may have fewer than 2n outputs. The decoders presented here are called n-to-m-line decoders, where m ≤ 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder is also used in conjunction with other code converters such as a BCD-to-seven-segment decoder. The entity of the decoder with the truth table are as follows:

VHDL CODE DECODER: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dec24d IS PORT(A,B,EN_L:IN BIT; Q0,Q1,Q2,Q3:OUT BIT); END ENTITY; ARCHITECTURE dataflow OF dec24d IS BEGIN Q0<=(NOT A)AND (NOT B) AND (NOT EN_L); Q1<=( A)AND (NOT B) AND (NOT EN_L); Q2<=(NOT A)AND (B) AND (NOT EN_L); Q3<=(A)AND (B) AND (NOT EN_L); END dataflow;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSIONS: 1.2:4 decoder is realized in behavioural model of architecture. 2. The output waveform is also obtained.

EXPERIMENT 8 AIM: To design SR flip flop .

THEORY: The S-R flip flop of two additional AND gates at the S and R inputs of S-R latch. In the circuit,when the clock input is LOW, the output of both the AND gates are LOW and the changes in S and R inputs will not affect the output (Q) of the flip flop.when the clock input becomes HIGH, the value at S-R inputs will be passed to the output of the AND gates and the output (Q)of the flip flop will change according to the changes in S and R inputs as long as the clock input is HIGH. The truth table of S-R flip flop: Present State Qn

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Clock Pulse Data Inputs Next State CLK S R Qn+1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 1 0 1 0 1 0 0 0 1 1 1 0 1 ? ?

VHDL CODE DECODER: library IEEE; use IEEE.std_logic_1164.all; ENTITY srffl is PORT ( S,R: in std_logic ; Q,NQ:in out std_logic); End srffl; ARCHITECTURE srffl _arch of srffl is begin Q<=R nor NQ; NQ<=S nor Q; end;

Action

No change No change No change No change No change No change Reset Reset No change No change Set Set No change No change Forbidden Forbidden

RTL VIEW:

Clocked NOR-based S-R flip flop

NAND – based S-R flip flop

Graphic symbol

SIMULATION WAVEFORM:

CONCLUSIONS: 1.S-R flip flop is realized in behavioural model of architecture. 2. The output waveform is also obtained.

EXPERIMENT 9 AIM:

To design 2X4 decoder.

THEORY: Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is capable of representing up to 2 n distinct elements of coded information. A decoder is a combinational circuit that converts binary informational from n input lines to a maximum of 2n unique output lines. If the n-bit coded information has unused combinations, the decoder may have fewer than 2n outputs. The decoders presented here are called n-to-m-line decoders, where m ≤ 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder is also used in conjunction with other code converters such as a BCD-to-seven-segment decoder. The entity of the decoder with the truth table are as follows:

VHDL CODE DECODER WITH SELECT STATEMENT: library IEEE; use IEEE.std_logic_1164.all; ENTITY decoder IS PORT ( sel: IN BIT_VECTOR (2 downto 0); outZ: OUT BIT_VECTOR (7 downto 0)); END decoder; ARCHITECTURE single_delay OF decoder IS BEGIN WITH sel SELECT outZ <= "00000001" WHEN "000", "00000010" WHEN "001",

"00000100" WHEN "010", "00001000" WHEN "011", "00010000" WHEN "100", "00100000" WHEN "101", "01000000" WHEN "110", "10000000" WHEN "111"; END single_delay;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSIONS: 1.2:4 decoder is realized in behavioural model of architecture. 2. The output waveform is also obtained.

EXPERIMENT 10 AIM:

To design a Moorie and Mealy machine.

THEORY: The two basic types of sequential networks are Mealy and Moore. In a Mealy network, the output depends on both the present state and present inputs. In a Moore networks, the outputs depend only on the present state. A general model of a Mealy sequencial network consisrs of a combinational network, which generates the outputs and next state, and a state register, which holds the present state. The state register normally consists of D flip flops. The normal sequence of events is (1) and X inputs are changed to a new value, (2) after a delay, the corresponding Z outputs and next state appear at the output of the combinational network, and (3) the next state is clocked into the state register an dstate changes. The new state feed backs into the combinational network, and the process is repeated.

VHDL CODE MOORE MACHINE: library IEEE; use ieee.std_logic_1164.all; entity RWCNTL is port ( Clock: in std_logic; Start: in std_logic; Rw: in std_logic; Last: in std_logic; Rdsig: out std_logic; Wrsig: out std_logic; Done: out std_logic); end RWCNTL; architecture RTL of RWCNTL is type State_type is (idle, reading, writing, waiting); signal cur_state, next_state: State_type; begin process (cur_state, start, last, rw) begin Done <='0'; Rdsig <='0'; Wrsig <='0'; case cur_state is when idle=> if (start='0') then Next_state <=idle; elsif (rw='0') then

Next_state <=writing; else Next_state <=reading; end if; when writing=> Wrsig <='1'; if (last='0') then Next_state <=writing; else Next_state <=waiting; end if; when reading=> Rdsig <='1'; if (last='0') then Next_state <=reading; else Next_state <=waiting; end if; when waiting=> Done <='1'; Next_state <=idle; end case; end process; process begin wait until clock ‘event and clock=‘1’; Cur_state <=next_state;

end process; end router;

VHDL CODE MEALY MACHINE: library IEEE; use ieee.std_logic_1164.all; entity RWCNTL is port ( Clock: in std_logic; Reset: in std_logic; Start: in std_logic; Rw: in std_logic; Last: in std_logic; Rdsig: out std_logic; Wrsig: out std_logic; Done: out std_logic); end RWCNTL; architecture RTL of RWCNTL is type State_type is (idle, reading, writing, waiting); signal cur_state, next_state: State_type; begin process (cur_state, start, last, rw) begin Done <='0'; Rdsig <='0'; Wrsig <='0'; case cur_state is when idle=> if (start='0') then Next_state <=idle; elsif (rw='0') then Next_state <=writing; else Next_state <=reading;

end if; when writing=> Wrsig <='1'; if (last='0') then Next_state <=writing; else Next_state <=waiting; end if; when reading=> Rdsig <='1'; if (last='0') then Next_state <=reading; else Next_state <=waiting; end if; when waiting=> Done <='1'; Next_state <=idle; end case; end process; process (Clock, Reset) begin if (Reset=’1’) then Cur_state <= idle; elsif (clock ‘event and clock=‘1’) then Cur_state <=next_state; end if;

end process; end router;

RTL VIEW:

State Diagram of Moore Machine

Moore Machine with output decoded

State Diagram of Mealy Machine

Mealy Machine with output decoded.

SIMULATION WAVEFORM:

Moore Machine Waveform

Mealy Machine Waveform

CONCLUSIONS: 1.2:4 decoder is realized in behavioural model of architecture. 2. The output waveform is also obtained.

EXPERIMENT 11 AIM: To design a gray to binary and binay to gray counter.

THEORY: While designing modules with asynchronous clock transfers, one may encounter the problem of transferring multi-bit data bus from one clock domain to another. To dual synchronize these bits and hope that all the bits are latched on the same clock is problematic. To eliminate

this problem, we use Gray code counters where only one bit changes during each clock transition. The most common Gray code is where the lower half of the sequence is exactly the mirror image of first half with only the MSB inverted.

VHDL CODE GRAY TO BINARY: library IEEE; use IEEE.std_logic_1164.all; entity gray_to_binary is port(G3,G2,G1,G0:in std_logic; B:out std_logic_vector(0 to 3); end gray_to_binary ; architecture arch_gray_to_binary of gray_to_binary is begin B(3)<=G3; B(2)<=G3 xor G2; B(1)<=B(2) xor G1; B(0)<=B(1) xor G0; End;

VHDL CODE BINARY TO GRAY: library IEEE; use IEEE.std_logic_1164.all; entity binary_to_gray is port(B0,B1,B2,B3:in std_logic; G:out std_logic_vector(0 to 3); end binary_to_gray; architecture arch_ binary_to_gray of binary_to_gray is begin G(3)<=B3; G(2)<=B3 xor B2; G(1)<=B(2) xor B1; G(0)<=B(1) xor B0; End;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSIONS: 1.Code conversion is realized in behavioural model of architecture. 2. The output waveform is also obtained.

EXPERIMENT 12 AIM: To design a Decade counter.

THEORY:

Design a synchronous BCD counter that counts from 0000 to 1001. Use two 7476 ICs and one 7408 IC. Test the counter for the proper sequence. Determine whether it is self-starting. This is done by initializing the counter to each of the six unused states by means of the preset and clear inputs. The application of pulses must transfer the counter to one of the valid states if the counter is self-starting.

VHDL CODE FOR DECIMAL COUNTER: library IEEE; use IEEE.std_logic_1164.all;

entity deci_count is port(clk: in std_logic; ones: out integer range 0 to 8); end deci_count;

architecture arch_count of deci_count is begin p1: process (clk) variable temp: integer; begin temp := 0; if (clk = '1') then for i in 0 to 7 loop temp := temp + 1; end loop; end if; ones <= temp; end process p1;

end arch_count;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSIONS: 1.Decade counter is realized in behavioural model of architecture. 2. The output waveform is also obtained.