Intro 2

Lecture 3 Motivation for HDL and Levels of Hardware Abstraction

Motivation for HDL

• Requirements specification - First stage in design is the documentation of system requirements.

- System Requirements: function and performance - Formal technique via a HDL is desirable.

Motivation for HDL • Design documentation and communication - Due to increased design complexity, a large number of individuals are involved in design. - Formal specification via HDL facilitates easier and error free communication of design. - Formal documentation also aids in maintaining legacy systems.

Motivation for HDL

Facilitates structured designed methodologie - Aids in design partitioning in >> space (structural) >> time (functional) - Decreases complexity by supporting design abstraction.

- Supports black box approach with clear distinctio between functional and interface behavior

Motivation of HDL

• Design verification via simulation

- The initial requirements specification and actual design can both be simulated with same test stimuli.

- Comparison of the resulting outputs verifies the functionality of the design.

Motivation of HDL

• Design verification through formal technique

- A formal specification at both requirements and design level aids in formal verification.

- Formal verification refers to logically proving the equivalence of two specifications with out actua simulation. - This techniques saves time in comparison to simulation based technique.

Motivation for HDL

Automated synthesis through computer-aided design tools - Computer aided design tools automatically synthesize or generate the hardware from the requirement specification. - Automated synthesis reduces design time and eliminates errors due to manual design.

Motivation for HDL • Unifying Philosophy - Maximum reliability in design process at minimum cost and design time.

St ru Proc. Mem. Switch ct ur al

Fu n ct io n al

Traditional Hardware Levels of Abstraction Algorithm

Y-Chart

Geometric

Floorplan

HW Design Abstraction Functional

Structural P S M

loop for each data input ….. end; wait for 10 ms; end;

I/P O/P

Pad Frame I/P Geometric

P

S

M O/P

St ru Proc. Mem. Switch ct ur al RT

Fu n ct io n al

Traditional Hardware Levels of Abstraction Algorithm

RT Language

Y-Chart

Standard Cells

Geometric

Floorplan

HW Design Abstraction Structural

Control Section

IR

ALU GPR Temp PC MAR MDR

Functional MAR<- PC, Mem_rd <- 1 PC <- PC + 1 Wait until ready = 1 IR <- Mem_data Mem_rd <- 0

St ru Proc. Mem. Switch ct ur al RT Gate

Y-Chart

Transistor

Fu n ct io n al

Traditional Hardware Levels of Abstraction Algorithm

RT Language

Boolean Eqn or Truth Tab

Differential Eqn Polygons Sticks Standard Cells

Geometric

Floorplan

Standard Cells

“Principles of CMOS VLSI Design”, Weste and Eshragian

Standard Cell Symbolic Layout

Standard Cell Symbolic Layout

Actual Layout

Traditional Hardware Levels of Abstraction Algorithm

Proc. Mem. Switch

RT Language

RT Gate

Y-Chart

Transistor

Boolean Eqn or Truth Tab Differential Eqn Polygons Sticks Standard Cells Floorplan

Merging of 3-axis Algorithm or Behavioral Level Structure or Register Transfer (RT) Level Logic Gates Transistors

Levels of Design Abstraction

Digital System Design IDEA Behavioral Design Structural Design

Algorithm State machine,ALU,Regs

Logic Design Physical Design Fabrication

ASIC

Gate level netlist Transistor list

Digital System Design IDEA Behavioral Design Behavioral Simulation Structural Design Structural Simulation Logic Design Gate level Simulation Physical Design Device level Simulation Fabrication

ASIC

Testing

Digital System Design Specification at higher level of abstraction Translation or Design Specification at lower level of abstraction

Verification by Simulation

Digital System Design IDEA SystemC, Behavioral Design Celoxica HandelC Compiler, Forte SystemC Compiler Structural Design Logic Design Physical Design Fabrication

ASIC

VHDL, Xilinx ISE Foundation series

VHDL, Xilinx ISE Foundation series