Intro 1
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UNIT III INTRODUCTION TO VHDL
TOPICS TO BE COVERED • DIGITAL SYSTEM DESIGN HIERARCHY • DESIGN FLOW • TOP-DOWN & BOTTOM-UP DESIGN FLOW
al r e
en
G
m ab le
ra m og
FullCustom
p
r Pu
AM R S
Combinational
DR
X
DEVICE n+
p
n+
Bipolar August 2002
Maitham Shams
n+
n+
p MOSFET
C
R E G
hip
Ci
B
A
FA
Y OR EM
CMOS Inverter
IC
M
Parallel Connection
Copy Right
Mo de m
Dynamic
CIRCUIT Simple
hip
P
M U X
Basic
AL
AS S
Sequential
D Q
IT
r C
LOGIC GATE Static
∑
Co ntr oll e
Gate Arrays
MODULE
& AM
Pr
e os
ASIC
DECODER
M
e oc r op
PLD
CellBased om
icr
r
o ss
FPGA
t us iC m
W
O
F O
Se
D L R
DI G
SYSTEM
S
Co
Series Connection
n
Complex
p
Diode Dept of Electronics
Carleton University
Ottawa, CANADA
IC Design Steps Specifications
High-level Description
Structural Description
Behavioral VHDL, C
Structural VHDL
Figs. [©Sherwani]
IC Design Steps (cont.) Specifications
High-level Description
Physical Design Placed & Routed Design
Packaging
Technology Mapping
Gate-level Design
Fabrication
Structural Description
Synthesis
Logic Description X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani]
IC Design Steps (cont.) Specifications
High-level Description
Physical Design Placed & Routed Design
Packaging
Technology Mapping
Gate-level Design
Fabrication
Structural Description
Synthesis
Logic Description
The IC Design Methods Design Methods Full Custom Standard Cell Library Design ASIC – Standard Cell Design RTL-Level Design
Cost / Quality % Companies Development involved Time
Design abstraction levels High System Specification
Level of Abstraction
System
Functional Module
+
Gate
Circuit
Device Low
G S
D
TOPICS TO BE COVERED • DIGITAL SYSTEM DESIGN HIERARCHY • DESIGN FLOW • TOP-DOWN & BOTTOM-UP DESIGN FLOW
al r e
en
G
m ab le
ra m og
FullCustom
p
r Pu
AM R S
Combinational
DR
X
DEVICE n+
p
n+
Bipolar August 2002
Maitham Shams
n+
n+
p MOSFET
C
R E G
hip
Ci
B
A
FA
Y OR EM
CMOS Inverter
IC
M
Parallel Connection
Copy Right
Mo de m
Dynamic
CIRCUIT Simple
hip
P
M U X
Basic
AL
AS S
Sequential
D Q
IT
r C
LOGIC GATE Static
∑
Co ntr oll e
Gate Arrays
MODULE
& AM
Pr
e os
ASIC
DECODER
M
e oc r op
PLD
CellBased om
icr
r
o ss
FPGA
t us iC m
W
O
F O
Se
D L R
DI G
SYSTEM
S
Co
Series Connection
n
Complex
p
Diode Dept of Electronics
Carleton University
Ottawa, CANADA
IC Design Steps Specifications
High-level Description
Structural Description
Behavioral VHDL, C
Structural VHDL
Figs. [©Sherwani]
IC Design Steps (cont.) Specifications
High-level Description
Physical Design Placed & Routed Design
Packaging
Technology Mapping
Gate-level Design
Fabrication
Structural Description
Synthesis
Logic Description X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani]
IC Design Steps (cont.) Specifications
High-level Description
Physical Design Placed & Routed Design
Packaging
Technology Mapping
Gate-level Design
Fabrication
Structural Description
Synthesis
Logic Description
The IC Design Methods Design Methods Full Custom Standard Cell Library Design ASIC – Standard Cell Design RTL-Level Design
Cost / Quality % Companies Development involved Time
Design abstraction levels High System Specification
Level of Abstraction
System
Functional Module
+
Gate
Circuit
Device Low
G S
D
