How Mips Pipeline Works
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PCSrc
ID/EX
0 M u x 1
WB
Control
IF/ID
EX/MEM
M
WB
EX
M
MEM/WB WB
Add Add Add result
Instruction memory
ALUSrc
Read register 1
Read data 1 Read register 2 Registers Read Write data 2 register Write data
MemtoReg
Address
Branch
Shift left 2
MemWrite
PC
Instruction
RegWrite
4
Zero ALU
0 M u x 1
ALU result
Address Data memory
Read data
Write data Instruction 16 [15–0]
Instruction [20–16]
Instruction [15–11]
Sign extend
32
6
ALU control
0 M u x 1
ALUOp
RegDst
MemRead
1 M u x 0
ID/EX
0 M u x 1
WB
Control
IF/ID
EX/MEM
M
WB
EX
M
MEM/WB WB
Add Add Add result
Instruction memory
ALUSrc
Read register 1
Read data 1 Read register 2 Registers Read Write data 2 register Write data
MemtoReg
Address
Branch
Shift left 2
MemWrite
PC
Instruction
RegWrite
4
Zero ALU
0 M u x 1
ALU result
Address Data memory
Read data
Write data Instruction 16 [15–0]
Instruction [20–16]
Instruction [15–11]
Sign extend
32
6
ALU control
0 M u x 1
ALUOp
RegDst
MemRead
1 M u x 0
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