Hip 4081

HIP4081 80V/2.5A Peak, High Frequency Full Bridge FET Driver

November 1996

Features

Description

• Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations

The HIP4081 is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081 can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081 can switch at frequencies up to 1MHz andssssss is well suited to driving Voice Coil Motors, high-frequency Class D audio amplifiers, and power supplies.

• Bootstrap Supply Max Voltage to 95VDC • Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns • User-Programmable Dead Time • On-Chip Charge-Pump and Bootstrap Upper Bias Supplies

For example, the HIP4081 can drive medium voltage brush motors, and two HIP4081s can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability.

• DIS (Disable) Overrides Input Control • Input Logic Thresholds Compatible with 5V to 15V Logic Levels • Very Low Power Consumption

Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load.

Applications • Medium/Large Voice Coil Motors • Full Bridge Power Supplies

A similar part, the HIP4080, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching.

• Class D Audio Power Amplifiers • High Performance Motor Controls • Noise Cancellation Systems

See Application Note AN9325 for HIP4081, Intersil AnswerFAX, (407) 724-7800, document #99325. Intersil web home page: http://www.semi.intersil.com

• Battery Powered Vehicles • Peripherals • U.P.S.

Similar part HIP4081A includes undervoltage circuitry which does not require the circuitry shown in Figure 30 of this data sheet.

Ordering Information PART NUMBER

TEMP. RANGE (oC)

PKG. NUMBER

HIP4081IP

-40 to 85

20 Lead Plastic DIP

E20.3

HIP4081IB

-40 to 85

20 Lead Plastic SOIC

M20.3

PACKAGE

Pinout HIP4081 (PDIP, SOIC) TOP VIEW BHB

1

20

BHO

BHI

2

19

BHS

DIS

3

18

BLO

VSS

4

17

BLS

BLI

5

16

VDD

ALI

6

15

VCC

AHI

7

14

ALS

HDEL

8

13

ALO

LDEL

9

12

AHS

AHB 10

11

AHO

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1

File Number

3556.7

HIP4081 Application Block Diagram 80V

12V BHO BHS BHI

LOAD

BLO

BLI HIP4081 ALI

ALO AHS

AHI

AHO

GND

GND

Functional Block Diagram (1/2 HIP4081) HIGH VOLTAGE BUS ≤ 80VDC AHB 10 CHARGE PUMP

LEVEL SHIFT AND LATCH

DRIVER

7

CBS AHS

VDD 16 AHI

AHO 11

12 TURN-ON DELAY DBS

DIS

3 15

DRIVER ALI

6

TURN-ON DELAY

VCC

ALO 13 ALS 14

HDEL

8

LDEL

9

VSS

4

TO VDD (PIN 16)

2

CBF

+12VDC BIAS SUPPLY

HIP4081 Typical Application (PWM Mode Switching) 80V

1 BHB

BHO 20

12V

2 BHI

BHS 19

DIS

3 DIS

BLO 18

4 VSS

BLS 17

5 BLI

VDD 16

PWM INPUT

6 ALI

VCC 15

7 AHI

ALS 14

8 HDEL

ALO 13

9 LDEL

AHS 12

10 AHB

AHO 11

LOAD

12V

GND

-

TO OPTIONAL CURRENT CONTROLLER

+ 6V

GND

3

HIP4081 Absolute Maximum Ratings

Thermal Information

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +16V Voltage on ALO, BLO . . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All voltages are relative to pin 4, VSS, unless otherwise specified.

Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC (For SOIC - Lead Tips Only) Thermal Resistance, Junction-Ambient SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W

(Typical, Note 1)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air.

Operating Conditions Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . +6V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V

Electrical Specifications

Voltage on AHB, BHB . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA Operating Ambient Temperature Range . . . . . . . . . . .-40oC to 85oC

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified TJS = -40oC TO 125oC

TJ = 25oC PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP MAX MIN MAX UNITS

SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current

IDD

VDD Operating Current

IDDO

VCC Quiescent Current

ICC

VCC Operating Current

ICCO

AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current

IAHB, IBHB

All Inputs = 0V

7

9

11

6

12

mA

Outputs Switching f = 500kHz

8

9.5

12

7

13

mA

All Inputs = 0V, IALO = IBLO = 0

-

0.1

10

-

20

µA

f = 500kHz, No Load

1

1.25

2.0

0.8

3

mA

-50

-30

-15

-60

-10

µA

0.5

0.9

1.3

0.4

1.7

mA

-

0.02

1.0

-

10

µA

All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V

IAHBO, IBHBO f = 500kHz, No Load

AHS, BHS, AHB, BHB Leakage Current

IHLK

AHB-AHS, BHB-BHS Qpump Output Voltage

VAHS = VBHS = VAHB = VBHB = 95V

VAHB-VAHS VBHB-VBHS

IAHB = IAHB = 0, No Load

11.5

12.6

14.0

10.5

14.5

V

Low Level Input Voltage

VIL

Full Operating Conditions

-

-

1.0

-

0.8

V

High Level Input Voltage

VIH

Full Operating Conditions

2.5

-

-

2.7

-

V

-

35

-

-

-

mV

-75

-135

-65

µA

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS

Input Voltage Hysteresis Low Level Input Current

IIL

VIN = 0V, Full Operating Conditions

High Level Input Current

IIH

VIN = 5V, Full Operating Conditions

-130 -100 -1

-

+1

-10

+10

µA

4.9

5.1

5.3

4.8

5.4

V

TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage

VHDEL, VLDEL IHDEL = ILDEL = -100µA

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage

VOL

IOUT = 100mA

0.7

0.85

1.0

0.5

1.1

V

High Level Output Voltage

VCC -VOH

IOUT = -100mA

0.8

.95

1.1

0.5

1.2

V

4

HIP4081 Electrical Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) TJ = 25oC

PARAMETER

SYMBOL

TEST CONDITIONS

TJS = -40oC TO 125oC

MIN

TYP MAX MIN MAX UNITS

Peak Pullup Current

IO+

VOUT = 0V

1.7

2.6

3.8

1.4

4.1

A

Peak Pulldown Current

IO-

VOUT = 12V

1.7

2.4

3.3

1.3

3.6

A

Switching Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF TJS = 40oC TO 125oC

TJ = +25oC PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX UNITS

Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO)

TLPHL

-

30

60

-

80

ns

Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO)

THPHL

-

35

70

-

90

ns

Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO)

TLPLH

-

45

70

-

90

ns

Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO)

THPLH

-

60

90

-

110

ns

Rise Time

TR

-

10

25

-

35

ns

Fall Time

TF

-

10

25

-

35

ns

Turn-on Input Pulse Width

TPWIN-ON

50

-

-

50

-

ns

Turn-off Input Pulse Width

TPWIN-OFF

40

-

-

40

-

ns

Disable Turn-off Propagation Delay (DIS - Lower Outputs)

TDISLOW

-

45

75

-

95

ns

Disable Turn-off Propagation Delay (DIS - Upper Outputs)

TDISHIGH

-

55

85

-

105

ns

TDLPLH

-

35

70

-

90

ns

TREF-PW

160

260

380

140

420

ns

THEN

-

335

500

-

550

ns

Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO)

TRUTH TABLE INPUT

OUTPUT

ALI, BLI

AHI, BHI

DIS

ALO, BLO

AHO, BHO

X

X

1

0

0

1

X

0

1

0

0

1

0

0

1

0

0

0

0

0

NOTE: X signifies that input can be either a “1” or “0”.

5

HIP4081 Pin Descriptions PIN NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2

BHI

B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

3

DIS

Disable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.

4

VSS

Chip negative supply, generally will be ground.

5

BLI

B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven.

6

ALI

A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven.

7

AHI

A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

8

HDEL

High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.

9

LDEL

Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.

10

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

12

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.

13

ALO

A Low-side Output. Connect to gate of A Low-side power MOSFET.

14

ALS

A Low-side Source connection. Connect to source of A Low-side power MOSFET.

15

VCC

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.

16

VDD

Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

17

BLS

B Low-side Source connection. Connect to source of B Low-side power MOSFET.

18

BLO

B Low-side Output. Connect to gate of B Low-side power MOSFET.

19

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.

20

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

6

HIP4081 Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL

THPHL

DIS = 0 XLI

XHI

XLO

XHO

THPLH

TLPLH

FIGURE 1.

TR (10% - 90%)

INDEPENDENT MODE

DIS = 0 XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

FIGURE 2. BISTATE MODE

TDLPLH

DIS

TDIS TREF-PW

XLI

XHI

XLO

XHO THEN

FIGURE 3. DISABLE FUNCTION

7

TF (10% - 90%)

HIP4081 Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified 11.0 10.5

12.0

SUPPLY CURRENT (mA)

IDD SUPPLY CURRENT (mA)

14.0

10.0 8.0 6.0

10.0 9.5 9.0 8.5

4.0

8.0

2.0 6

8

10

12

14

0

100

200

VDD SUPPLY VOLTAGE (V)

400

500

600

700

800

900 1000

FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) 5.0

30.0

125oC ICC SUPPLY CURRENT (mA)

FLOATING SUPPLY BIAS CURRENT (mA)

FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE

25.0 20.0 15.0 10.0 5.0 0.0

75oC

4.0

25oC 0oC

3.0

-40oC 2.0

1.0

0.0 0

100

200

300

400

500

600

700

800

900 1000

0

100

200

300

400

500

600

700

800

900 1000

SWITCHING FREQUENCY (kHz)

SWITCHING FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF)

FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE

-90 1.8

LOW LEVEL INPUT CURRENT (µA)

FLOATING SUPPLY BIAS CURRENT (mA)

300

SWITCHING FREQUENCY (kHz)

1.4

1.0

0.6

0.2

200

400

600

800

-110

-120 -50

-0.2 0

-100

1000

-25

0

25

50

75

100

125

JUNCTION TEMPERATURE (oC)

SWITCHING FREQUENCY (kHz)

FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY CURRENT vs FREQUENCE

FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE

8

HIP4081 Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 80

PROPAGATION DELAY (ns)

NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)

15.0

14.0

13.0

12.0

11.0

10.0 -40

-20

0

20

40

60

80

100

70

60

50

40

30 -40

120

-20

0

FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE

60

80

100

120

80

PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

40

FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE

400

380

360

340

320

300 -40

70

60

50

40

30 -20

0

20

40

60

80

100

120

-40

-20

JUNCTION TEMPERATURE (oC)

FIGURE 12. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE

0

20 40 60 80 JUNCTION TEMPERATURE (oC)

100

120

FIGURE 13. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE

80

PROPAGATION DELAY (ns)

375 REFRESH PULSE WIDTH (ns)

20

JUNCTION TEMPERATURE (oC)

JUNCTION TEMPERATURE (oC)

325

275

225

70 60 50 40 30 20

175 -40

-20

0

20

40

60

80

100

120

-40

JUNCTION TEMPERATURE (oC)

-20

0

20

40

60

80

100

JUNCTION TEMPERATURE (oC)

FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE

FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE

9

120

HIP4081 Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,

80

80

70

70

PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)

60 50 40 30 20 -40

-20

0

20 40 60 80 JUNCTION TEMPERATURE (oC)

100

50 40 30 20 -40

120

FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE

-20

0

20 40 60 80 JUNCTION TEMPERATURE (oC)

80

80

70

70

60 50 40 30

120

60 50 40 30 20

20 -40

-20

0

20

40

60

80

100

120

-40

-20

0

JUNCTION TEMPERATURE (oC)

12.5

12.5

TURN-ON RISE TIME (ns)

13.5

11.5

10.5

9.5

-20

0

20 40 60 80 JUNCTION TEMPERATURE (oC)

40

60

80

100

120

FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE

13.5

8.5 -40

20

JUNCTION TEMPERATURE (oC)

FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE

GATE DRIVE FALL TIME (ns)

100

FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE

PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

60

100

11.5

10.5

9.5

8.5 -40

120

FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE

-20

0

20 40 60 80 JUNCTION TEMPERATURE (oC)

100

120

FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE

10

HIP4081 Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 1500

1250 5.5 VCC - VOH (mV)

HDEL, LDEL INPUT VOLTAGE (V)

6.0

5.0

1000 -40oC

750

0oC 500

25oC

4.5

75oC

250

125oC 4.0 -40

-20

0

20

40

60

80

100

0

120

6

8

JUNCTION TEMPERATURE (oC)

FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE

12

14

FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA

3.5

1500 GATE DRIVE SINK CURRENT (A)

-40oC 1250 0oC 1000 VOL (mV)

10

BIAS SUPPLY VOLTAGE (V)

750 500

25oC

250

75oC

3.0 2.5 2.0 1.5 1.0 0.5

125oC 0

0.0 6

8

10 12 BIAS SUPPLY VOLTAGE (V)

6

14

FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERTURE AT 100mA

8

9 10 11 12 13 VDD , VCC , VAHB , VBHB (V)

14

15

16

FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE

3.5

500 LOW VOLTAGE BIAS CURRENT (mA)

GATE DRIVE SINK CURRENT (A)

7

3.0 2.5 2.0 1.5 1.0 0.5 0.0 6

7

8

9

10

11

12

13

14

15

200

10,000pF

100

3,000pF

50

1,000pF

20

100pF

10 5 2 1 0.5 0.2 0.1

16

1

VDD , VCC , VAHB , VBHB (V)

2

5

10

20

50

100

200

500

1000

SWITCHING FREQUENCY (kHz)

FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE

FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE

11

HIP4081 Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 150

1000

120 200 DEAD-TIME (ns)

LEVEL-SHIFT CURRENT (µA)

500

100 50 20 10

80V

5

60V

90

60

30

40V

2

20V 1

0 1

2

5

10

20

50

100

200

10

500 1000

50

100

150

200

250

HDEL/LDEL RESISTANCE (kΩ)

SWITCHING FREQUENCY (kHz)

FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE

FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE

HI4081 Power-up Application Information The HIP4081 H-Bridge Driver IC requires external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up.

R1 15K

ENABLE R2 3.3K

The HIP4081 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the DIS pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 30. As the VDD /VCC supply ramps from zero up, the DIS voltage is below its input threshold of 1.7V due to the R1/R2 resistor divider. When VDD /VCC exceeds approximately 9V to 10V, DIS becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to DIS reaching its threshold level of 1.7V while VDD /VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low.

1 BHB

BHO 20

2 BHI

BHS 19

3 DIS

BLO 18

4 VSS

BLS 17

5 BLI

VDD 16

6 ALI

VCC 15

7 AHI

ALS 14

8 HDEL

ALO 13

9 LDEL 10 AHB

AHS 12 AHO 11

FIGURE 30A.

VDD

12V, FINAL VALUE 8.5V TO 10.5V (ASSUMES 5% RESISTORS)

ALI, BLI

DIS 1.7V

t1

NOTES: 2. ALI and/or BLI may be high after t1, whereupon the ENABLE pin may also be brought high. 3. Another product, HIP4081A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. FIGURE 30B. TIMING DIAGRAM FOR FIGURE 30A

12

IN2 IN1

POWER SECTION

+12V

B+ Q1

1

2

U2

R29

JMPR1

+ C6

JMPR5

CONTROL LOGIC SECTION

JMPR2

12

U2

4 V SS 5 OUT/BLI 6 IN+/ALI

IN+/ALI

CD4069UB JMPR4

2

13

CW CD4069UB

9 LDEL 10 AHB

R34 3

IN-/AHI

DD

3 L1 AO Q2 2

+12V

R23

L2

C1

1

BO C2

3

ALO 13 AHS 12

Q4 R24

AHO 11

2

1

3

CW

3

CR1

2 1

R22

VCC 15 ALS 14

7 IN-/AHI 8 HDEL R33

10

U2

BLS 17 16 V

2

1

1

C3 CX

CY

R30

R31

C5 ENABLE IN I R32

3

U2

4

ALS

15K

9

U2

8

COM

O

CD4069UB

HIP4081

11

Q3

3

C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18

OUT/BLI

JMPR3 HEN/BHI

6

U2

C8

U1

CD4069UB 5

CR2

2

1

HIP4080/81

CD4069UB 13

R21

DRIVER SECTION

BLS

TO DIS PIN 3.3K O

CD4069UB

NOTES: 4. Device CD4069UB PIN 7 = COM, Pin 14 = +12V. 5. Components L1, L2, C1, C2, CX, CY, R30, R31, not supplied. refer to Application Note for description of input logic operation to determine jumper locations for JMPR1 - JMPR4. FIGURE 31. HIP4081 EVALUATION BOARD SCHEMATIC

C1

R26

COM

C8 C6

R28

R27

B+

CR2

AO

+

R32

+

JMPR5

+12V

C7

R29

GND

Q1 C4 BHO

U1

Q3

1

R22

1

ALS ALO

Q4

1

1

R21 LDEL

CY

CX

FIGURE 32. HIP4081 EVALUATION BOARD SILKSCREEN

R31

R34

R30

CR1 R33

BLS

C3 C5

ALS

L2

C2 Q2

R23

AHO

O HDEL

14

O IN2

BO

HIP4081

JMPR1 JMPR2 JMPR3 JMPR4

I

BLO BLS

L1

IN1

HIP4080/81

R24 DIS

U2

HIP4081 Supplemental Information for HIP4080 and HIP4081 Power Application

level of 1.7V while VDD/VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low.

The HIP4080 and HIP4081 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shootthrough current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up.

HIP4080 The HIP4080 does not have an input protocol like the HIP4081 that keeps both lower power MOSFETs off other than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming DIS is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 34. Pulling LDEL to VDD will indefinitely delay the lower turn-on delays through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e., DIS = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure 33.

HIP4081 The HIP4081 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the DIS pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 33. As the VDD/VCC supply ramps from zero up, the DIS voltage is below its input threshold of 1.7V due to the R1/R2 resistor divider. When VDD/VCC exceeds approximately 9V to 10V, DIS becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to DIS reaching its threshold

R1 15K

ENABLE R2 3.3K

ENABLE

1 BHB

BHO 20

2 BHI

BHS 19

3 DIS

BLO 18

4 VSS

BLS 17

5 BLI

VDD 16

6 ALI

VCC 15

6 ALI

VCC 15

7 AHI

ALS 14

7 AHI

ALS 14

8 HDEL

ALO 13

8 HDEL

ALO 13

9 LDEL

AHS 12

9 LDEL

10 AHB

R1 15K

R2 3.3K

AHO 11

1 BHB

BHO 20

2 BHI

BHS 19

3 DIS

BLO 18

4 VSS

BLS 17

5 BLI

VDD 16

AHS 12

10 AHB

AHO 11

1 BHB

BHO 20

FIGURE 33.

VDD

VDD

ENABLE 56K 2N3906 56K 8.2V

VDD 100K

RDEL

100K 0.1µF

FIGURE 34.

15

RDEL

2 HEN

BHS 19

3 DIS

BLO 18

4 VSS

BLS 17

5 OUT

VDD 16

6 IN+

VCC 15

7 IN-

ALS 14

8 HDEL

ALO 13

9 LDEL

AHS 12

10 AHB

AHO 11

HIP4081 Timing Diagrams VDD

12V, FINAL VALUE 8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)

VDD

12V, FINAL VALUE DIS

8.5V TO 10.5V (ASSUMES 5% RESISTORS) ALI, BLI

LDEL 5.1V

DIS t1

1.7V

NOTE:

=10ms

t2

NOTE:

6. ALI and/or BLI may be high after t1, whereupon the ENABLE pin may also be brought high.

7. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the undervoltage circuit is satisfied, the ENABLE pin will initiate the 10ms time delay during which the IN+ and IN- pins must cycle at least once.

FIGURE 35.

FIGURE 36.

16

HIP4081 Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D)

N

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1 INDEX AREA

1 2 3

INCHES

N/2 -B-

-AE

D BASE PLANE

A2

-C-

SEATING PLANE

A L

D1

e

B1

D1

B 0.010 (0.25) M

A1

eC C A B S

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

-

0.210

-

5.33

4

A1

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

B

0.014

0.022

0.356

0.558

-

C L

B1

0.045

0.070

1.55

1.77

8

eA

C

0.008

0.014

D

0.980

1.060

D1

0.005

-

0.13

-

5

E

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

C

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

e

2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

0.100 BSC

eA

0.300 BSC

eB

-

L

0.115

N

0.204

20

0.355

24.89

26.9

2.54 BSC 7.62 BSC

0.430

-

0.150

2.93 20

5

6

10.92

7

3.81

4 9 Rev. 0 12/93

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

17

HIP4081 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

N INDEX AREA

H

0.25(0.010) M

B M

INCHES

E -B1

2

3

L SEATING PLANE

-A-

h x 45o

A

D -C-

e

A1

B 0.25(0.010) M

C 0.10(0.004)

C A M

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

0.0926

0.1043

2.35

2.65

-

A1

0.0040

0.0118

0.10

0.30

-

B

0.013

0.0200

0.33

0.51

9

C

0.0091

0.0125

0.23

0.32

-

D

0.4961

0.5118

12.60

13.00

3

E

0.2914

0.2992

7.40

7.60

4

e

α

B S

0.050 BSC

1.27 BSC

-

H

0.394

0.419

10.00

10.65

-

h

0.010

0.029

0.25

0.75

5

L

0.016

0.050

0.40

1.27

6

N

α

NOTES:

MILLIMETERS

20 0o

20 8o

0o

7 8o

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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18

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