Fullreport

PROFESSOR ASSISTANCE SYSTEM USING GSM Project submitted in partial fulfillment of requirements For the Degree of

BACHELOR OF ENGINEERING BY GAURAV A SHETYE SIDDHARTH CHAUDHARY

Under the SAWANT guidance SIDDHARTH

of

SWAPNIL ANGANE

PROF. SUKANYA KULKARNI Internal Guide

Department of Electronics and Telecommunications Engineering Sardar Patel Institute of Technology University of Mumbai 2008-2009

BHARTIYA VIDYA BHAVAN’S SARDAR PATEL INSTITUTE OF TECHNOLOGY MUNSHI NAGAR, ANDHERI (W), MUMBAI - 400 058. 2008-09

CERTIFICATE OF APPROVAL This is to certify that the following students GAURAV A SHETYE SIDDHARTH CHAUDHARY SIDDHARTH SAWANT SWAPNIL ANGANE

have successfully completed and submitted the project entitled

PROFESSOR ASSISTANCE SYSTEM USING GSM Towards the fulfillment of Bachelor of Engineering course in Electronics and Telecommunications of the Mumbai University.

_________________

_________________

Internal Examiner

External Examiner

_______________

Internal Guide

_______________

_________________

Head of Department

Principal

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

ABSTRACT Now a days, most of the systems are automated in order to face new challenges and present day TABLE OF CONTENTS requirements to achieve good results. Automated systems have less manual operations, so that the flexibility, reliabilities are high and accurate. Hence every field prefers automated control systems, especially in the field of electronics. Wireless and mobile communications is one of the fastest growing areas of modern life. It has an enormous impact on almost every aspect of our daily lives. Our project is concerned with the interface of a GSM modem with 8-bit Philips Microcontroller P89V51RD2 to send SMS to predetermined locations .Operation of the GSM modem, circuit techniques and development of embedded software for wireless communications are the focus of this report. Operation of the GSM automation board runs via a serial interface by the specific AT commands.The status of the system can be requested via SMS. The system can also be programmed to send specific SMS to predetermined number if any event or condition triggered.

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

Introduction Our project mainly deals with interfacing of microcontroller and gsm modem.using this interface we are going to demonstrate following tasks. •

Intimate the faculty about their current lecture via SMS prior to every lecture.

•

Reply to a professor his schedule for the day in response to a blank SMS to the system.

•

Assist the professor in taking feedback from the students at the end of semester.

•

Disallow unauthorized users to access the time-table data base in case they are not registered thus ensuring security.

HARDWARE DESCRIPTION A. Block Diagram and Description: 0100090000037400000002001c00000000000400000003010800050000000b0200000000050000000c026704b d06040000002e0118001c000000fb02ceff0000000000009001000000000440001254696d6573204e657720526f 6d616e0000000000000000000000000000000000040000002d010000040000000201010005000000090200000 0020d000000320a2c00ffff0100040000000000bd06650420bc16001c000000fb021000070000000000bc020000 00000102022253797374656d000000000000000000001800000001000000f0fd5105e4040000040000002d0101 00030000000000 Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

BLOCK DIAGRAM DESCRIPTION:  MICRO-CONTROLLER: THE DATA IN THE CODED FORM IS FED INTO THE IC 89V51RB2.IT CAN BE REPROGRAMMED AS AND WHEN REQIURED.THE KEY FEATURES OF THIS IC ARE THE X2 MODE OPTION AND THE FLASH MEMORY WHICH SUPPORTS BOTH PARALLEL PROGRAMMING AND IN SERIAL ISP.  GSM MODEM: IT CAN BE PROGRAMMED USING A PC AND IS CONNECTED TO THE MICRO-CONTROLLER. IT IS USED TO SEND AND RECEIVE SMS.NOKIA 3310 IS USED FOR THIS PURPOSE.  REAL TIME CLOCK: THE DS1307 IS A SERIES REAL TIME CLOCK WHOSE COUNT IS INCREMENTED IN A 12/24 HR FORMAT WITH THE AM OR PM INDICATOR.ADDRESS AND DATA ARE TRANSFERRED SERIALLY THROUGH THE BIDIRECTIONAL I^2 C BUS.  POWER SUPPLY MODULE: IT IS USED TO SUPPLY THE REQUIRED VOLTAGES TO DIFFERENT PARTS OF THE CIRCUIT.

Controller P89V51RD2: As it say 89V51RD2 having architecture same as 8051 it is 8-bit controller. 8051 architecture is Harvard architecture. Unlike microcontrollers with Von Neumann architectures, which can use a single memory address for either program code or data, but not for both, the 8051 uses the same address, in different memories, for code and data. Some of 8051 features are; 

8-bit CPU with registers A and B



Sixteen-bit program counter and data pointer



8-bit program status word



8-bit stack pointer



Internal ROM or EPROM (8751) of 4K



Internal RAM of 128 bytes:



4 register bank containing 8 registers each



16 bytes that can be addressed at bit level



80 bytes of general-purpose data memory



32 input/output pins arranged as four 8-bit ports: P0,P1,P2,P3



Two 16 bit timer/counter: T0 and T1 In 89V51RD2 there are some modifications in these features. The P89V51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM. Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

A key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency. The Flash program memory supports both parallel programming and in serial In-System Programming (ISP). Parallel programming mode offers high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running. 

80C51 Central Processing Unit



5 V Operating voltage from 0 to 40 MHz



64 kB of on-chip Flash program memory with ISP (In-System Programming) and



IAP (In-Application Programming)



Supports 12-clock (default) or 6-clock mode selection via software or ISP



Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)



Three 16-bit timers/counters



Eight interrupt sources with four priority levels



Second DPTR register



TTL- and CMOS-compatible logic levels Variations: 1. P89V51RD2FA PLCC44 plastic leaded chip carrier; 44 leads 2. P89V51RD2FBC TQFP44 plastic thin quad flat package; 44 leads 3. P89V51RD2BN PDIP40 plastic dual in-line package; 40 leads



P89V51RD2FA 40 *C to +85 *C−-



P89V51RD2FBC - 40 *C to +85 *C−



P89V51RD2BN 0 *C to +70 *C This is pin diagram for 89V51RD2 having 40 pin DIP.

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

Pin functions

Port 0.1-7 pin 39-32: Port 0 is an 8-bit open drain bi-directional I/O port. Port 0 pins that have ‘1’s written to them float, and in this state can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when transitioning to ‘1’s. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification or as a general purpose I/O port. Port 1.0-7 pins 1-8: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 pins are pulled high by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. P1.5, P1.6, P1.7 have high current drive of 16 mA. Port 1 also receives the low-order address bytes during the external host mode programming and verification. T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2. Pin Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

1.0 There are some more functions of port1 pins alternatively for use in PCA which is additional here in RV2. But is not useful here in our application. Port 2.0-7 pins 21-28: Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins are pulled HIGH by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to ‘1’s. Port 2 also receives some control signals and a partial of highorder address bits during the external host mode programming and verification. Port 3.0-7 pins 10-17: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins are pulled HIGH by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. Port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. 

RXD: serial input port



TXD: serial output port



INT0: external interrupt 0 input



INT1: external interrupt 1 input



T0: external count input to Timer/Counter 0

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T1: external count input to Timer/Counter 1

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WR: external data memory write strobe



RD: external data memory read strobe

Program Store Enable PSEN active low pin 29: PSEN is the read strobe for external program memory. When the device is executing from internal program memory, PSEN is inactive (HIGH). When the device is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. A forced HIGH-to-LOW input transition on the PSEN pin while the RST input is continually held HIGH for more than 10 machine cycles will cause the device to enter external host mode programming. Reset pin 9: While the oscillator is running, a HIGH logic state on this pin for two machine cycles will reset the device. If the PSEN pin is driven by a HIGH-to-LOW input transition while the RST input pin is held HIGH, the device will enter the external host mode, otherwise the device will enter the normal operation mode.

External Access Enable pin 31 active low: EA must be connected to VSS in order to enable the device to fetch code from the external program memory. EA must be Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

strapped to VDD for internal program execution. However, Security lock level 4 will disable EA, and program execution is only possible from internal program memory. The EA pin can tolerate a high voltage of 12 V. Address Latch Enable pin 30: ALE is the output signal for latching the low byte of the address during an access to external memory. Crystal 1 pin 19: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2 pin 18: Output from the inverting oscillator amplifier. Power supply Vdd pin 40 Ground pin 20 In-System Programming (ISP): In-System Programming is performed without removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89V51RD2 through the serial port. This firmware is provided by Philips and embedded within each P89V51RD2 device. The Philips In-System Programming facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TxD, RxD, and RST). Only a small connector needs to be available to

RS 232 Description: It provides the interface between the data terminal equipment and the data communications equipment using serial binary data exchange. This defines the DTE as the computer while the DCE as Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

the MODEM. It presupposes a common ground between the DTE and the DCE.It is mainly used for single ended data communication between elements. It overcomes the noise problems prevalent in the direct communication of the GSM modem with the micro-controller. It uses the asynchronous mode of serial transmission: first the start bit is sent, then the data bits. This is followed by parity bits to detect errors and finally the stop bit is sent.

RS 232 pin diagram:

Working: The data carrier detect pin is used to check whether a good carrier is being received or not. The sending and receiving data pins are used to send and receive data. The data terminal ready is a signal fro the computer that it is on. The data set ready is an indication from the modem that it is on. Pin 5 is signal ground which is used as ground terminal. When the DTE wants to transmit data , it makes the RTS high. The modem turns on the carrier and raises the CTS. The DTE transmits data and after finishing drops the RTS and the modem drops the CTS.

RS 232 SIGNALS:

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

RS 232 signals are represented by two voltage levels with respect to common ground. The first is the “idle” state (MARK) which is negative and the second is the “active” state (SPACE) which is positive. RS 232 data is bipolar.+3 to +12 indicates space condition whereas -3 to -12 indicates mark condition. Output swings between +12 to -12.The dead area between +3 to -3 is used to absorb the line noise . It has numerous handshaking signals and also specifies a communications protocol.

REAL TIME CLOCK Features: 1. RTC counts seconds, minutes, hours, date of the month, month,day of the year and leap year with compensation valid upto 2100. 2. It has 56 bytes of battery backed non volatile RAM for data storage. 3. It uses the I2 bus for data interface. 4. It has programmable square wave output signal. 5. It has automatic power failure detection and switching circuitry. 6. It consumes less than 500 nA in battery backup mode with oscillator running. 7. It is available in 8 pin DIP package or SO.

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

Pin Description: 1. X1 and X2: It is used for connecting the standard 32.768 Khz crystal. X1 is the input to the oscillator and can be connected to external 32.768 Khz oscillator.The output of oscillator X2 is floated if input is connected to X1. 2. VBAT: Battery voltage must be within min and maximum limits for proper operation. Diode in series between battery and VBAT pin may prevent proper operation.If battery back up is not required VBAT must be grounded. The nominal power fail trip point (VPF) at which acesss to the RTC and the user RAM is denied is set by the internal circuitry as 1.25*VBAT nominal.Alithium battery with 48 mAhr or greater will back up DS1307 for more than 10 years in the absence of power at 25 degree Celsius. 3. Ground : It is used as common ground terminal. 4. SDA: The Serial Data Input/Output pin is used for the I2c serial interface.It is open drain and requires an external pull up resistor. 5. SCL: It is the Serial Clock Interface and is used to synchronize data movement on the serial interface. 6. SWQ/OUT: It is the square wave output driver.When enabled SQWE bit is set to 1 and SWQ

outputs one of the square wave frequencies (1 Khz,8 Khz,16 Khz and 32 Khz).It is open drain and requires an external pull up resistor.It operates either with VCC or VBAT applied. 7. VCC: It is the primary power supply.When voltage is applied within normal limits,device is fully accessible and data can be read and written. When a back up supply is connected to the device and VCC is below VTP, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage.

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

I2C BUS The DS 1307 supports the I2C protocol. The device that sends data is called as the transmitter,the device receiving data is called as the receiver, the device that controls the message is called as the master and the devices that are controlled by the master are referred to as the slaves. The bus must be controlled by a master device that generates the serial clock, controls the bus access and generates the START and STOP conditions. The DS 1307 operates as a slave on the I2C bus. • •

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line when the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been identified:  NOT BUSY: Both the clock and data lines remain high.  START TRANSFER: A change in the state of the data line from high to low while the clock line is high defines the START condition.  STOP TRANSFER: A change in the state of the data line from low to high while the clock line is high defines the STOP condition.  DATA VALID: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.The information is transmitted byte wise and each receiver acknowledges with a ninth bit.  ACKNOWLEDGE: Each receiving device is obliged to generate an acknowledge. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse.A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

Depending upon the state of the R/W bit, two types of data transfer are possible:  Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first.  Data transfer from a slave transmitter to a master receiver: The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first.

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

Sardar Patel Institute Of Technology

Professor Assistance System Using GSM

Sardar Patel Institute Of Technology