Flash Part

Flash Part LPC - Low Pin Count FWH - Firmware Hub SPI - Serial Peripheral Interface Interfaces LPC  Enable a system without an ISA or X-bus  Support new Firmware Memory cycle type allowing separate boot BIOS firmware memory cycles and application memory cycles  Software transparency: don’t require special drivers or configuration for this interface. The motherboard BIOS should be able to configure all devices at boot.  Ability to have I/O and memory cycles retried in SMM handler.  BIOS Firmware Memory => Firmware Memory Slave

FWH  The Intel FWH interface is designed to work with the Intel family of I/O Controller Hubs (ICH) during platform operation.  The device operates under the LPC/FWH interface/protocol.  Hardware Features - Random Number Generator (RNG) - Five General-Purpose Inputs (GPIs) - Register-based Block Locking - Hardware-based Locking  Enable better protection for storage and update of platform code and data  Add platform flexibility through additional GPIs  A non-volatile memory core based on Intel Flash Technology. - Fast Factory Programming and Low-Power Designs.  The Intel FWH interface is designed to use an LPC-compatible start cycle, with a reserved cycle type code.

SPI    

  







An industry standard serial flash interface or SPI specification has not been identified. Cost-effective flash solution for PC-based products - Low Cost, Small Size, Fewer Pins The ICH chipset will provide a mechanism to route access either to LPC or SPI after the system has booted. The strap is sampled at boot time to boot from SPI flash or LPC, and cannot be changed dynamically when the system is operated. SPI flash is required to use advanced features of chipset such as integrated GbE, Intel AMT, AFSC and ASF. Non-Descriptor Mode can only be used by BIOS. Descriptor Mode - ICH will look for a descriptor on the SPI flash device on Chip Select 0. It will load up the descriptor into corresponding registers in the ICH. - It is recommended to put BIOS at the top of flash on single SPI flash platforms so even if the descriptor gets corrupted, the system will still be bootable. Host Vendor Specific Component Control - LVSCC and UVSCC are memory mapped registered are used by the ICH9 when BIOS or Integrated LAN read, programs or erases the SPI flash via Hardware sequencing. Hardware Sequencing - A predefined list of opcodes with only the erase opcode being programmable. Software Sequencing - BIOS has to enter in a table of all possible opcodes and define how hardware should behave with each opcode

SPI Write Protect * SST SPI Flash chip The Write Protect (WP#) pin enables the lock-down function of the Block-Protect-Lock (BPL) bit in the status register.

The Write-Status-Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. SPI raw Read/Write command * SPI Read 1. initial SPI Flash Data 0 Register (ICH8 : SPIBAR + 10h) 2. initial SPI Flash Address Register (ICH8 : SPIBAR + 8h) 3. initial Software Sequencing Flash Control Register (SPIBAR +91h) * BIT[8..13] Data Byte Count * BIT[4..6] Cycle Opcode Pointer (Opcode Read Index) * BIT[14] Data Cycle 4. Wait for Cycle Done 5. Read Data from SPI Flash Data 0 Register * SPI Write 1. initial Opcode Menu Configuration Register (ICH8 : SPIBAR + 98h) 2. initial SPI Flash Data 0 Register (ICH8 : SPIBAR + 10h) 3. initial SPI Flash Address Register (ICH8 : SPIBAR + 8h) 4. initial Software Sequencing Flash Control Register (SPIBAR +91h) * BIT[1] Cycle Go * BIT[2] Atomic Cycle Sequence * BIT[4..6] Cycle Opcode Pointer (Opcode Write Index) 5. Wait for Cycle Done

Definition of Terms JEDEC – Joint Electronic Device Engineering Council

References  Low Pin Count Interface Specification http://www.intel.com/design/chipsets/industry/25128901.pdf  Intel 82802AB/82802AC Firmware Hub (FWH) http://download.intel.com/design/chipsets/datashts/29065804. pdf  Firmware Hub to SPI Flash Conversion http://download.intel.com/design/intarch/applnots/320572.pdf