Exercise Solution) 2

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COMPTER ORGANIZATION AND ARCHITECTURE (All Sections) MIDTERM 2 (WEDNESDAY, APRIL 25, 2007) COMPUTER ARITHMATIC, INSTRUCTION SETS, REGISTERS, PIPLINING SOLUTION Question 1 (10 points): All All of the following questions carry 2 point and no partial credit for these questions. Please provide a single line explanation for you answers even if you have to state the obvious. Otherwise you will get a 0. i.

What is the difference between General Purpose Registers (GPR) and Special Purpose Registers (SPR)? GPR are for general use, user visible and needs to have address bits in the machine code. SPR are special purpose, do not need explicit address bits and may be user visible or not

ii. What is the difference between a floating point number and a fixed point number? A floating number has an exponent part via which it floats whereas Fixed point as the name says is fixed and no exponent iii. What is difference between a pre-indexing and post-indexing addressing mode? Indexing  Indirection VS Indirection  Indexing iv. If a microprocessor does not have an Accumulator register, can it still work? Yes, it can use any of the general purpose registers but will need to use explicit address bits. v. Why it is better to follow orthogonality principal for an instruction set? That provides completeness via making the whole Op code useable for operation coding

Question 2 (20 points): Computer Arithmetic a. Check if overflow occurs after addition of following 2’s compliment signed 16-bit numbers. Perform all the necessary calculations. (7 points) Principal: if one number is already big enough then any number added with the same sign will cause an overflow e.g. to FFFF add any number (other than 0) and it will cause an overflow. • -12345 and -54321 - Overflow

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12345 and 54321 - Overflow 12345 and -54321 – no Overflow

b. Convert following IEEE 754 double precision numbers to their equivalent decimal value. (7 points) – This is a binary number represented using Hex. • 40F0000000000000h = 0100 0000 11110 (13*4 zeros) = 1.0 x 2100 0000 1111 - 1111111111 = 1 x 21000 = 65536 • 413F424000000000h = 0100 0001 0011 1111 0100 0010 0100 (9*4 zeros) = 1. 1111 0100 0010 01 x 210000010011- 1111111111 = 1. 1111 0100 0010 01 x 210100 = (approx) 1.11 x 210100 = (Approx) 1835008 c. Express the following numbers in IEEE 32 bit floating point format. (6 points) • -1/64 = -1 x 2-110 = 1 (11111111-110) 1 (22 zeroes) = 1 01111001 00000000000000000000000 • -2.625 = 2 + 5/8 = 10 + 101 x 2-11 = 10101 x 2-11 = 1 (11111111-11) 10101 (18 zeroes) = 1 01111100 01010000000000000000000

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Question 3 (20 points): Instruction Sets – Addressing Modes For the following instructions assuming that 1st operand is destination fill in values in the blank (shaded) cells in the following table. 00004100 = 00005100; 00004105 = 0000000A; 00004150 = 00000003; 00004200= 00000002; 00004206= 0000000A; 0000420D = 00000006; 00005100 = 00000006; 0000E100 = 00004100; 0000E106= 00004200; R2= 00004105; R3=00000005; PC= 00004000; SP = FFFFABCD; FFFFABCD = 00000008;

Address

Instruction

2100

Load R1, 4100

2101

MPY 4150,(E100)R1

2102

ADD 200,0001

2103

SUB R1( E106), R2

Register Indirect

2104

Pop 300

Stack

2105

ADD

Indexing

2106

Push R3(E100)

2107

DIV R2,0002;

2108

ADD R1, R2(3)

R2,R1(E100)

Source Addressing Mode Indirect

Destination Addressing Mode Register

Source Effective Address (4100)

Destination Effective Address R1

Contents of Destination

PreIndexing Immediate

Direct

(E100 + (R1)) = (E106) = 4200 NA

4150

4105

(E106) + (R1) = 4206

Relative addressing

SP = FFFFABCD

4300

Register Indirect

E100+(R1) = E106

4105

4105

FFFFABCD

(4200)*(4150 ) = 2*3 =6 (4200)+0001 = 03 (4206) (4105) = A-A =0 ( FFFFABCD) =8 (4105)+(E10 6) = A + 4200 = 420A (4105) = A

NA

(R2) = 4105

(R2) + 3 = 4108

R1

Post Indexing Immediate Base Register

Relative to PC Post-Indexing

Stack Register Indirect Register

4200

06

(4105)/2 = A/2 = 5 (R1) + (4105)

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Question 4 (20 points): Instruction Sets – Instruction Format, Registers Following table shows machine code for data move and add instructions of a microprocessor, the only user visible SPR (Special Purpose Register) is Program Counter - PC: No. 1 2 3 4 5 5 6 7

Instruction mnemonics MOVE R1,(A10) MOVE R1,R2,#5 MOVE R1,R2,#A10 MOVE R1,R2 STORE R1, (B10) ADD R1,#55 ADD R1,R2 ADD R1,R2,R3

Machine code (hex)

Meaning

FF 0 01 A10 FF 1 01 02 5 FF 1 01 02 A10 FF 3 01 02 FE 0 01 B10 AA 2 01 55 AA 6 01 02 AA 7 01 02 03

R1  (A10) R1  ((R2) + 5) R1  (A10 + (R2)) R1  R2 R1  (B10) R1  R1 + 55 R1  R1+R2 R1  R2+R3

Now answers the following: i.

What is the optimal length of for the instruction This is a fixed length instruction therefore look at the largest instruction from the table. The largest Instruction is 10 Hex numbers (No. 3) = 40 bits.

ii.

Does this follow orthogonality? If yes then how many mode bits and for what purpose (coding) Yes, because op codes for all MOVE and ADD are the same. One Hex number is used for the mode but that hex number is from 0-7. Therefore mode bits can be 3 or 4. In case of 3 mode bits the use is for identification of Addressing Modes.

iii.

How many GPRs (general purpose registers) does this microprocessor have? The Machine code for any register instruction contains 01 for R1, 02 for R2 and so on therefore either 2 hex numbers are used for a GPR address or one hex. In case of one hex # of GPRS = 28

iv.

How many addressing modes are supported? Due to 3 mode bits max Addressing modes supported are 28 (not all the modes are shown in the table above). OR simply count addressing modes in the table.

v.

What is the size of directly accessible memory? Max size of instruction = 40 bits; 8 bits are for op code, 3 for mode, 8 bits are needed for a GRPS address  bits available for direct addressing = 40 – 8 – 3 - 8 = 21 bits. How many maximum operations this microprocessor supports? Op code = 8 bits therefore 28 max operations.

vi.

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Is this has fixed instruction length or variable? The instruction length is fixed because there are no mode bits to determine a particular length.

viii.

In the above table entry 1, can you replace R1 with some SPR to increase directly accessible memory? Yes, PC (the only SPR available) can be used in the relative mode

ix.

What SPRS will you add and why? AC will be a good choice so that more direct bits become available for other addressing modes. IX can also be added to provide help for indexing mode.

x.

What is the word size for this microprocessor? Word size = optimal instruction length = 40 bits

Question 5 (20 Points):Pipeline The 6 basic stages for instruction fetch and execute are: Fetch Instruction (FI), Decode Instruction (DI), Calculate Operands (CO), Fetch Operands (FO), Write Operand (WO) TABLE A1: TABLE A2: No. Address Instruction Meaning I1 F000 MOVE R1,(A100) R1  (A100) I2 F001 MOVE R2, (B100) R2  (B100) I3 F002 ADD R3, R1, R2 R3  R1+R2 Address Data I4 F003 SUB R4,R1,R2 R4  R1-R2 A100 5 I5 F004 DIV R5,R3,R4 R5  R3/R4 B100 A I6 F005 STORE R5,(B100) R5  (B100)

a. Above table A1 shows 6 instructions and Table A2 shows data values for some locations, please fill the following pipeline table B to execute these instructions. Please watch out for the data dependency and if certain instruction do not need an stage then skip it i.e. if WO stages is not needed then do not use it.

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TABEL B: (only one instruction can be in one stage at a time) TIME FI DI CO FO EI WO 1 I1 2 I2 I1 3 I3 I2 I1 4 I4 I3 I2 I1 5 I5 I4 I3 I2 I1 6 I5 I4 I3 I2 I1 7 I5 I4 I3 I2 8 I6 I5 I4 I3 9 I6 I5 I4 I3 10 I6 I5 I4 I3 11 I6 I5 I4 12 I6 I5 13 I6 I5 14 I6 I5 15 I6 16 I6 Shaded areas are due to data dependencies.

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No.

b. Address

Instruction

Meaning

I3 I4 I5 I6 I7 I8 I9

F002 F003 F004 F005 F006 F007 F009

ADD R3, R1, R2 SUB R4,R1,R2 JZ F002 ADD R5,R3,R4 JC FF03 SUB R6,R5,R1 JN FF05

R3  R1+R2 R4  R1-R2 Jump on Zero

NOT TAKEN

Jump on carry

TAKEN

Jump on Negative

TAKEN

I10 I11

F00A F00B

MUL R7,R1,R2 JO FF07

NOT TAKEN

I12 I13

F00C F00D

JUMP F002 STORE R7,(B100)

Jump on Overflow PC  F002 R5  (B100)

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JUMP RESULT

FF03 JUMP F007 PC  F007 FF05 JUMP F00A PC  F00A FF07 JUMP F002 PC  F002 Fill the following branch history table for the above code for 2 iterations: Address of Branch State (2 bit history, use T for taken and NT Target Instruction Instruction for not taken) Previous branch

1 2 3 4 5 6 7 8 9 10 11 12 13 14

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F004 (1st iteration) F006 FF03 F009 FF05 F00B F00C F004 (2nd iteration) F006 FF03 F009 FF05 F00B F00C

----------------------NT T T T T NT NT NT T T T T NT

previous to previous branch ----------------------------------------NT T T T T T NT NT T T T T

I3 JUMP F007 I8 JUMP F00A I10 JUMP F002 I3 I3 JUMP F007 I8 JUMP F00A I10 JUMP F002 I3

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