Em-unit-3

UNIT-3 DIGITAL ELECTRONICS

Topics v Binary number system v AND, OR, NOT, NAND, NOR circuits v Boolean algebra-Exclusive OR gate v Flip flops v Half and full adders v Registers-Counters v A/D and D/A conversion.

Binary Number System v Decimal system with its ten digits is a base-ten system. Similarly binary system with its two digits is a base-two system. The two binary digits (bits) a I and 0. v Like digital system, in binary system each binary digit commonly known bit, has its own value or weight. However in binary system weight is expressed as power of 2, as shown in Fig. 1.2.

Logic Gates v A logic gate (or logic circuit) is a digital circuit with one or more input signals, but only one output signet All input and output signals are either low voltages or high voltages. v A digital circuit is referred to as a logic gate for the simple reason that it can be analyzed on the basis of Boolean logic. v In Boolean algebra, the variables of an equation can take only two values, 0 and I. Thus irrespective of how many variables are involved, each variable has the value 0 or 1. v Two important operations on these variables are i) Boolean addition, and ii) Boolean multiplication. v The operation of OR gate can be illustrated with a beautiful example. Consider the circuit of fig.2-2. A and B are mechanical switches, and V is a lamp. Switches an evident A and lamp V lip. And B is connected in parallel. It is seen

that the lamp V lights up i) with a closed and Open ii) with B closed and an open, and iii) with both A and B closed. It is also that with both B open, the does not light

v Let a binary 0 indicate open switch and a binary 1 indicate closed switch. Also, let 0 indicate dark lamp, and I indicate bright lamp. The various possibilities of switching operations and state of the lamp are listed below.

2-input OR gate.

9.3 AND gate

v An AND gate can have any number of inputs, but has only one output the output is high only if all inputs are high. Even if one of the inputs is low, the output is low. v By input and output, we mean voltages.)Symbolically, a 2-input AND gate .

2- Input AND gate

v This statement is read as ‘V equals A AND B’. The (.) symbol indicates AND operation. It implies that V is high only if both A and B is high. If both A and B are low, V Is low. v Also, even if one of the inputs is low, V is low. Since there are 2 inputs, there are only 4 possibilities. These possibilities and the output in each case are listed above in the truth table [2-6 and 2-7]. v From the truth table 2-7, it is obvious that AND operation is Boolean multiplication. This Table gives the rules of AND operation (or Boolean multiplication as follows:

v The logic symbol of a 3-input AND gate .There are three inputs A, B and C, and there is only one output given as V = A. B. C. The truth table is as shown (Table 2.8).If there are more than 3-inputs at an AND gate, say 6 or 9- inputs, the gate is symbolically shown as in figs. 2.7 (a) and (b).

The operation of an AND with the following example. Gate can be beautifully illustrated

NOT gate or Inverter v This logic gate has only one input and only one output. The output is the complement of the input. The NOT gate is an inverter. If the input to the gate is high, the output is low, and if the input is low, the output is high. v If A = input and V = output, then V is the complement of A. It means that when A is low, V is high, and when A is high, V is low. The NOT operation is indicated by an over bar (-). Thus, in the present case,

NAND gate v A NAND gate is essentially an AND gate followed by a NOT gate (i.e. inverter). The output of a NAND gate is therefore NOT the AND of the Inputs. A NAND gate can have any number of inputs, but it has only one output. v We studied that the output of an AND gate is high only when all inputs are high. If this AND gate is followed by an inverter, the inverter output is low; since it is the complement of its input which is high. Hence, the output of a NAND gate is low, only when all inputs are high. The logic symbol of a 2-input NAND gate

v The triangle of fig. 2-13 (a) is deleted, and the bubble is moved to the AND gate output. The symbol shown in (b) is generally accepted as representing a WAND gate. v If one or more of the inputs, but not all the inputs, of an AND gate are low, we know that, the output is low. Hence the output of a NAND gate is high, if one or more (but not all) of the inputs are high. v Also, when all Inputs of a NANO gate are low, the output is high. Combining all cases considered above, it can be inferred that the output of a NAND gate is: i) Low, when alt inputs are high ii) High, when one or more or all of the inputs are low.

NOR gate v Not all, of the inputs of a NOR gate Thus the output of a NOR gate is A NOR gate can have any number . v A NOR gate is essentially an OR gate followed by a NOT gate (i.e. inverter). We studied that the output of an OR gate i.e. low only when all inputs are low. v Hence if this OR gate is followed by an inverter, its output would be high. Hence, the output of a NOR gate is high only when all Inputs are low. v If even one or more, but are high, the output is low. NOT the OR of the inputs .Of inputs, but it has only one output. v The logic symbol of a 2-input NOR gate is as shown in fig. 2-15 (b).

v Fig. 2-15 (b) shows the can be seen that, just like in of fig. (a) Is omitted and the the output of the OR gate. Standard symbol of a NOR gate. It the NAND gate symbol, the triangle bubble (or small circle) is moved. If one or more or all of the inputs of a NOR gate are high, its output is low. The truth table for a 2-input NOR gate is given below.

Exclusive OR gate or XOR gate v Consider the logic gate shown in fig. 2-17 (b). It is termed as an exclusive OR gate or XOR gate. v When the number of inputs is 2, the output of the gate Is high only if either of the inputs, but not both, Is high. v When both inputs are high, the output is low. Also, when both inputs are low, the output is low. v The XOR gate is built up of OR gate, AND gates and inverters as shown in fig. 217 (a).

Master-Slave SR Flip-Flop v A master-slave flip-flop is constructed from two flip-flops. One circuit serves as a master and the other as a slave, and the overall circuit is referred to as a masterslave flip-flop. v Fig. 5.27 shows SR master-slave flip-flop. It consists of a master flip-flop, a slave flip-flop, and an inverter. Both the flip-flops are positive level triggered, but

v The master-slave combination can be constructed for any type of flip Pig. 5.29 shows one way to build a JK master-slave flip-flop.

v It consists of clocked JK flip-flop as a master and clocked SR flip-flop as a slave. Like SR master-slave, the output of the master flip-flop is fed as an input to the slave flip-flop. v As shown in the Fig. 5.29, clock signal is connected directly to the master flip flop, but it is connected through inverter to the slave flip-flop. v Therefore, the information present at the I and K inputs is transmitted to the output of master flip-flop on the positive clock pulse and it is held there until the negative clock pulse occurs, after which it is allowed to pass through to the output of slave flip-flop. T v he output of the slave flip-flop is connected as a third input of the master JK flipflop. When J =1 and K = 0, the master sets on the positive clock. The high Y outputs of the master drives the S input of the slave, so at negative clock, slave sets, copying the action of the master. v When J = 0 and K = 1, the master resets on the positive clock. The high Y output of the master goes to the R input of the slave. Therefore, at the negative clock slave resets, again copying the action of the master. v When I = 1 and K = 1, master toggles on the positive clock and slave then copies the output of master on the negative clock. v At this instant, feedback inputs to the master flip-flop are complemented but as it is negative half of the clock pulse master flip-flop is inactive. v This prevents race around condition. Fig. 5.30 shows input and output waveforms of master-slave 1K flip-flop. JK Flip-Flop v The truth table and excitation table for JK flip-flop are shown in Table 5.22 (a) and (b) respectively. Let us examine each case.

v —÷ 0 Transition When both present state and next state are 0, the J input must remain at 0 and the K input can be either 0 and 1. v o —> 1 Transition : The present state is 0 and is to change to 1. This can happen either when J = 1 and K = 0 (set condition) or when J = K = 1 (toggle condition). v Thus,has to be 1, but K can be at either level for this transition to occur. v 1—+ 0 Transition The present state is I and is to change to a 0. This can happen either when J = 0 and K = I or when J = K = 1. Thus, K has to be 1 but J can be at either level. v 1 Transition When both present state and next are 1, the K input must remain While the J input can be 0 or 1. v As seen from Table 5.13, the excitation table for JK flip-flop has more don’t care conditions than the excitation table for RS flip-flop. v The don’t care terms usually simplify the function. Therefore, the combinational circuits using JK flip-flops for the input functions are likely to be simpler than those using RS flip-flops. D Flip-Flop v The Table 5.14 (a) and (b) show the truth table and excitation table for D flipflop, respectively. v In D flip-flop, the next state is always equal to the D input and it is independent of the present state. Therefore, D must be 0 if Q + i has to be 0, and 1 if

Half Adder v The half-adder operation needs two binary inputs augends and addend bits; and two binary outputs sum and carry. v The truth table shown in Table 4.2 gives the relation between input and output variables for half-adder operation.

Limitations of Half-Adder v In multi digit addition we have to add two bits along with the carry of previous digit addition. Effectively such addition requires addition of three bits. This is not possible with half adder. Hence half-adders are not used in practice. Full-Adder v A full-adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. v Two of the input variables, denoted by A and B, represent the two significant bits to be added. The third input represents the carry from the previous lower significant position. v The truth table for full-adder isShown in Table 4.3.

v A flip-flop can store 1-bit information. So an n-bit register has a group of n flipflops and is capable of storing any binary information/number containing n-bits. v Fig. 8.1 shows the simplest register constructed with four D flip-flops. This register is also called buffer register. Each D-flip-flop is triggered with a common negative edge clock pulse. The input X bits set up the flip-flops for loading.

Buffer register In this register, four D flip-flops are used. So it can store 4-bit binary information the

number of flip-flop stages in a register determines its total storage capacity.

v We can control input and output of the register by connecting tri-state devices at the input and output sides of register as shown in Fig. 8.2. So this register is called ‘controlled buffer register’. v Here, tri-state switches are used to control the When you want to store data in the register; you have to make LOAD or WR signal low to activate the tri-state buffers. v When you want the data at the output, you have to make RD signal low to activate the buffers. Controlled buffer registers are commonly used for temporary storage of data within a digital system. Shift Registers v The binary information (data) in a register can be moved from stage to stage within the register or into or out of the register upon application of clock pulses. v This type of bit movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. v This gives rise to a group of registers called ‘shift registers’. They are very important in applications involving the storage and transfer of data in a digital system. v The symbolical representations of the different types of movement in shift register operations.

Universal Shift Register v A register capable of shifting in one direction only is a unidirectional shift register. A register capable of shifting in both directions is a bidirectional shift register. v If the register has both shifts (right shift and left shift) and parallel load capabilities, it is referred to as Universal shift register. v The Fig. 8.3 shows the 4 bit universal shift register. It has all the capabilities listed above. It consists of four flip-flops and four multiplexers. v The ‘four multiplexes have two common selection inputs S and S and they select appropriate input for D Flip-flop. v The Table 8.2 shows the register operation depending on the selection inputs of multi WI .en S S = 00, input 0 is selected and the present value of the register is applied to the D inputs of the flip-flops. v This results no change in the register value. When S S 01, input 1 is selected and circuit connections are such that it operates as a right shift register. v When S = 10, input 2 is selected and circuit connections are such that it operates as a left shift register. Finally, when S = 11, the binary information on the parallel input lines is transferee into the, register simultaneously and it is a parallel’ load ‘operation.

Applications of Shift Registers v We have seen that primary use of shift register is temporary data storage a manipulations. Some of the common applications of shift registers are as discus below.

1. Delay Line v A serial-in-serial-out (SISO) shift register can be used to introduce time delay at digital signals. where N is the number of stages (i.e. flip-flops) and is the clock frequency. v Thus, an input pulse train appears at the output delayed by At. The amount delay can be controlled by the clock by the number of flip-flops in tri shift register. 2 .Serial-to-Parallel Converter v A serial-in-parallel-out (SIPO) shift register can be used to convert data in the sen. form to the parallel form. 3. Parallel-to-Serial Converter v A parallel-in-serial-out (PISO) shift register can be used to convert data in parallel form to the serial form. 4. Shift Register Counters v A shift register can also be used as a counter. A shift register with the serial connected back to the serial input is called shift register counter. Because of connection, special specified sequences are produced as the output. The most shift register counters are the ring counter and the Johnson counter. Ring Counter v Fig. 8.14 shows the logic diagram for ten-bit ring counter. As shown in the Fig.8.14, the Q output of each stage is connected to the D input of the next stage and the output of last stage is fed back to the input of first stage. v The CLR followed by PRE makes the output of first stage to ‘1’ and remaining outputs are zero v The first clock pulse produces QB = 1 and remaining outputs are zero. According to the clock pulses applied at the clock input CP, a sequence of ten states is produced. These states are summarized in Table.8.5.