Eee445 Fall2009 Syllabus

MIDDLE EAST TECHNICAL UNIVERSITY NORTHERN CYPRUS CAMPUS ELECTRICAL AND ELECTRONICS ENGINEERING PROGRAM EEE-445 (3-0)3

Fall-2009 COMPUTER ARCHITECTURE I

Instructor’s Name

Office

Phone

e-mail

ALİ MUHTAROĞLU

R-216

661 2933

[email protected]

Course Schedule: Office Hours :

T. 13:40–15:30 (S-105); Th. 9:40–10:30 (S-106) W. 9:00–10:30 or by appointment (R-216) th

Main Text:

Patterson&Hennessy, “Computer Organization and Design” (4 Ed.), Kaufmann, 2008. Will use plenty of lecture notes since no single text has the full coverage. th Auxiliary Text: Stallings, “Computer Organization & Architecture” (7 Ed.), Pearson, 2006. Mano & Kime, “Logic and Computer Design Fundamentals”, 4th Ed., Prentice Hall, 2008. Brown & Vranesic, “Fund. Of Dig. Logic with VHDL Design” (2nd Ed.), McGraw Hill, 2005. Catalog Description: Asynchronous logic system. Algorithmic state machines. CPU organization. Construction of arithmetic logic unit. Process control architectures. Instruction modalities. Microprogramming. Bit slicing. Prerequisite: EEE 248 or consent of the department. Course Objectives: We will learn about the components of a computer system organization, and instruction set architectures. We will build on the knowledge of microcontroller macro-coding from EEE 347, and study hardware and micro-programmed control for single- and multi-cycle datapath design. I/O organizations, asynchronous logic design concepts will be covered as time allows this term. EEE-446 (next term) will follow from where we left off. Those without EEE 347 background can take the course, but let the instructor know in advance. Course Outline (Tentative): Week #

Week Starts

LECTURE

HW Out 1

1 2 3

28-Sep 5-Oct 12-Oct

Intro. to Computer System Architecture and Organization Computer Components and Program Concept; Instructions Instruction Set Architecture Design

4 5 6 7 8 9 10

19-Oct 26-Oct 2-Nov 9-Nov 16-Nov 23-Nov 30-Nov

11 12 13 14 15 16 17

Note: Grading:

   

HW Due

2

1

Instruction Sets and Addressing Modes Addressing Modes; Program Control; Data Types Midterm #1; Sequential Design Review Fetch-Decode-Execute cycle Single-Cycle Datapath for Fetch-Decode-Execute Single-Cycle Datapath & Control for Fetch-Decode-Execute Multi-Cycle Datapath & Control Design

3

2

4

3

5

4

6

5

7-Dec 14-Dec 21-Dec 28-Dec 4-Jan 11-Jan

Microprogrammed Control Microprogrammed Control Examples Midterm #2; Input/Output Interrupts, Traps Buses; PCI example Final’s week

7

6

8

7

9

8

18-Jan

Final's week

9

No class on 29-10-09. Midterm 1 Midterm 2 Final H.W. + Attendance

: 20% : 25% : 35% : 20%

rd

Tentatively on November 3 in class nd Tentatively on December 22 in class Date/Time/Place To Be Determined Late assignments penalized 20% per week day

Brush up on C programming language and VHDL for homeworks/projects. Those who fail to follow the rules of academic honesty will fail the class. ALL course work should be completed independently. Attendance is higly recommended to do well in the class. Will use METU-Online to post HWs, Labs, solutions, lecture notes, announcements, etc.