Ecr Machine

Electronic Cash (Based on 89C51RD2 Register Microcontroller)

Under the supervision of

Mr. Arvind Toshniwal

(Arun Infotech Pvt. Ltd. Pune)

Ms. Preeti Salunkhe (ICIT Pvt. Ltd. Pune)

Presented by Gaurav Sharma Gopinath Sridara Mohit Kumar Rawat

AIM & OBJECTIVE Aim: Self-design and self-development of “Electronic Cash Register” with two user operating modes:  Printing Mode  Setup Mode Objective: Printing the bill for the customer in detailing about the purchases he/she made. Printing details are names of the items, quantity of the item, cost of the each item, Sub Total cost of the each item, & grand total with time, day & date of the purchase as well as welcome note & greetings.

OVERVIEW OF THIS PROJECT We have designed a Electronic Cash Register. We have selected 89C51RD2 microcontroller as a platform. So the interfacing modules (with microcontroller) of this ECR are as follows: Interfacing Modules Real Time Clock (RTC) EEPROM as a external memory (RTC & EEPROM both are interfaced with microcontroller over I2C Protocol.) LCD Display Keyboard over PS/2 Protocol Impact Printer We are also using Buzzer as a signaling device & 9V dc supply for Vcc with 9V dc Battery backup Circuit

BLOCK DIAGRAM Power Supply

Impact Printer

Battery Backup

Buzzer

89C51RD2 EEPROM

RTC I2C

Display Unit

Keyboard

MICROCONTROLLER 89C51RD2 Basic Features: 80C51 Central Processing Unit On-chip Flash Program Memory with ISP capability Boot ROM contains low level Flash programming routines for downloading via the UART 6 clocks per machine cycle operation (standard) 12 clocks per machine cycle operation (optional) RAM expandable externally to 64 kB 4 level priority interrupt 8 interrupt sources Four 8-bit I/O ports Full-duplex enhanced UART

What is I2C Protocol ?

I2C PROTOCOL Basic Characteristics of I2C Protocol Two-wired bus Serial data line (SDA) Serial clock line (SCL Originally to interact within small num. of devices Speeds: 100 kbps (standard mode) 400 kbps (fast mode) 3.4 Mbps (high-speed mode) Data transfers: serial, 8-bit oriented, bi-directional Master/slave relationships with multi-master option (arbitration) Master can operate as transmitter or receiver

BASIC FRAMES Start Condition SDA 1-0 transition when SCL = 1 Start data transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. ********************************************************************************************************

Stop Condition SDA 0-1 transition when SCL = 1

Stop data transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

Data Transfer on 2-Wire Serial Bus

SERIAL REAL TIME CLOCK (RTC) DS1307 (64 X 8)

DS1307 (64 X 8) SERIAL REAL TIME CLOCK FEATURES Real time clock counts seconds, minutes, hours, date, day of week, and year with leap year compensation valid up to 2100 56 byte nonvolatile RAM for data storage 2-wire serial interface Programmable square wave output signal Automatic power-fail detect and switch circuitry Low power consumption

Pin Assignment (DS1307 8-Pin DIP)

Pin Description VCC X1, X2 VBAT GND SDA SCL SQW/OUT

: : : : : : :

Primary Power Supply 32.768 kHz Crystal Connection +3V Battery Input Ground Serial Data Serial Clock Square wave/Output Driver

Control Register

OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square wave output is disabled. If SQWE=0, the logic level on the SQW/OUT pin is 1 if OUT=1 and is 0 if OUT=0. SQWE (Square Wave Enable): This bit, when set to logic 1, will enable the oscillator output. The freq. of the square wave output depends upon the value of the RS0 and RS1 bits. RS (Rate Select): These bits control the freq. of the square wave output when the square wave output has been enabled.

RTC AND RAM Address Map

DS1307 TIMEKEEPER REGISTERS

RTC READ

RTC Write

2-Wire Serial EEPROM 512K (65,536 x 8)

2-wire Serial EEPROM 512K (65,536 x 8) 

             

Low-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V) • Internally Organized 65,536 x 8 • 2-wire Serial Interface • Schmitt Triggers, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 128-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability – Endurance: 100,000 Write Cycles – Data Retention: 40 Years • Automotive Grade, Extended Temperature and Lead-free/Halogen-free •

LCD (HD44780) 16*2 Character Display

LCD Hitachi HD44780 

16x2 character by line display



The different instructions available for use with 44780 are -Clear Display -Return Cursor and LCD to Home Position -Set Cursor Move Direction -Enable Display/Cursor -Move Cursor/Shift Display -Set Interface Length -Move Cursor into CGRAM -Move Cursor to Display -Poll the "Busy Flag"

LCD Mc

Interfacing of PS/2 Keyboard (Over PS/2 Protocol)

PS/2 PROTOCOL Basic Characteristics of PS/2 Protocol The communication is binary, synchronous and serial based: Only two channels (CLOCK and DATA) are sufficient. Communication is two-sided: The Data and Clock lines are both open-collector with pull-up resistors to Vcc. The bus is "idle" when both lines are high (open-collector). This is the only state where the keyboard is allowed begin transmitting data. The host has ultimate control over the bus and may inhibit communication at any time by pulling the Clock line low. The device always generates the clock signal. Each key pressed causes a packet of data to be output by the encoder. Each data packet is output during 11 cycles of CLOCK, therefore can be interpreted to be containing 11 bits : 1 start bit (= 0), 8 data bits (one byte), 1 parity (= 0 or =1) and 1 stop (=1) bit

Summary: Bus States Data = high, Clock = high: Idle state. Data = high, Clock = low: Communication Inhibited. Data = low, Clock = high: Host Request-to-Send Communication: Device-to-Host The Data and Clock lines are both open collector. A resistor is connected between each line and +5V, so the idle state of the bus is high. When the keyboard wants to send information, it first checks the Clock line to make sure it's at a high logic level. If it's not, the host is inhibiting communication and the device must buffer any to-be-sent data until the host releases Clock. The Clock line must be continuously high for at least 50 microseconds before the device can begin to transmit its data. The keyboard writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low.

Device-to-host communication. The Data line changes state when Clock is high and that data is valid when Clock is low.

AND……………FINALLY!

HOW THE MAIN FUNCTION WORK?

Conclusion we successfully interface following devices with Microcontroller.      

Self development of I2c and PS/2 protocol RTC with I2C protocol EEPROM with I2C protocol keyboard with ps/2 protocol Program the 89c51RD2 for LCD display Send the data to serial port for Printer

T H A N K Y O U!