Ecil Report.docx

A Project Report On

BUILT IN ALARM SYSTEMS FOR HOME APPLICATIONS Submitted in partial fulfilment of the requirements for award of the degree of BACHELOR OF TECHNOLOGY In ELECTRONICS AND COMMUNICATION ENGINEERING By L.SAI PRANEETH REDDY (16311A04H7) Under the guidance of Dr.T. THIRUMALAI DGM, CED Of ECIL-ECIT ELECTRONICS CORPORATION OF INDIA LIMITED (A Government of India Enterprise)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING SREENIDHI INSTITUTE OF SCIENCE&TECHNOLOGY(AUTONOMOUS) Yamnampet, Ghatkesar, R.R District, Hyderabad – 501301(Affiliated to JNT University Hyderabad, Hyderabad and Approved by AICTE - New Delhi)

DECLARATION

We hereby declare that the project entitled BUILT IN ALARM SYSTEMS FOR HOME APPLICATIONS submitted in partial fulfilment of the requirements for the award of degree of Bachelor of Technology in Electronics and Communication Engineering. This dissertation is our original work and the project has not formed the basis for the award of any degree, associate ship, fellowship or any other similar titles and no part of it has been published or sent for the publication at the time of submission.

L.SAI PRANEETH REDDY(16311A04H7)

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ACKNOWLEDGEMENT We wish to take this opportunity to express our deep gratitude to all those who helped, encouraged, motivated and have extended their cooperation in various ways during our project work. It is our pleasure to acknowledgement the help of all those individuals who was responsible for foreseeing the successful completion of our project. We would like to thank Dr. T. THIRUMALAI (DGM, CED) and express our gratitude with great admiration and respect to our project guide Ms K. Siva Rama Lakshmi and Mr T. Naveen Kumar Reddy for their valuable advice and help throughout the development of this project by providing us with required information without whose guidance, cooperation and encouragement, this project couldn’t have been materialized. Last but not the least; we would like to thank the entire respondents for extending their help in all circumstances.

L.SAI PRANEETH REDDY(16311A04H7).

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CONTENTS 1. INTRODUCTION 1.1. Abstract

2. ORGANISATION PROFILE 3. INTRODUCTION TO VLSI 3.1. VLSI design flow 3.2. Design hierarchy 3.3. VLSI design styles 3.4. 3.3.1 FPGA

4 . LANGUAGE INTRODUCTION 5. PROJECT OVERVIEW 6. XILINX PROCEDURE 7. RTL SCHEMATIC 8. WAVEFORMS 9. CONCLUSION

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1. INTRODUCTION 1.1 ABSTRACT: In recent times, Field Programmable Gate Arrays have wide applications in market due to its advantage of having programmable interconnects. Alarm-system is the best solution to overcome house intrusion. The effective Alarm-system is available at low cost with which the user can built their own security system. In this project, we present the design and implementation of the alarm-system. The design has been described using VHDL and implemented in the hardware using FPGA (Field Programmable Gate Array). This is installed in the hardware by ISE project navigator, a software of Xilinx. The system is a four code system that runs on FPGA with the sensor to sense correct pattern for code and the alarm. The design involves a code-checker with which the system can change its states.

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2.ORGANIZATION PROFILE ECIL was setup under the department of Atomic Energy in the year 1967 with a view to generate a strong indigenous capability in the field of professional grade electronic. The initial accent was on self-reliance and ECIL was engaged in the Design Development Manufacture and Marketing of several products emphasis on three technology lines viz. Computers, control systems and communications. ECIL thus evolved as a multi-product company serving multiple sectors of Indian economy with emphasis on import of country substitution and development of products and services that are of economic and strategic significance to the country. Electronics Corporation of India Limited (ECIL) entered into collaboration with OSI Systems Inc. (www.osi-systems.com) and set up a joint venture "ECIL_RAPSICAN LIMITED". This Joint Venture manufacture the equipment’s manufactured by RAPSICAN, U.K, U.S.A with the same state of art Technology, Requisite Technology is supplied by RAPSICAN and the final product is manufactured at ECIL facility. Recognizing the need for generating quality IT professionals and to meet the growing demand of IT industry, a separate division namely CED has been established to impart quality and professional IT training under the brand name of ECIT. ECIT, the prestigious offshoot of ECIL is an emerging winner and is at the fore front of IT education in the country.

Mission ECIL’s mission is to consolidate its status as a valued national asset in the area of strategic electronics with specific focus on Atomic Energy, Defense, Security and such critical sectors of strategic national importance.

Objectives 

To continue services to the country’s needs for the peaceful uses Atomic Energy. Special and Strategic requirements of Defence and Space, Electronics Security System and Support for Civil aviation sector.



To establish newer Technology products such as Container Scanning Systems and Explosive Detectors. 6



To re-engineer the company to become nationally and internationally competitive by paying particular attention to delivery, cost and quality in all its activities.



To explore new avenues of business and work for growth in strategic sectors in addition to working realizing technological solutions for the benefit of society in areas like Agriculture, Education, Health, Power, Transportation, Food, Disaster Management etc.

Divisions The Company is organized into divisions serving various sectors, national and Commercial Importance. They are Divisions serving nuclear sector like Control & Automation Division (CAD), Instruments & Systems Division (ISD), Divisions Serving defence sector like Communications Division (CND), Antenna Products Division (APD), Servo Systems Division (SSD) etc., Divisions handling Commercial Products are Telecom Division (TCD), Customer Support Division (CSD), Computer Education Division (CED).

Exports ECIL is currently operating in major business EXPORT segments like Instruments and systems design, Industrial/Nuclear, Servo Systems, Antenna Products, Communication, Control and Automation and several other components.

Services The company played a very significant role in the training and growth of high calibre technical and managerial manpower especially in the fields of Computers and Information Technology. Though the initial thrust was on meeting the Control & Instrumentation requirements of the Nuclear Power Program, the expanded scope of self-reliance pursued by ECIL enabled the company to develop various products to cater to the needs of Defence, Civil Aviation, Information & Broadcasting, Tele communications, etc.

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3. INTRODUCTION TO VLSI The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale systems design - in short, due to the advent of VLSI. The number of applications of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power (or, in other words, the intelligence) of these applications is the driving force for the fast development of this field. Figure 1.1 gives an overview of the prominent trends in information technologies over the next few decades. The current leading-edge technologies (such as low bit-rate video and cellular communications) already provide the end-users a certain amount of processing power and portability.

This trend is expected to continue, with very important implications on VLSI and systems design. One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth (in order to handle real-time video, for example). The other important characteristic is that the information services tend to become more and more personalized (as opposed to collective services such as broadcasting), which means that the

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devices must be more intelligent to answer individual demands, and at the same time they must be portable to allow more flexibility/mobility As more and more complex functions are required in various data processing and telecommunications devices, the need to integrate these functions in a small system/package is also increasing. The level of integration as measured by the number of logic gates in a monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Table 1.1 shows the evolution of logic complexity in integrated circuits over the last three decades, and marks the milestones of each era. Here, the numbers for circuit complexity should be interpreted only as representative examples to show the order-of-magnitude. A logic block can contain anywhere from 10 to 100 transistors, depending on the function. State-of-the-art examples of ULSI chips, such as the DEC Alpha or the INTEL Pentium contain 3 to 6 million transistors. ERA

DATE

COMPLEXITY

Single transistor

1959

less than 1

Unit logic (one gate)

1960

1

Multi-function

1962

2-4

Complex function

1964

5 - 20

Medium Scale Integration

1967

20 - 200 (MSI)

Large Scale Integration

1972

200 - 2000

(LSI)

Very Large Scale Integration

1978

2000 - 20000

(VLSI)

Ultra Large Scale Integration

1989

20000 - ? (ULSI)

(number of logic blocks per chip)

Table-3.1: Evolution of logic complexity in integrated circuits.

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The most important message here is that the logic complexity per chip has been (and still is) increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides: 

Less area/volume and therefore, compactness

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Less power consumption



Less testing requirements at system level



Higher reliability, mainly due to improved on-chip interconnects



Higher speed, due to significantly reduced interconnection length



Significant cost savings

Figure-3.2: Evolution of integration density and minimum feature size, as seen in the early 1980s. Therefore, the current trend of integration will also continue in the foreseeable future. Advances in device manufacturing technology, and especially the steady reduction of minimum feature size (minimum length of a transistor or an interconnect realizable on chip) support this trend. Figure 1.2 shows the history and forecast of chip complexity - and minimum feature size 10

over time, as seen in the early 1980s. At that time, a minimum feature size of 0.3 microns was expected around the year 2000. The actual development of the technology, however, has far exceeded these expectations. A minimum size of 0.25 microns was readily achievable by the year 1995. As a direct result of this, the integration density has also exceeded previous expectations - the first 64 Mbit DRAM, and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available by 1994, pushing the envelope of integration density. When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips. Figure 1.3 shows the level of integration over time for memory and logic chips, starting in 1970. It can be observed that in terms of transistor count, logic chips contain significantly fewer transistors in any given year mainly due to large consumption of chip area for complex interconnects. Memory circuits are highly regular and thus more cells can be integrated with much less area for interconnects.

Figure-3.3: Level of integration over time, for memory chips and logic chips. Generally speaking, logic chips such as microprocessor chips and digital signal processing (DSP) chips contain not only large arrays of memory (SRAM) cells, but also many different functional units. As a result, their design complexity is considered much higher than that of memory chips, although advanced memory chips contain some sophisticated logic 11

functions. The design complexity of logic chips increases almost exponentially with the number of transistors to be integrated. This is translated into the increase in the design cycle time, which is the time period from the start of the chip development until the mask-tape delivery time. However, in order to make the best use of the current technology, the chip development time has to be short enough to allow the maturing of chip manufacturing and timely delivery to customers. As a result, the level of actual logic integration tends to fall short of the integration level achievable with the current processing technology. Sophisticated computer-aided design (CAD) tools and methodologies are developed and applied in order to manage the rapidly increasing design complexity.

3.1 VLSI Design Flow: The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not possible or too costly, then the revision of requirements and its impact analysis must be considered. The Y-chart (first introduced by D. Gajski) shown in Fig. 1.4 illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter Y.

Figure-3.4: Typical VLSI design flow in three domains (Y-chart representation). 12

The Y-chart consists of three major domains, namely: 

behavioral domain,



structural domain,



geometrical layout domain.

The design flow starts from the algorithm that describes the behavior of the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning. The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the interconnects area and signal delays. The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell placement & routing program. The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use.

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Figure-3.5: A more simplified view of VLSI design flow. Figure 1.5 provides a more simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market. Although the design process has been described in linear fashion for simplicity, in reality there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined. For instance, if a chip designer 14

defined an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated. Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels (bottom up) as early as possible. In the following, we will examine design methodologies and structured approaches which have been developed over the years to deal with both complex hardware and software projects. Regardless of the actual size of the project, the basic principles of structured design will improve the prospects of success. Some of the classical techniques for reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality.

3.2 Design Hierarchy: The use of hierarchy, or � divide and conquer� technique involves dividing a module into sub- modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. This approach is very similar to the software case where large programs are split into smaller and smaller sections until simple subroutines, with welldefined functions and interfaces, can be written. In Section 1.2, we have seen that the design of a VLSI chip can be represented in three domains. Correspondingly, a hierarchy structure can be described in each domain separately. However, it is important for the simplicity of design that the hierarchies in different domains can be mapped into each other easily. As an example of structural hierarchy, Fig. 1.6 shows the structural decomposition of a CMOS four-bit adder into its components. The adder can be decomposed progressively into onebit adders, separate carry and sum circuits, and finally, into individual logic gates. At this lower level of the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much more easier to handle than at the higher levels of the hierarchy.

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In the physical domain, partitioning a complex system into its various functional blocks will provide a valuable guidance for the actual realization of these blocks on chip. Obviously, the approximate shape and size (area) of each sub-module should be estimated in order to provide a useful floorplan. Figure 1.7 shows the hierarchical decomposition of a four-bit adder in physical description (geometrical layout) domain, resulting in a simple floorplan. This physical view describes the external geometry of the adder, the locations of input and output pins, and how pin locations allow some signals (in this case the carry signals) to be transferred from one sub-block to the other without external routing. At lower levels of the physical hierarchy, the internal mask

Figure-3.6: Structural decomposition of a four-bit adder circuit, showing the hierarchy down to gate level.

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Figure-3.7: Regular design of a 2-1 MUX, a DFF and an adder, using inverters and tri-state buffers.

3.3 VLSI Design Styles: Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to provide the functionality at low cost.

3.3.1 Field Programmable Gate Array (FPGA): Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable interconnects, are available to users for their custom hardware programming to realize desired functionality. This design style provides a means for fast prototyping and also for cost-effective chip design, especially for low-volume applications. A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures. The programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. A general architecture of FPGA from XILINX is shown in Fig. 3.8. A more detailed view showing the locations of switch matrices used for interconnect routing is given in Fig. 3.9. 17

A simple CLB (model XC2000 from XILINX) is shown in Fig. 3.10. It consists of four signal input terminals (A, B, C, D), a clock signal terminal, user-programmable multiplexers, an SR-latch, and a look-up table (LUT). The LUT is a digital memory that stores the truth table of the Boolean function. Thus, it can generate any function of up to four variables or any two functions of three variables. The control terminals of multiplexers are not shown explicitly in Fig. 3.10. The CLB is configured such that many different logic functions can be realized by programming its array. More sophisticated CLBs have also been introduced to map complex functions. The typical design flow of an FPGA chip starts with the behavioral description of its functionality, using a hardware description language such as VHDL. The synthesized architecture is then technology-mapped (or partitioned) into circuits or logic cells. At this stage, the chip design is completely described in terms of available logic cells. Next, the placement and routing step assigns individual logic cells to FPGA sites (CLBs) and determines the routing patterns among the cells in accordance with the netlist. After routing is completed, the on-chip

Figure-3.8: General architecture of Xilinx FPGAs.

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Figure-3.9: Detailed view of switch matrices and interconnection routing between CLBs.

Figure-3.10: XC2000 CLB of the Xilinx FPGA. Performance of the design can be simulated and verified before downloading the design for programming of the FPGA chip. The programming of the chip remains valid as long as the chip is powered-on, or until new programming is done. In most cases, full utilization of the FPGA chip area is not possible - many cell sites may remain unused. The largest advantage of FPGA-based design is the very short turn-around time, i.e., the time required from the start of the design process until a functional chip is available. Since no physical manufacturing step is necessary for customizing the FPGA chip, a functional sample can be obtained almost as soon as the design is mapped into a specific technology. The typical 19

price of FPGA chips are usually higher than other realization alternatives (such as gate array or standard cells) of the same design, but for small-volume production of ASIC chips and for fast prototyping, FPGA offers a very valuable option. Gate Array Design: In view of the fast prototyping capability, the gate array (GA) comes after the FPGA. While the design implementation of the FPGA chip is done with user programming, that of the gate array is done with metal mask design and processing. Gate array implementation requires a two-step manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These uncommitted chips can be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array (Fig. 3.11). Since the patterning of metallic interconnects is done at the end of the chip fabrication, the turn-around time can be still short, a few days to a few weeks.

Figure-3.11: Basic processing steps required for gate array implement The availability of these routing channels simplifies the interconnections, even using one metal layer only. The interconnection patterns to realize basic logic gates can be stored in a library, which can then be used to customize rows of uncommitted transistors according to the netlist. While most gate array platforms only contain rows of uncommitted transistors separated 20

by routing channels, some other platforms also offer dedicated memory (RAM) arrays to allow a higher density where memory functions are required. Figure 3.14 shows the layout views of a conventional gate array and a gate array platform with two dedicated memory banks. With the use of multiple interconnect layers, the routing can be achieved over the active cell areas; thus, the routing channels can be removed as in Sea-of-Gates (SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and pMOS transistors. As in the gate array case, neighboring transistors can be customized using a metal mask to form basic logic gates. For intercell routing, however, some of the uncommitted transistors must be sacrificed. This approach results in more flexibility for interconnections, and usually in a higher density. The basic platform of a SOG chip is shown in Fig. 1.19. Figure 1.20 offers a brief comparison between the channeled (GA) vs. the channelless (SOG) approaches.

Figure-3.13: Metal mask design to realize a complex logic function on a channeled GA platform. .

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Figure-3.15: The platform of a Sea-of-Gates (SOG) chip. In general, the GA chip utilization factor, as measured by the used chip area divided by the total chip area, is higher than that of the FPGA and so is the chip speed, since more customized design can be achieved with metal mask designs. The current gate array chips can implement as many as hundreds of thousands of logic gates.

Figure-3.16: Comparison between the channeled (GA) vs. the channelless (SOG) approaches. Standard-Cells Based Design The standard-cells based design is one of the most prevalent full custom design styles which require development of a full custom mask set. The standard cell is also called the polycell. In this design style, all of the commonly used logic cells are developed, characterized, and stored in 22

a standard cell library. A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops. Each gate type can have multiple implementations to provide adequate driving capability for different fanouts. For instance, the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors so that the chip designer can choose the proper size to achieve high circuit speed and layout density. The characterization of each cell is done for several different categories. It consists of 

delay time vs. load capacitance



circuit simulation model



timing simulation model



fault simulation model



cell data for place-and-route



mask data

To enable automated placement of the cells and routing of inter-cell connections, each cell layout is designed with a fixed height, so that a number of cells can be abutted side-by-side to form rows. The power and ground rails typically run parallel to the upper and lower boundaries of the cell, thus, neighboring cells share a common power and ground bus. If a number of cells must share the same input and/or output signals, a common signal bus structure can also be incorporated into the standard-cell-based chip layout. Figure 1.23 shows the simplified symbolic view of a case where a signal bus has been inserted between the rows of standard cells. Note that in this case the chip consists of two blocks, and power/ground routing must be provided from both sides of the layout area. Standard-cell based designs may consist of several such macro-blocks, each corresponding to a specific unit of the system architecture such as ALU, control logic, etc.

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In many VLSI chips, such as microprocessors and digital signal processing chips, standard-cells based design is used to implement complex control logic modules. Some full custom chips can be also implemented exclusively with standard cells. mask design is done anew without use of any library. However, the development cost of such a design style is becoming prohibitively high. Thus, the concept of design reuse is becoming popular in order to reduce design cycle time and development cost. The most rigorous full custom design can be the design of a memory cell, be it static or dynamic. Since the same layout design is replicated, there would not be any alternative to high density memory chip design. For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip, such as standard cells, data-path cells and PLAs. In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually by the designer, design productivity is usually very low - typically 10 to 20 transistors per day, per designer. In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, highperformance microprocessors and FPGA masters. Figure 3.21 shows the full layout of the Intel 486 microprocessor chip, which is a good example of a hybrid full-custom design. Here, one can identify four different design styles on one chip: Memory banks (RAM cache), data-path units consisting of bit-slice cells, control circuitry mainly consisting of standard cells and PLA blocks.

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Figure-3.21: Overview of VLSI design styles.

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4.VHDL INTRODUCTION VHDL is an acronym for Very high speed integrated circuit (VHSIC) Hardware Description Language which is a programming language that describes a logic circuit by function, data flow behaviour, and/or structure. This hardware description is used to configure a programmable logic device (PLD), such as a field programmable gate array (FPGA), with a custom logic design. The general format of a VHDL program is built around the concept of BLOCKS which are the basic building units of a VHDL design. Within these design blocks a logic circuit of function can be easily described. A VHDL design begins with an ENTITY block that describes the interface for the design. The interface defines the input and output l1ogic signals of the circuit being designed. The ARCHITECTURE block describes the internal operation of the design. Within these blocks are numerous other functional blocks used to build the design elements of the logic circuit being created. After the design is created, it can be simulated and synthesized to check its logical operation. SIMULATION is a bare bones type of test to see if the basic logic works according to design and concept. SYNTHESIS allows timing factors and other influences of actual field programmable gate array (FPGA) devices to effect the simulation thereby doing a more thorough type of check before the design is committed to the FPGA or similar device. 1.1 VHDL Application VHDL is used mainly for the development of Application Specific Integrated Circuits (ASICs). Tools for the automatic transformation of VHDL code into a gate-level net list were developed already at an early point of time. This transformation is called synthesis and is an integral part of current design flows. For the use with Field Programmable Gate Arrays (FPGAs) several problems exist. In the first step, Boolean equations are derived from the VHDL description, no matter, whether an ASIC or a FPGA is the target technology. But now, this Boolean code has to be partitioned into the configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an ASIC library. Another big problem is the routing of the CLBs as the available resources for interconnections are the bottleneck of current FPGAs. While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices(PLDs). VHDL can be applied to model system behaviour independently from the target technology. This is either useful to provide standard solutions, e.g. for micro controllers, error correction (de)coders, etc, or behavioural models of microprocessors and RAM devices are used to simulate a new device in its target environment. An ongoing field of research is the hardware/software co 26

design. The most interesting question is which part of the system should be implemented in software and which part in hardware. The decisive constraints are the costs and the resulting performance.

entity entity-name is [port(interface-signal-declaration);] end [entity] [entity-name]; architecture architecture-name of entity-name is [declarations] Begin architecture body end [architecture] [architecture-name]; 2.1 ENTITY BLOCK An entity block is the beginning building block of a VHDL design. Each design has only one entity block which describes the interface signals into and out of the design unit. The syntax for an entity declaration is: entity entity_name is port (signal_name,signal_name : mode type; signal_name,signal_name : mode type); 27

end entity_name; An entity block starts with the reserve word entity followed by the entity_name. Names and identifiers can contain letters, numbers, and the under score character, but must begin with an alpha character. Next is the reserved word is and then the port declarations. The indenting shown in the entity block syntax is used for documentation purposes only and is not required since VHDL is insensitive to white spaces. A single PORT declaration is used to declare the interface signals for the entity and to assign MODE and data TYPE to them. If more than one signal of the same type is declared, each identifier name is separated by a comma. Identifiers are followed by a colon (:), mode and data type selections. In general, there are five types of modes, but only three are frequently used. These three will be addressed here. They are in, out, and inout setting the signal flow direction for the ports as input, output, or bidirectional. Signal declarations of different mode or type are listed individually and separated by semicolons (;). The last signal declaration in a port statement and the port statement itself are terminated by a semicolon on the outside of the port's closing parenthesis. The entity declaration is completed by using an end operator and the entity name. Optionally, you can also use an end entity statement. In VHDL, all statements are terminated by a semicolon. Here is an example of an entity declaration for a set/reset (SR) latch: entity latch is port (s,r : in std_logic; q,nq : out std_logic); end latch; The set/reset latch has input control bits s and r which are define d as single input bits and output bits q and nq. Notice that the declaration does not define the operation yet, just the interfacing input and output logic signals of the design. A design circuit's operation will be defined in the architecture block. We can define a literal constant to be used within an entity with the generic declaration, which is placed before the port declaration within the entity block. Generic literals than can be used in port and other declarations. This makes it easier to modify or update designs. For instance if you declare a number of bit_vector bus signals, each eight bits in length, and at some future time you want to change them all to 16-bits, you would have to change each of the bit_vector range. However, by using a generic to define the range value, all you have to do is change the generic's value and the change will be reflected in each of the bit_vectors defined by that generic. The syntax to define a generic is: generic (name : type := value); 28

The reserved word generic defines the declaration statement. This is followed by an identifier name for the generic and a colon. Next is the data type and a literal assignment value for the identifier. := is the assignment operator that allows a literal value to be assigned to the generic identifier name. This operator is used for other assignment functions as we will see later. For example, here is the code to define a bus width size using a generic literal. entity my processor is generic (busWidth : integer := 7); Presently, busWidth has the literal value of 7. This makes the documentation more descriptive for a vector type in a port declaration: port( data_bus : in std_logic_vector (busWidth downto 0); q-out : out std_logic_vector (busWidth downto 0)); In this example, data_bus and q_out have a width of eight (8) bits ( 7 down to 0). When the design is updated to a larger bus size of sixteen (16) bits, the only change is to the literal assignment in the generic declaration from 7 to 15 . 2.2 ARCHITECTURE BLOCK The architecture block defines how the entity operates. This may be described in many ways, two of which are most prevalent: STRUCTURE and DATA FLOW and BEHAVIOR formats. The BEHAVIOR approach describes the actual logic behavior of the circuit. This is generally in the form of a Boolean expression or process. The STRUCTURE approach defines how the entity is structured - what logic devices make up the circuit or design. The general syntax for the architecture block is: architecture arch_name of entity_name is declarations; begin statements defining operation; 29

end arch_name; example, we will use the set/reset NOR latch of figure 1. In VHDL code listings, -- (double dash) indicates a comment line used for documentation and ignored by the compiler.

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library ieee; use ieee.std_logic_1164.all; -- entity block entity latch is -- interface signal declarations port (s,r : in std_logic; q,nq : out std_logic); end latch; -- architecture block architecture flipflop of latch is begin -- assignment statements q <= r nor nq; nq <= s nor q; 31

end flipflop; The first two lines imports the IEEE standard logic library std_logic_1164 which contains predefined logic functions and data types such as std_logic and std_logic_vector. The use statement determines which portions of a library file to use. In this example we are selecting all of the items in the 1164 library. The next block is the entity block which declares the latch's interface inputs, r and s and outputs q and nq. This is followed by the architecture block which begins by identifying itself with the name flipflop as a description of entity latch. Within the architecture block's body (designated by the begin reserved word) are two assignment statements. Signal assignment statements follow the general syntax of: signal_identifier_name <= expression; The <= symbol is the assignment operator for assigning a value to a signal. This differs from the := assignment operator used to assign an initial literal value to generic identifier used earlier. In our latch example, the state of the signal q is assigned the logic result of the nor function using input signals r and nq. The nor operator is defined in the IEEE std_logic_1164 library as a standard VHDL function to perform the nor logic operation. Through the use of Boolean expressions, the operation of the NOR latch's behavior is described and translated by a VHDL compiler into the hardware function appearing in figure 1.

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5.PROJECT OVERVIEW INTRODUCTION TO FLIP FLOPS: In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops and latches are used as data storage elements. A flip-flop is a device which stores a single bit (binary digit) of data; one of its two states represents a "one" and the other represents a "zero". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches. Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.

TYPES OF FLIP FLOPS:    

SR FLIP FLOP JK FLIP FLOP D FLIP FLOP T FLIP FLOP

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D FLIP-FLOP

D flip-flop symbol The D flip-flop is widely used. It is also known as a "data" or "delay" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line. Truth table: Clock

D Qnext

Rising edge 0

0

Rising edge 1

1

Non-Rising X

Q

('X' denotes a Don't care condition, meaning the signal is irrelevant) Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used as described above. Here is the truth table for the others S and R possible configurations: Inputs

Outputs

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S R D > Q

Q'

0 1

X

X 0

1

1 0

X

X 1

0

1 1

X

X 1

1

4-bit serial-in, parallel-out (SIPO) shift register

These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. The advantage of the D flip-flop over the Dtype "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. An exception is that some flip-flops have a "reset" signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock. The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock. The input X is shifted into the leftmost bit position. Classical positive-edge-triggered D flip-flop

A positive-edge-triggered D flip-flop This circuit consists of two stages implemented by SR NAND latches. The input stage (the two latches on the left) processes the clock and data signals to ensure correct input 35

signals for the output stage (the single latch on the right). If the clock is low, both the output signals of the input stage are high regardless of the data input; the output latch is unaffected and it stores the previous state. When the clock signal changes from low to high, only one of the output voltages (depending on the data signal) goes low and sets/resets the output latch: if D = 0, the lower output becomes low; if D = 1, the upper output becomes low. If the clock signal continues staying high, the outputs keep their states regardless of the data input and force the output latch to stay in the corresponding state as the input logical zero (of the output stage) remains active while the clock is high. Hence the role of the output latch is to store the data only while the clock is low. The circuit is closely related to the gated D latch as both the circuits convert the two D input states (0 and 1) to two input combinations (01 and 10) for the output SR latch by inverting the data input signal (both the circuits split the single D signal in two complementary S and Rsignals). The difference is that in the gated D latch simple NAND logical gates are used while in the positive-edge-triggered D flip-flop SRNAND latches are used for this purpose. The role of these latches is to "lock" the active output producing low voltage (a logical zero); thus the positive-edge-triggered D flip-flop can also be thought of as a gated D latch with latched input gates. Master–slave edge-triggered D flip-flop

A master–slave D flip-flop. It responds on the falling edge of the enable input (usually a clock)

An implementation of a master–slave D flip-flop that is triggered on the rising edge of the clock A master–slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called master–slave because the second latch in the series only changes in response to a change in the first (master) latch. For a positive-edge triggered master–slave D flip-flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is 36

high (logical 1). This allows the "master" latch to store the input value when the clock signal transitions from low to high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now "locked" master latch to pass through the "slave" latch. When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge. By removing the leftmost inverter in the circuit at side, a D-type flip-flop that strobes on the falling edge of a clock signal can be obtained. This has a truth table like this: D Q

>

Qnext

0 X Falling

0

1 X Falling

1

A CMOS IC implementation of a "true single-phase edge-triggered flip-flop with reset"

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Dual-edge-triggered D flip-flop

An implementation of a master–slave D flip-flop that is triggered on the rising edge of the clock Flip-Flops that read in a new value on the rising and the falling edge of the clock are called dual-edge-triggered flip-flops. Such a flip-flop may be built using two singleedge -triggered D-type flip-flops and a multiplexer as shown in the image.

Circuit symbol of a dual-edge-triggered D flip-flop. Edge-triggered dynamic D storage element An efficient functional alternative to a D flip-flop can be made with dynamic circuits (where information is stored in a capacitance) as long as it is clocked often enough; while not a true flip-flop, it is still called a flip-flop for its functional role. While the master–slave D element is triggered on the edge of a clock, its components are each triggered by clock levels. The "edge-triggered D flip-flop", as it is called even though it is not a true flip-flop, does not have the master–slave properties. Edge-triggered D flip-flops are often implemented in integrated high-speed operations using dynamic logic. This means that the digital output is stored on parasitic device capacitance while the device is not transitioning. This design of dynamic flip flops also enables simple resetting since the reset operation can be performed by simply discharging one or more internal nodes. A common dynamic flip-flop variety is the true single-phase clock (TSPC) type which performs the flipflop operation with little power and at high speeds. However, dynamic flip-flops will typically not work at static or low clock speeds: given enough time, leakage paths may discharge the parasitic capacitance enough to cause the flip-flop to enter invalid states. 38

6. XILINX PROCEDURE ISE 13.2i Quick Start procedure The ISE 13.2i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of the basic design process using ISE 13.2i. After you have completed the tutorial, you will have an understanding of how to create, verify, and implement a design. Note: This tutorial is designed for ISE 13.2i on Windows. This procedure contains the following sections: • “Getting Started” • “Create a New Project” • “Create an HDL Source” • “Design Simulation” • “Create Timing Constraints” • “Implement Design and Verify Constraints” • “Reimplement Design and Verify Pin Locations” • “Download Design to the Spartan™-3 Demo Board” For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/

Getting Started Software Requirements: 39

To use this tutorial, you must install the following software: • ISE 13.2i For more information about installing Xilinx® software, see the ISE Release Notes and

Hardware Requirements: To use this tutorial, you must have the following hardware: • Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board Starting the ISE Software To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting: Start → All Programs → Xilinx ISE → Project Navigator Note: Your start-up path is set during the installation process and may differ from the one above. Accessing Help At any time during the tutorial, you can access online help for additional information about the ISE software and related tools. To open Help, do either of the following: • Press F1 to view Help for the specific tool or function that you have selected or 40

Highlighted. • Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

ISE Help Topics

Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3e Startup Kit demo board. To create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 41

4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: ♦ Product Category: All ♦ Family: Spartan3E ♦ Device: XC3S500E ♦ Package: FG320 ♦ Speed Grade: -4 ♦ Top-Level Module Type: HDL ♦ Synthesis Tool: XST (VHDL/Verilog) ♦ Simulator: ISE Simulator (VHDL/Verilog) ♦ Verify that Enable Enhanced Design Summary is selected. Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:

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Project Device Properties 7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.

Create a Verilog HDL Source In this section, I will create the a example top-level Verilog HDL file Creating a Verilog Source Create the top-level Verilog source file as follows: 1. Click New Source in the New Project dialog box. 2. Select Verilog Module as the source type in the New Source dialog box. 3. Type in the file name counter. 4. Verify that the Add to Project checkbox is selected. 5. Click Next. 43

6. Declare the ports for the counter design by filling in the port information as shown below:

Define Module 7. Click Next, then Finish in the New Source Information dialog box to complete the new source file template. 8. Click Next, then Next, then Finish.

The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below:

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New Project in ISE

Using Language Templates (Verilog) The next step in creating the new source is to add the behavioral description for counter. Use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement. 2. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible. 3. Using the “+” symbol, browse to the following code example: Verilog → Synthesis Constructs → Coding Examples → Counter → Binary → Up/Down Counters → Simple Counter 45

4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.

Final Editing of the Verilog Source 1. To declare and initialize the register that stores the counter value, modify the declaration statement in the first line of the template as follows: replace: reg [:0] ; with: reg [3:0] count_int = 0; 2. Customize the template for the counter design by replacing the port and signal name placeholders with the actual ones as follows: ♦ replace all occurrences of with CLOCK ♦ replace all occurrences of with DIRECTION ♦ replace all occurrences of with count_int 3. Add the following line just above the endmodule statement to assign the register value to the output port: assign COUNT_OUT = count_int; 4. Save the file by selecting File → Save. When you are finished, the code for the counter will look like the following: module counter(CLOCK, DIRECTION, COUNT_OUT); input CLOCK; 46

input DIRECTION; output [3:0] COUNT_OUT; reg [3:0] count_int = 0; always @(posedge CLOCK) if (DIRECTION) count_int <= count_int + 1; else count_int <= count_int - 1; assign COUNT_OUT = count_int; endmodule You have now created the Verilog source for the tutorial project.

Checking the Syntax of the New Counter Module When the source files are complete, check the syntax of the design to find errors and typos. 1. Verify that Synthesis/Implementation is selected from the drop-down list in the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window. 3. Click the “+” next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process. 47

Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design. 5. Close the HDL file.

Design Simulation Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows: 1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project → New Source. 3. In the New

Source Wizard, select Verilog test fixture as the source type, and type

counter_tbw in

the File Name field.

4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. 7. Save the waveform. 8. Close the test bench waveform.

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7. RTL SCHEMATIC Programme:

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Schematic:

50

8. WAVE FORMS

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9. CONCLUSION In our project, we use Field Programmable Gate Arrays which have wide applications in market due to its advantage of having programmable interconnects. Alarm-system is the best solution to overcome house intrusion. The effective Alarm-system is available at low cost with which the user can built their own security system. In this project, we present the design and implementation of the alarm-system. The design has been described using VHDL and implemented in the hardware using FPGA (Field Programmable Gate Array). This is installed in the hardware by ISE project navigator, a software of Xilinx. The system is a four code system that runs on FPGA with the sensor to sense correct pattern for code and the alarm. The design involves a code-checker with which the system can change its states.

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