6.002
CIRCUITS AND ELECTRONICS
Digital Circuit
6.002 Fall 2000
Lecture
13
1
Review vI
R
vI + –
VI
+ vC –
C
t
0
vC (0 ) = VO vC = VI + (VO − VI ) e
−t RC
1
vC VI
VO RC
6.002 Fall 2000
time constant RC t
Lecture
13
2
Let’s apply the result to an inverter. B
A X
First, rising delay tr at B
VS
VS
A vA 5V
0 1 Æ 0 at A
6.002 Fall 2000
B CGS
X t
Lecture
13
3
First, rising delay tr at B VS
A
VS
B vA 5V
CGS
X
0 1 Æ 0 at A
t
vB
5V
ideal observed
t
0
6.002 Fall 2000
Lecture
13
4
First, rising delay tr at B VS
A vA 5V
VS
B CGS
X
0 1 Æ 0 at A
t 5V VOH
rising delay of X
6.002 Fall 2000
Lecture
vB
0
tr
13
t
5
Equivalent circuit for 0Æ1 at B
vI = VS
RL
+ –
vI = VS vB (0 ) = 0
From
CGS
+ vB –
for t ≥ 0
1 vB = VS + (0 − VS ) e
−t RL CGS
Now, we need to find t for which vB = VOH .
6.002 Fall 2000
Lecture
13
6
Or vOH = VS − VS e
Find tr : VS e
−t r RL CGS
−t RL CGS
= VS − VOH
VS − VOH − tr = ln RL CGS VS
VS − VOH t r = − RL CGS ln VS
6.002 Fall 2000
Lecture
13
7
Or vOH = VS − VS e
Find tr : VS e
−t r RL CGS
−t RL CGS
= VS − VOH
VS − VOH − tr = ln RLCGS VS VS − VOH t r = − RL CGS ln VS e.g.
RL = 1K
VS = 5V
CGS = 0.1 pF
VOH = 4V
t r = −1 × 10 × 0.1 × 10 3
= 0.16 ns
−12
5−4 ln 5
RC = 0.1 ns ! 6.002 Fall 2000
Lecture
13
8
Falling Delay tf Falling delay tf is the t for which vB falls to VOL
Equivalent circuit for 1 Æ 0 at B vB (0 ) = VS (5V )
RL
VS + –
CGS
RON
+ vB –
X
6.002 Fall 2000
Lecture
13
9
Falling Delay tf
Equivalent circuit for 1 Æ 0 at B vB (0 ) = VS (5V )
RL
VS + – RON
CGS
+ vB –
CGS
+ vB –
X Thévenin replacement … RTH
VTH + –
RTH = RL || RON VTH 6.002 Fall 2000
RON = VS RON + RL Lecture
13
10
From
1 vB = VTH + (VS − VTH ) e
−t RTH CGS
Falling decay tf is the t for which vB falls to VOL −t f
VOL = VTH + (VS − VTH ) e RTH CGS or
VOL − VTH t f = − RTH CGS ln VS − VTH
6.002 Fall 2000
Lecture
13
11
t f = − RTH CGS ln
e.g.
RL = 1K
VS = 5V
CGS = 0.1 pF RTH ≈ 10Ω,
VOL − VTH VS − VTH RON = 10Ω
VOL = 1V
VTH ≈ 0V
t f = −10 ⋅ 0.1 ⋅10 = 1.6 ps
−12
1 ln 5
RC = 1 ps !
6.002 Fall 2000
Lecture
13
12
For recitation: Slow may be better
Problem
chip
pin 2 pin 1
v CL
v:
ideal
observed
slow!
So the engineers decided to speed it up…
RL RON
6.002 Fall 2000
made RL small made RON small
Lecture
13
13
For recitation: Slow may be better
Problem
chip
pin 2 pin 1
v CL
v:
ideal
…
observed
slow!
but, disaster!
v:
observed expected
6.002 Fall 2000
VIL
Lecture
13
14
Why? Consider Case
1
…
Demo
R1
pin1
R0 ok
6.002 Fall 2000
Lecture
13
15
Why? Consider Case 2
…
Demo
CP
R1
pin1
pin2
R0
R2
crosstalk! CP
R model for crosstalk:
+ v
+ –
–
6.002 Fall 2000
Lecture
13
16
Case 3
…
6.002 expert saw the solution R1
CP
R0
R2
+ –
slower transitions!
Detailed analysis in recitation.
6.002 Fall 2000
Lecture
13
17