Digital Abstraction

6.002

CIRCUITS AND ELECTRONICS

The Digital Abstraction

6.002 Fall 2000

Lecture 4

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Review z Discretize matter by agreeing to

observe the lumped matter discipline

Lumped Circuit Abstraction zAnalysis tool kit: KVL/KCL, node method, superposition, Thévenin, Norton (remember superposition, Thévenin, Norton apply only for linear circuits)

6.002 Fall 2000

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Today

Discretize value

Digital abstraction

Interestingly, we will see shortly that the tools learned in the previous three lectures are sufficient to analyze simple digital circuits

Reading: Chapter 5 of Agarwal & Lang

6.002 Fall 2000

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But first, why digital? In the past … Analog signal processing R1 V0

R2

V1 + –

V1

and V2 might represent the outputs of two sensors, for example.

+ –

V2

By superposition, V0 =

R2 R1 V1 + V2 R1 + R2 R1 + R2

If R1 = R 2 , V0 =

V1 + V2 2

The above is an “adder” circuit. 6.002 Fall 2000

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Noise Problem t

add noise on this wire

Receiver: huh?

…

noise hampers our ability to distinguish between small differences in value — e.g. between 3.1V and 3.2V.

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Value Discretization Restrict values to be one of two HIGH

LOW

5V

0V

TRUE

FALSE

1

0

…like two digits

0 and 1

Why is this discretization useful? (Remember, numbers larger than 1 can be represented using multiple binary digits and coding, much like using multiple decimal digits to represent numbers greater than 9. E.g., the binary number 101 has decimal value 5.)

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Digital System sender

noise VN

VS

VR

VN = 0V

receiver

VS

VR

5V “0” “1” “0” HIGH

“0” “1” “0” 5V

t

2.5V

0V

LOW

0V

t

2.5V

With noise

VS

VN = 0.2V

“0” “1” “0” 5V

“0” “1” “0”

0.2V

t

2.5V

VS

t

t

2.5V

0V 6.002 Fall 2000

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Digital System

Better noise immunity Lots of “noise margin” For “1”: noise margin 5V to 2.5V = 2.5V For “0”: noise margin 0V to 2.5V = 2.5V

6.002 Fall 2000

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Voltage Thresholds and Logic Values

5V

1

1

sender 0

1 2.5V receiver

0

0 0V

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But, but, but … What about 2.5V? Hmmm… create “no man’s land” or forbidden region For example, 5V

1 sender

3V 2V

0

1

VH

forbidden region

receiver

VL

0

0V

“1”

V

“0”

0V

6.002 Fall 2000

H

Lecture 4

5V V

L 10

But, but, but …

Where’s the noise margin? What if the sender sent 1:

VH ?

Hold the sender to tougher standards! 5V 1

V 0H

1 V IH

sender

V IL

0

receiver 0

V 0L

0V

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But, but, but …

Where’s the noise margin? What if the sender sent 1:

VH ?

Hold the sender to tougher standards! 5V 1

V 0H

1

sender

Noise margins

V IH

receiver

V IL

0

0

V 0L

0V “1” noise margin: V

- V

“0” noise margin:

-

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Lecture 4

IH V IL

0H V 0L 12

5V V 0H V IH V IL V 0L 0V

5V V 0H V IH V IL V 0L 0V

0

1

0

1

sender

t

0

1

0

1

receiver

t

Digital systems follow static discipline: if inputs to the digital system meet valid input thresholds, then the system guarantees its outputs will meet valid output thresholds. 6.002 Fall 2000

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Processing digital signals Recall, we have only two values —

1,0

Map naturally to logic: T, F Can also represent numbers

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Processing digital signals Boolean Logic If X is true and Y is true Then Z is true else Z is false. Z = X AND Y

X, Y, Z are digital signals “0” , “1”

Z = X • Y Boolean equation X Y

AND gate

Z

Truth table representation: X Y Z 0 0 1 1

0 1 0 1

0 0 0 1

Enumerate all input combinations 6.002 Fall 2000

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Combinational gate abstraction „ Adheres to static discipline „ Outputs are a function of

inputs alone.

Digital logic designers do not have to care about what is inside a gate.

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Demo

X

Y

Z Noise X Y

Z

Z = X • Y 6.002 Fall 2000

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Examples for recitation X

t Y

t Z

t Z = X • Y 6.002 Fall 2000

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In recitation… Another example of a gate If (A is true) OR (B is true) then C is true else C is false C = A + B A B

Boolean equation OR C

OR gate

More gates B

B Inverter

X Y

Z NAND

Z = X • Y

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Boolean Identities X X X X

• 1 = X • 0 = X + 1 = 1 +0 = X

1 = 0 0 = 1 AB + AC = A • (B + C)

Digital Circuits Implement: B C

output = A + B • C B•C output

A

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